[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / armada-375.dtsi

/*
 * Device Tree Include file for Marvell Armada 375 family SoC
 *
 * Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 375 family SoC";
	compatible = "marvell,armada375";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		serial0 = &uart0;
		serial1 = &uart1;
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <2000000000>;
		};
		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-375-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	soc {
		compatible = "marvell,armada375-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&gic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
				cache-unified;
				cache-level = <2>;
			};

			scu@c000 {
				compatible = "arm,cortex-a9-scu";
				reg = <0xc000 0x58>;
			};

			timer@c600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xc600 0x20>;
				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			gic: interrupt-controller@d000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				#size-cells = <0>;
				interrupt-controller;
				reg = <0xd000 0x1000>,
				      <0xc100 0x100>;
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0xc0054 0x4>;
				clocks = <&gateclk 19>;
			};

			/* Network controller */
			ethernet@f0000 {
				compatible = "marvell,armada-375-pp2";
				reg = <0xf0000 0xa000>, /* Packet Processor regs */
				      <0xc0000 0x3060>, /* LMS regs */
				      <0xc4000 0x100>,  /* eth0 regs */
				      <0xc5000 0x100>;  /* eth1 regs */
				clocks = <&gateclk 3>, <&gateclk 19>;
				clock-names = "pp_clk", "gop_clk";
				status = "disabled";

				eth0: eth0@c4000 {
					interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <0>;
					status = "disabled";
				};

				eth1: eth1@c5000 {
					interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <1>;
					status = "disabled";
				};
			};

			rtc@10300 {
				compatible = "marvell,orion-rtc";
				reg = <0x10300 0x20>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			};

			spi0: spi@10600 {
				compatible = "marvell,orion-spi";
				reg = <0x10600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			spi1: spi@10680 {
				compatible = "marvell,orion-spi";
				reg = <0x10680 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl {
				compatible = "marvell,mv88f6720-pinctrl";
				reg = <0x18000 0x24>;

				i2c0_pins: i2c0-pins {
					marvell,pins = "mpp14",  "mpp15";
					marvell,function = "i2c0";
				};

				i2c1_pins: i2c1-pins {
					marvell,pins = "mpp61",  "mpp62";
					marvell,function = "i2c1";
				};

				nand_pins: nand-pins {
					marvell,pins = "mpp0", "mpp1", "mpp2",
						"mpp3", "mpp4", "mpp5",
						"mpp6", "mpp7", "mpp8",
						"mpp9", "mpp10", "mpp11",
						"mpp12", "mpp13";
					marvell,function = "nand";
				};

				sdio_pins: sdio-pins {
					marvell,pins = "mpp24",  "mpp25", "mpp26",
						     "mpp27", "mpp28", "mpp29";
					marvell,function = "sd";
				};

				spi0_pins: spi0-pins {
					marvell,pins = "mpp0",  "mpp1", "mpp4",
						     "mpp5", "mpp8", "mpp9";
					marvell,function = "spi0";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			};

			system-controller@18200 {
				compatible = "marvell,armada-375-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-375-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			usbcluster: usb-cluster@18400 {
				compatible = "marvell,armada-375-usb-cluster";
				reg = <0x18400 0x4>;
				#phy-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>;
			};

			mpic: interrupt-controller@20a00 {
				compatible = "marvell,mpic";
				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			timer@20300 {
				compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
						      <&mpic 5>,
						      <&mpic 6>;
				clocks = <&coreclk 0>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			watchdog@20300 {
				compatible = "marvell,armada-375-wdt";
				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
				clocks = <&coreclk 0>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x10>;
			};

			coherency-fabric@21010 {
				compatible = "marvell,armada-375-coherency-fabric";
				reg = <0x21010 0x1c>;
			};

			usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 18>;
				phys = <&usbcluster PHY_TYPE_USB2>;
				phy-names = "usb";
				status = "disabled";
			};

			usb@54000 {
				compatible = "marvell,orion-ehci";
				reg = <0x54000 0x500>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 26>;
				status = "disabled";
			};

			usb3@58000 {
				compatible = "marvell,armada-375-xhci";
				reg = <0x58000 0x20000>,<0x5b880 0x80>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 16>;
				phys = <&usbcluster PHY_TYPE_USB3>;
				phy-names = "usb";
				status = "disabled";
			};

			xor@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60A00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor00 {
					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 23>;
				status = "okay";

				xor10 {
					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			sata@a0000 {
				compatible = "marvell,orion-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 14>, <&gateclk 20>;
				clock-names = "0", "1";
				status = "disabled";
			};

			nand@d0000 {
				compatible = "marvell,armada370-nand";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 11>;
				status = "disabled";
			};

			mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};

			thermal@e8078 {
				compatible = "marvell,armada375-thermal";
				reg = <0xe8078 0x4>, <0xe807c 0x8>;
				status = "okay";
			};

			coreclk: mvebu-sar@e8204 {
				compatible = "marvell,armada-375-core-clock";
				reg = <0xe8204 0x04>;
				#clock-cells = <1>;
			};

			coredivclk: corediv-clock@e8250 {
				compatible = "marvell,armada-375-corediv-clock";
				reg = <0xe8250 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};
		};

		pcie-controller {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;

			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

		};
	};
};
Commit	Line	Data
4de59085 GC	1	/*
	2	* Device Tree Include file for Marvell Armada 375 family SoC
	3	*
	4	* Copyright (C) 2014 Marvell
	5	*
	6	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	7	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	8	*
b89cfa65 GC	9	* This file is dual-licensed: you can use it either under the terms
	10	* of the GPL or the X11 license, at your option. Note that this dual
	11	* licensing only applies to this file, and not this project as a
	12	* whole.
	13	*
	14	* a) This file is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of the
	17	* License, or (at your option) any later version.
	18	*
	19	* This file is distributed in the hope that it will be useful
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* Or, alternatively
	25	*
	26	* b) Permission is hereby granted, free of charge, to any person
	27	* obtaining a copy of this software and associated documentation
	28	* files (the "Software"), to deal in the Software without
	29	* restriction, including without limitation the rights to use
	30	* copy, modify, merge, publish, distribute, sublicense, and/or
	31	* sell copies of the Software, and to permit persons to whom the
	32	* Software is furnished to do so, subject to the following
	33	* conditions:
	34	*
	35	* The above copyright notice and this permission notice shall be
	36	* included in all copies or substantial portions of the Software.
	37	*
	38	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	39	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	40	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	41	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	42	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	43	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	44	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	45	* OTHER DEALINGS IN THE SOFTWARE.
4de59085 GC	46	*/
4de59085 GC	47
a2be1561	48	#include "skeleton.dtsi"
f327d43d	49	#include <dt-bindings/interrupt-controller/arm-gic.h>
d11548e3	50	#include <dt-bindings/interrupt-controller/irq.h>
623394de	51	#include <dt-bindings/phy/phy.h>
4de59085 GC	52
	53	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
	54
	55	/ {
	56	model = "Marvell Armada 375 family SoC";
	57	compatible = "marvell,armada375";
	58
	59	aliases {
	60	gpio0 = &gpio0;
	61	gpio1 = &gpio1;
	62	gpio2 = &gpio2;
bf6acf16 TP	63	serial0 = &uart0;
bf6acf16 TP	64	serial1 = &uart1;
4de59085 GC	65	};
	66
	67	clocks {
	68	/* 2 GHz fixed main PLL */
	69	mainpll: mainpll {
	70	compatible = "fixed-clock";
	71	#clock-cells = <0>;
	72	clock-frequency = <2000000000>;
	73	};
9a27b449 EG	74	/* 25 MHz reference crystal */
	75	refclk: oscillator {
	76	compatible = "fixed-clock";
	77	#clock-cells = <0>;
	78	clock-frequency = <25000000>;
	79	};
4de59085 GC	80	};
	81
	82	cpus {
	83	#address-cells = <1>;
	84	#size-cells = <0>;
42eae5a4 GC	85	enable-method = "marvell,armada-375-smp";
42eae5a4 GC	86
4de59085 GC	87	cpu@0 {
	88	device_type = "cpu";
	89	compatible = "arm,cortex-a9";
	90	reg = <0>;
	91	};
	92	cpu@1 {
	93	device_type = "cpu";
	94	compatible = "arm,cortex-a9";
	95	reg = <1>;
	96	};
	97	};
	98
	99	soc {
a9e274c4	100	compatible = "marvell,armada375-mbus", "simple-bus";
4de59085 GC	101	#address-cells = <2>;
	102	#size-cells = <1>;
	103	controller = <&mbusc>;
	104	interrupt-parent = <&gic>;
	105	pcie-mem-aperture = <0xe0000000 0x8000000>;
	106	pcie-io-aperture = <0xe8000000 0x100000>;
	107
	108	bootrom {
	109	compatible = "marvell,bootrom";
	110	reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
	111	};
	112
	113	devbus-bootcs {
	114	compatible = "marvell,mvebu-devbus";
	115	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	116	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	117	#address-cells = <1>;
	118	#size-cells = <1>;
	119	clocks = <&coreclk 0>;
	120	status = "disabled";
	121	};
	122
	123	devbus-cs0 {
	124	compatible = "marvell,mvebu-devbus";
	125	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	126	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	127	#address-cells = <1>;
	128	#size-cells = <1>;
	129	clocks = <&coreclk 0>;
	130	status = "disabled";
	131	};
	132
	133	devbus-cs1 {
	134	compatible = "marvell,mvebu-devbus";
	135	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	136	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	137	#address-cells = <1>;
	138	#size-cells = <1>;
	139	clocks = <&coreclk 0>;
	140	status = "disabled";
	141	};
	142
	143	devbus-cs2 {
	144	compatible = "marvell,mvebu-devbus";
	145	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	146	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	147	#address-cells = <1>;
	148	#size-cells = <1>;
	149	clocks = <&coreclk 0>;
	150	status = "disabled";
	151	};
	152
	153	devbus-cs3 {
	154	compatible = "marvell,mvebu-devbus";
	155	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
	156	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
	157	#address-cells = <1>;
	158	#size-cells = <1>;
	159	clocks = <&coreclk 0>;
	160	status = "disabled";
	161	};
	162
	163	internal-regs {
	164	compatible = "simple-bus";
165	#address-cells = <1>;
166	#size-cells = <1>;
167	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
168
169	L2: cache-controller@8000 {
170	compatible = "arm,pl310-cache";
171	reg = <0x8000 0x1000>;
172	cache-unified;
173	cache-level = <2>;
174	};
175
6a8a57f2 TP	176	scu@c000 {
	177	compatible = "arm,cortex-a9-scu";
	178	reg = <0xc000 0x58>;
	179	};
	180
4de59085 GC	181	timer@c600 {
	182	compatible = "arm,cortex-a9-twd-timer";
	183	reg = <0xc600 0x20>;
d11548e3	184	interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING \| GIC_CPU_MASK_SIMPLE(2))>;
4de59085 GC	185	clocks = <&coreclk 2>;
	186	};
	187
	188	gic: interrupt-controller@d000 {
	189	compatible = "arm,cortex-a9-gic";
	190	#interrupt-cells = <3>;
	191	#size-cells = <0>;
	192	interrupt-controller;
	193	reg = <0xd000 0x1000>,
	194	<0xc100 0x100>;
	195	};
	196
ff10e2cd EG	197	mdio {
	198	#address-cells = <1>;
	199	#size-cells = <0>;
	200	compatible = "marvell,orion-mdio";
	201	reg = <0xc0054 0x4>;
112dc53d	202	clocks = <&gateclk 19>;
ff10e2cd EG	203	};
	204
	205	/* Network controller */
	206	ethernet@f0000 {
	207	compatible = "marvell,armada-375-pp2";
	208	reg = <0xf0000 0xa000>, /* Packet Processor regs */
	209	<0xc0000 0x3060>, /* LMS regs */
	210	<0xc4000 0x100>, /* eth0 regs */
	211	<0xc5000 0x100>; /* eth1 regs */
	212	clocks = <&gateclk 3>, <&gateclk 19>;
	213	clock-names = "pp_clk", "gop_clk";
	214	status = "disabled";
	215
	216	eth0: eth0@c4000 {
	217	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	218	port-id = <0>;
	219	status = "disabled";
	220	};
	221
	222	eth1: eth1@c5000 {
	223	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	224	port-id = <1>;
	225	status = "disabled";
	226	};
	227	};
	228
dd2d62df GC	229	rtc@10300 {
	230	compatible = "marvell,orion-rtc";
	231	reg = <0x10300 0x20>;
	232	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	233	};
	234
4de59085 GC	235	spi0: spi@10600 {
	236	compatible = "marvell,orion-spi";
	237	reg = <0x10600 0x50>;
	238	#address-cells = <1>;
	239	#size-cells = <0>;
	240	cell-index = <0>;
d11548e3	241	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	242	clocks = <&coreclk 0>;
	243	status = "disabled";
	244	};
	245
	246	spi1: spi@10680 {
	247	compatible = "marvell,orion-spi";
	248	reg = <0x10680 0x50>;
	249	#address-cells = <1>;
	250	#size-cells = <0>;
	251	cell-index = <1>;
d11548e3	252	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	253	clocks = <&coreclk 0>;
	254	status = "disabled";
	255	};
	256
	257	i2c0: i2c@11000 {
	258	compatible = "marvell,mv64xxx-i2c";
	259	reg = <0x11000 0x20>;
	260	#address-cells = <1>;
	261	#size-cells = <0>;
d11548e3	262	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	263	timeout-ms = <1000>;
	264	clocks = <&coreclk 0>;
	265	status = "disabled";
	266	};
	267
	268	i2c1: i2c@11100 {
	269	compatible = "marvell,mv64xxx-i2c";
	270	reg = <0x11100 0x20>;
	271	#address-cells = <1>;
	272	#size-cells = <0>;
d11548e3	273	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	274	timeout-ms = <1000>;
	275	clocks = <&coreclk 0>;
	276	status = "disabled";
	277	};
	278
43e58e90	279	uart0: serial@12000 {
4de59085 GC	280	compatible = "snps,dw-apb-uart";
	281	reg = <0x12000 0x100>;
	282	reg-shift = <2>;
d11548e3	283	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4de59085	284	reg-io-width = <1>;
64939dc5	285	clocks = <&coreclk 0>;
4de59085 GC	286	status = "disabled";
	287	};
	288
43e58e90	289	uart1: serial@12100 {
4de59085 GC	290	compatible = "snps,dw-apb-uart";
	291	reg = <0x12100 0x100>;
	292	reg-shift = <2>;
d11548e3	293	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4de59085	294	reg-io-width = <1>;
64939dc5	295	clocks = <&coreclk 0>;
4de59085 GC	296	status = "disabled";
	297	};
	298
	299	pinctrl {
	300	compatible = "marvell,mv88f6720-pinctrl";
	301	reg = <0x18000 0x24>;
	302
	303	i2c0_pins: i2c0-pins {
	304	marvell,pins = "mpp14", "mpp15";
	305	marvell,function = "i2c0";
	306	};
	307
	308	i2c1_pins: i2c1-pins {
	309	marvell,pins = "mpp61", "mpp62";
	310	marvell,function = "i2c1";
	311	};
	312
	313	nand_pins: nand-pins {
	314	marvell,pins = "mpp0", "mpp1", "mpp2",
	315	"mpp3", "mpp4", "mpp5",
	316	"mpp6", "mpp7", "mpp8",
	317	"mpp9", "mpp10", "mpp11",
	318	"mpp12", "mpp13";
	319	marvell,function = "nand";
	320	};
	321
	322	sdio_pins: sdio-pins {
	323	marvell,pins = "mpp24", "mpp25", "mpp26",
	324	"mpp27", "mpp28", "mpp29";
	325	marvell,function = "sd";
	326	};
	327
	328	spi0_pins: spi0-pins {
	329	marvell,pins = "mpp0", "mpp1", "mpp4",
	330	"mpp5", "mpp8", "mpp9";
	331	marvell,function = "spi0";
	332	};
	333	};
	334
	335	gpio0: gpio@18100 {
	336	compatible = "marvell,orion-gpio";
	337	reg = <0x18100 0x40>;
	338	ngpios = <32>;
	339	gpio-controller;
	340	#gpio-cells = <2>;
	341	interrupt-controller;
	342	#interrupt-cells = <2>;
d11548e3 TP	343	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	344	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	345	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	346	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	347	};
	348
	349	gpio1: gpio@18140 {
	350	compatible = "marvell,orion-gpio";
	351	reg = <0x18140 0x40>;
	352	ngpios = <32>;
	353	gpio-controller;
	354	#gpio-cells = <2>;
	355	interrupt-controller;
	356	#interrupt-cells = <2>;
d11548e3 TP	357	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	358	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	359	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	360	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	361	};
	362
	363	gpio2: gpio@18180 {
	364	compatible = "marvell,orion-gpio";
	365	reg = <0x18180 0x40>;
	366	ngpios = <3>;
	367	gpio-controller;
	368	#gpio-cells = <2>;
	369	interrupt-controller;
	370	#interrupt-cells = <2>;
d11548e3	371	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	372	};
	373
	374	system-controller@18200 {
	375	compatible = "marvell,armada-375-system-controller";
	376	reg = <0x18200 0x100>;
	377	};
	378
	379	gateclk: clock-gating-control@18220 {
	380	compatible = "marvell,armada-375-gating-clock";
	381	reg = <0x18220 0x4>;
	382	clocks = <&coreclk 0>;
	383	#clock-cells = <1>;
	384	};
	385
90eed0ee GC	386	usbcluster: usb-cluster@18400 {
	387	compatible = "marvell,armada-375-usb-cluster";
	388	reg = <0x18400 0x4>;
	389	#phy-cells = <1>;
	390	};
	391
4de59085 GC	392	mbusc: mbus-controller@20000 {
	393	compatible = "marvell,mbus-controller";
	394	reg = <0x20000 0x100>, <0x20180 0x20>;
	395	};
	396
24c2573b	397	mpic: interrupt-controller@20a00 {
4de59085 GC	398	compatible = "marvell,mpic";
	399	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	400	#interrupt-cells = <1>;
	401	#size-cells = <1>;
	402	interrupt-controller;
	403	msi-controller;
d11548e3	404	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	405	};
	406
	407	timer@20300 {
	408	compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
	409	reg = <0x20300 0x30>, <0x21040 0x30>;
d11548e3 TP	410	interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	411	<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	412	<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	413	<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
4de59085 GC	414	<&mpic 5>,
4de59085 GC	415	<&mpic 6>;
9a27b449 EG	416	clocks = <&coreclk 0>, <&refclk>;
9a27b449 EG	417	clock-names = "nbclk", "fixed";
4de59085 GC	418	};
4de59085 GC	419
13dacc56 EG	420	watchdog@20300 {
	421	compatible = "marvell,armada-375-wdt";
	422	reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
9a27b449 EG	423	clocks = <&coreclk 0>, <&refclk>;
9a27b449 EG	424	clock-names = "nbclk", "fixed";
13dacc56 EG	425	};
13dacc56 EG	426
42eae5a4 GC	427	cpurst@20800 {
	428	compatible = "marvell,armada-370-cpu-reset";
	429	reg = <0x20800 0x10>;
	430	};
	431
6a8a57f2 TP	432	coherency-fabric@21010 {
	433	compatible = "marvell,armada-375-coherency-fabric";
	434	reg = <0x21010 0x1c>;
	435	};
	436
57dc7971 GC	437	usb@50000 {
	438	compatible = "marvell,orion-ehci";
	439	reg = <0x50000 0x500>;
	440	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	441	clocks = <&gateclk 18>;
623394de GC	442	phys = <&usbcluster PHY_TYPE_USB2>;
623394de GC	443	phy-names = "usb";
57dc7971 GC	444	status = "disabled";
	445	};
	446
	447	usb@54000 {
	448	compatible = "marvell,orion-ehci";
	449	reg = <0x54000 0x500>;
	450	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	451	clocks = <&gateclk 26>;
	452	status = "disabled";
	453	};
	454
e8f99c5b GC	455	usb3@58000 {
	456	compatible = "marvell,armada-375-xhci";
	457	reg = <0x58000 0x20000>,<0x5b880 0x80>;
	458	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	459	clocks = <&gateclk 16>;
623394de GC	460	phys = <&usbcluster PHY_TYPE_USB3>;
623394de GC	461	phy-names = "usb";
e8f99c5b GC	462	status = "disabled";
	463	};
	464
4de59085 GC	465	xor@60800 {
	466	compatible = "marvell,orion-xor";
	467	reg = <0x60800 0x100
	468	0x60A00 0x100>;
	469	clocks = <&gateclk 22>;
	470	status = "okay";
	471
	472	xor00 {
d11548e3	473	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	474	dmacap,memcpy;
	475	dmacap,xor;
	476	};
	477	xor01 {
d11548e3	478	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	479	dmacap,memcpy;
	480	dmacap,xor;
	481	dmacap,memset;
	482	};
	483	};
	484
	485	xor@60900 {
	486	compatible = "marvell,orion-xor";
	487	reg = <0x60900 0x100
	488	0x60b00 0x100>;
	489	clocks = <&gateclk 23>;
	490	status = "okay";
	491
	492	xor10 {
d11548e3	493	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	494	dmacap,memcpy;
	495	dmacap,xor;
	496	};
	497	xor11 {
d11548e3	498	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	499	dmacap,memcpy;
	500	dmacap,xor;
	501	dmacap,memset;
	502	};
	503	};
	504
	505	sata@a0000 {
	506	compatible = "marvell,orion-sata";
	507	reg = <0xa0000 0x5000>;
d11548e3	508	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	509	clocks = <&gateclk 14>, <&gateclk 20>;
	510	clock-names = "0", "1";
	511	status = "disabled";
	512	};
	513
	514	nand@d0000 {
	515	compatible = "marvell,armada370-nand";
	516	reg = <0xd0000 0x54>;
	517	#address-cells = <1>;
	518	#size-cells = <1>;
d11548e3	519	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	520	clocks = <&gateclk 11>;
	521	status = "disabled";
	522	};
	523
	524	mvsdio@d4000 {
	525	compatible = "marvell,orion-sdio";
	526	reg = <0xd4000 0x200>;
d11548e3	527	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	528	clocks = <&gateclk 17>;
	529	bus-width = <4>;
	530	cap-sdio-irq;
	531	cap-sd-highspeed;
	532	cap-mmc-highspeed;
	533	status = "disabled";
f672e481 EG	534	};
	535
	536	thermal@e8078 {
	537	compatible = "marvell,armada375-thermal";
	538	reg = <0xe8078 0x4>, <0xe807c 0x8>;
	539	status = "okay";
4de59085 GC	540	};
	541
	542	coreclk: mvebu-sar@e8204 {
	543	compatible = "marvell,armada-375-core-clock";
	544	reg = <0xe8204 0x04>;
	545	#clock-cells = <1>;
	546	};
	547
	548	coredivclk: corediv-clock@e8250 {
	549	compatible = "marvell,armada-375-corediv-clock";
	550	reg = <0xe8250 0xc>;
	551	#clock-cells = <1>;
	552	clocks = <&mainpll>;
	553	clock-output-names = "nand";
	554	};
	555	};
	556
	557	pcie-controller {
	558	compatible = "marvell,armada-370-pcie";
	559	status = "disabled";
	560	device_type = "pci";
	561
	562	#address-cells = <3>;
	563	#size-cells = <2>;
	564
	565	msi-parent = <&mpic>;
	566	bus-range = <0x00 0xff>;
	567
	568	ranges =
	569	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
	570	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
	571	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
	572	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
	573	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
	574	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
	575
	576	pcie@1,0 {
	577	device_type = "pci";
	578	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	579	reg = <0x0800 0 0 0 0>;
	580	#address-cells = <3>;
	581	#size-cells = <2>;
	582	#interrupt-cells = <1>;
	583	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	584	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	585	interrupt-map-mask = <0 0 0 0>;
d11548e3	586	interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	587	marvell,pcie-port = <0>;
	588	marvell,pcie-lane = <0>;
	589	clocks = <&gateclk 5>;
	590	status = "disabled";
	591	};
	592
	593	pcie@2,0 {
	594	device_type = "pci";
	595	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	596	reg = <0x1000 0 0 0 0>;
	597	#address-cells = <3>;
	598	#size-cells = <2>;
	599	#interrupt-cells = <1>;
	600	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	601	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	602	interrupt-map-mask = <0 0 0 0>;
d11548e3	603	interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	604	marvell,pcie-port = <0>;
	605	marvell,pcie-lane = <1>;
	606	clocks = <&gateclk 6>;
	607	status = "disabled";
	608	};
	609
	610	};
	611	};
	612	};