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0d3d96ab TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 380 SoC. | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | */ | |
14 | ||
a2be1561 | 15 | #include "armada-38x.dtsi" |
0d3d96ab TP |
16 | |
17 | / { | |
18 | model = "Marvell Armada 380 family SoC"; | |
19 | compatible = "marvell,armada380", "marvell,armada38x"; | |
20 | ||
21 | cpus { | |
22 | #address-cells = <1>; | |
23 | #size-cells = <0>; | |
24 | cpu@0 { | |
25 | device_type = "cpu"; | |
26 | compatible = "arm,cortex-a9"; | |
27 | reg = <0>; | |
28 | }; | |
29 | }; | |
30 | ||
31 | soc { | |
32 | internal-regs { | |
33 | pinctrl { | |
34 | compatible = "marvell,mv88f6810-pinctrl"; | |
35 | reg = <0x18000 0x20>; | |
36 | }; | |
37 | }; | |
38 | ||
39 | pcie-controller { | |
40 | compatible = "marvell,armada-370-pcie"; | |
41 | status = "disabled"; | |
42 | device_type = "pci"; | |
43 | ||
44 | #address-cells = <3>; | |
45 | #size-cells = <2>; | |
46 | ||
47 | msi-parent = <&mpic>; | |
48 | bus-range = <0x00 0xff>; | |
49 | ||
50 | ranges = | |
51 | <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | |
52 | 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | |
53 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | |
54 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 | |
55 | 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ | |
56 | 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ | |
57 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ | |
58 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ | |
59 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ | |
60 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; | |
61 | ||
62 | /* x1 port */ | |
63 | pcie@1,0 { | |
64 | device_type = "pci"; | |
65 | assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; | |
66 | reg = <0x0800 0 0 0 0>; | |
67 | #address-cells = <3>; | |
68 | #size-cells = <2>; | |
69 | #interrupt-cells = <1>; | |
70 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
71 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
72 | interrupt-map-mask = <0 0 0 0>; | |
f327d43d | 73 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>; |
0d3d96ab TP |
74 | marvell,pcie-port = <0>; |
75 | marvell,pcie-lane = <0>; | |
76 | clocks = <&gateclk 8>; | |
77 | status = "disabled"; | |
78 | }; | |
79 | ||
80 | /* x1 port */ | |
81 | pcie@2,0 { | |
82 | device_type = "pci"; | |
83 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
84 | reg = <0x1000 0 0 0 0>; | |
85 | #address-cells = <3>; | |
86 | #size-cells = <2>; | |
87 | #interrupt-cells = <1>; | |
88 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
89 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
90 | interrupt-map-mask = <0 0 0 0>; | |
f327d43d | 91 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>; |
0d3d96ab TP |
92 | marvell,pcie-port = <1>; |
93 | marvell,pcie-lane = <0>; | |
94 | clocks = <&gateclk 5>; | |
95 | status = "disabled"; | |
96 | }; | |
97 | ||
98 | /* x1 port */ | |
99 | pcie@3,0 { | |
100 | device_type = "pci"; | |
101 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | |
102 | reg = <0x1000 0 0 0 0>; | |
103 | #address-cells = <3>; | |
104 | #size-cells = <2>; | |
105 | #interrupt-cells = <1>; | |
106 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | |
107 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | |
108 | interrupt-map-mask = <0 0 0 0>; | |
f327d43d | 109 | interrupt-map = <0 0 0 0 &gic GIC_SPI 70 0x4>; |
0d3d96ab TP |
110 | marvell,pcie-port = <2>; |
111 | marvell,pcie-lane = <0>; | |
112 | clocks = <&gateclk 6>; | |
113 | status = "disabled"; | |
114 | }; | |
115 | }; | |
116 | }; | |
117 | }; |