[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / armada-385-db-ap.dts

/*
 * Device Tree file for Marvell Armada 385 Access Point Development board
 * (DB-88F6820-AP)
 *
 *  Copyright (C) 2014 Marvell
 *
 * Nadav Haklai <nadavh@marvell.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is licensed under the terms of the GNU General Public
 *     License version 2.  This program is licensed "as is" without
 *     any warranty of any kind, whether express or implied.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "armada-385.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell Armada 385 Access Point Development Board";
	compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";

	chosen {
		bootargs = "console=ttyS0,115200";
		stdout-path = &uart1;
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x80000000>; /* 2GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;

		internal-regs {
			spi1: spi@10680 {
				pinctrl-names = "default";
				pinctrl-0 = <&spi1_pins>;
				status = "okay";

				spi-flash@0 {
					#address-cells = <1>;
					#size-cells = <1>;
					compatible = "st,m25p128";
					reg = <0>; /* Chip select 0 */
					spi-max-frequency = <54000000>;
				};
			};

			i2c0: i2c@11000 {
				pinctrl-names = "default";
				pinctrl-0 = <&i2c0_pins>;
				status = "okay";

				/*
				 * This bus is wired to two EEPROM
				 * sockets, one of which holding the
				 * board ID used by the	bootloader.
				 * Erasing this EEPROM's content will
				 * brick the board.
				 * Use this bus with caution.
				 */
			};

			mdio@72004 {
				pinctrl-names = "default";
				pinctrl-0 = <&mdio_pins>;

				phy0: ethernet-phy@1 {
					reg = <1>;
				};

				phy1: ethernet-phy@4 {
					reg = <4>;
				};

				phy2: ethernet-phy@6 {
					reg = <6>;
				};
			};

			/* UART0 is exposed through the JP8 connector */
			uart0: serial@12000 {
				pinctrl-names = "default";
				pinctrl-0 = <&uart0_pins>;
				status = "okay";
			};

			/*
			 * UART1 is exposed through a FTDI chip
			 * wired to the mini-USB connector
			 */
			uart1: serial@12100 {
				pinctrl-names = "default";
				pinctrl-0 = <&uart1_pins>;
				status = "okay";
			};

			ethernet@30000 {
				status = "okay";
				phy = <&phy2>;
				phy-mode = "sgmii";
			};

			ethernet@34000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "sgmii";
			};

			ethernet@70000 {
				pinctrl-names = "default";

				/*
				 * The Reference Clock 0 is used to
				 * provide a clock to the PHY
				 */
				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};
		};

		pcie-controller {
			status = "okay";

			/*
			 * The three PCIe units are accessible through
			 * standard mini-PCIe slots on the board.
			 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			pcie@2,0 {
				/* Port 1, Lane 0 */
				status = "okay";
			};

			pcie@3,0 {
				/* Port 2, Lane 0 */
				status = "okay";
			};
		};
	};
};
Commit	Line	Data
e5ee1281 MR	1	/*
	2	* Device Tree file for Marvell Armada 385 Access Point Development board
	3	* (DB-88F6820-AP)
	4	*
	5	* Copyright (C) 2014 Marvell
	6	*
	7	* Nadav Haklai <nadavh@marvell.com>
	8	*
	9	* This file is dual-licensed: you can use it either under the terms
	10	* of the GPL or the X11 license, at your option. Note that this dual
	11	* licensing only applies to this file, and not this project as a
	12	* whole.
	13	*
	14	* a) This file is licensed under the terms of the GNU General Public
	15	* License version 2. This program is licensed "as is" without
	16	* any warranty of any kind, whether express or implied.
	17	*
	18	* Or, alternatively,
	19	*
	20	* b) Permission is hereby granted, free of charge, to any person
	21	* obtaining a copy of this software and associated documentation
	22	* files (the "Software"), to deal in the Software without
	23	* restriction, including without limitation the rights to use,
	24	* copy, modify, merge, publish, distribute, sublicense, and/or
	25	* sell copies of the Software, and to permit persons to whom the
	26	* Software is furnished to do so, subject to the following
	27	* conditions:
	28	*
	29	* The above copyright notice and this permission notice shall be
	30	* included in all copies or substantial portions of the Software.
	31	*
	32	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	33	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	34	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	35	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	36	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	37	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	38	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	39	* OTHER DEALINGS IN THE SOFTWARE.
	40	*/
	41
	42	/dts-v1/;
	43	#include "armada-385.dtsi"
	44
	45	#include <dt-bindings/gpio/gpio.h>
	46
	47	/ {
	48	model = "Marvell Armada 385 Access Point Development Board";
	49	compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
	50
	51	chosen {
	52	bootargs = "console=ttyS0,115200";
	53	stdout-path = &uart1;
	54	};
	55
	56	memory {
	57	device_type = "memory";
	58	reg = <0x00000000 0x80000000>; /* 2GB */
	59	};
	60
	61	soc {
	62	ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
	63	MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
	64
65	internal-regs {
66	spi1: spi@10680 {
67	pinctrl-names = "default";
68	pinctrl-0 = <&spi1_pins>;
69	status = "okay";
70
71	spi-flash@0 {
72	#address-cells = <1>;
73	#size-cells = <1>;
74	compatible = "st,m25p128";
75	reg = <0>; /* Chip select 0 */
76	spi-max-frequency = <54000000>;
77	};
78	};
79
80	i2c0: i2c@11000 {
81	pinctrl-names = "default";
82	pinctrl-0 = <&i2c0_pins>;
83	status = "okay";
84
85	/*
86	* This bus is wired to two EEPROM
87	* sockets, one of which holding the
88	* board ID used by the bootloader.
89	* Erasing this EEPROM's content will
90	* brick the board.
91	* Use this bus with caution.
92	*/
93	};
94
95	mdio@72004 {
96	pinctrl-names = "default";
97	pinctrl-0 = <&mdio_pins>;
98
99	phy0: ethernet-phy@1 {
100	reg = <1>;
101	};
102
103	phy1: ethernet-phy@4 {
104	reg = <4>;
105	};
106
107	phy2: ethernet-phy@6 {
108	reg = <6>;
109	};
110	};
111
112	/* UART0 is exposed through the JP8 connector */
113	uart0: serial@12000 {
114	pinctrl-names = "default";
115	pinctrl-0 = <&uart0_pins>;
116	status = "okay";
117	};
118
119	/*
120	* UART1 is exposed through a FTDI chip
121	* wired to the mini-USB connector
122	*/
123	uart1: serial@12100 {
124	pinctrl-names = "default";
125	pinctrl-0 = <&uart1_pins>;
126	status = "okay";
127	};
128
129	ethernet@30000 {
130	status = "okay";
131	phy = <&phy2>;
132	phy-mode = "sgmii";
133	};
134
135	ethernet@34000 {
136	status = "okay";
137	phy = <&phy1>;
138	phy-mode = "sgmii";
139	};
140
141	ethernet@70000 {
142	pinctrl-names = "default";
143
144	/*
145	* The Reference Clock 0 is used to
146	* provide a clock to the PHY
147	*/
148	pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
149	status = "okay";
150	phy = <&phy0>;
151	phy-mode = "rgmii-id";
152	};
153	};
154
155	pcie-controller {
156	status = "okay";
157
158	/*
159	* The three PCIe units are accessible through
160	* standard mini-PCIe slots on the board.
161	*/
162	pcie@1,0 {
163	/* Port 0, Lane 0 */
164	status = "okay";
165	};
166
167	pcie@2,0 {
168	/* Port 1, Lane 0 */
169	status = "okay";
170	};
171
172	pcie@3,0 {
173	/* Port 2, Lane 0 */
174	status = "okay";
175	};
176	};
177	};
178	};