[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / armada-388-clearfog.dtsi

/*
 * Device Tree include file for SolidRun Clearfog 88F6828 based boards
 *
 *  Copyright (C) 2015 Russell King
 *
 * This board is in development; the contents of this file work with
 * the A1 rev 2.0 of the board, which does not represent final
 * production board.  Things will change, don't expect this file to
 * remain compatible info the future.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "armada-388.dtsi"
#include "armada-38x-solidrun-microsom.dtsi"

/ {
	aliases {
		/* So that mvebu u-boot can update the MAC addresses */
		ethernet1 = &eth0;
		ethernet2 = &eth1;
		ethernet3 = &eth2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	soc {
		internal-regs {
			ethernet@30000 {
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
				bm,pool-short = <1>;
				status = "okay";
			};

			ethernet@34000 {
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <3>;
				bm,pool-short = <1>;
				status = "okay";

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			i2c@11000 {
				/* Is there anything on this? */
				clock-frequency = <100000>;
				pinctrl-0 = <&i2c0_pins>;
				pinctrl-names = "default";
				status = "okay";

				/*
				 * PCA9655 GPIO expander, up to 1MHz clock.
				 *  0-CON3 CLKREQ#
				 *  1-CON3 PERST#
				 *  2-
				 *  3-CON3 W_DISABLE
				 *  4-
				 *  5-USB3 overcurrent
				 *  6-USB3 power
				 *  7-
				 *  8-JP4 P1
				 *  9-JP4 P4
				 * 10-JP4 P5
				 * 11-m.2 DEVSLP
				 * 12-SFP_LOS
				 * 13-SFP_TX_FAULT
				 * 14-SFP_TX_DISABLE
				 * 15-SFP_MOD_DEF0
				 */
				expander0: gpio-expander@20 {
					/*
					 * This is how it should be:
					 * compatible = "onnn,pca9655",
					 *	 "nxp,pca9555";
					 * but you can't do this because of
					 * the way I2C works.
					 */
					compatible = "nxp,pca9555";
					gpio-controller;
					#gpio-cells = <2>;
					reg = <0x20>;

					pcie1_0_clkreq {
						gpio-hog;
						gpios = <0 GPIO_ACTIVE_LOW>;
						input;
						line-name = "pcie1.0-clkreq";
					};
					pcie1_0_w_disable {
						gpio-hog;
						gpios = <3 GPIO_ACTIVE_LOW>;
						output-low;
						line-name = "pcie1.0-w-disable";
					};
					usb3_ilimit {
						gpio-hog;
						gpios = <5 GPIO_ACTIVE_LOW>;
						input;
						line-name = "usb3-current-limit";
					};
					usb3_power {
						gpio-hog;
						gpios = <6 GPIO_ACTIVE_HIGH>;
						output-high;
						line-name = "usb3-power";
					};
					m2_devslp {
						gpio-hog;
						gpios = <11 GPIO_ACTIVE_HIGH>;
						output-low;
						line-name = "m.2 devslp";
					};
					sfp_los {
						/* SFP loss of signal */
						gpio-hog;
						gpios = <12 GPIO_ACTIVE_HIGH>;
						input;
						line-name = "sfp-los";
					};
					sfp_tx_fault {
						/* SFP laser fault */
						gpio-hog;
						gpios = <13 GPIO_ACTIVE_HIGH>;
						input;
						line-name = "sfp-tx-fault";
					};
					sfp_tx_disable {
						/* SFP transmit disable */
						gpio-hog;
						gpios = <14 GPIO_ACTIVE_HIGH>;
						output-low;
						line-name = "sfp-tx-disable";
					};
					sfp_mod_def0 {
						/* SFP module present */
						gpio-hog;
						gpios = <15 GPIO_ACTIVE_LOW>;
						input;
						line-name = "sfp-mod-def0";
					};
				};

				/* The MCP3021 is 100kHz clock only */
				mikrobus_adc: mcp3021@4c {
					compatible = "microchip,mcp3021";
					reg = <0x4c>;
				};

				/* Also something at 0x64 */
			};

			i2c@11100 {
				/*
				 * Routed to SFP, mikrobus, and PCIe.
				 * SFP limits this to 100kHz, and requires
				 *  an AT24C01A/02/04 with address pins tied
				 *  low, which takes addresses 0x50 and 0x51.
				 * Mikrobus doesn't specify beyond an I2C
				 *  bus being present.
				 * PCIe uses ARP to assign addresses, or
				 *  0x63-0x64.
				 */
				clock-frequency = <100000>;
				pinctrl-0 = <&clearfog_i2c1_pins>;
				pinctrl-names = "default";
				status = "okay";
			};

			sata@a8000 {
				/* pinctrl? */
				status = "okay";
			};

			sata@e0000 {
				/* pinctrl? */
				status = "okay";
			};

			sdhci@d8000 {
				bus-width = <4>;
				cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
				no-1-8-v;
				pinctrl-0 = <&microsom_sdhci_pins
					     &clearfog_sdhci_cd_pins>;
				pinctrl-names = "default";
				status = "okay";
				vmmc = <&reg_3p3v>;
				wp-inverted;
			};

			serial@12100 {
				/* mikrobus uart */
				pinctrl-0 = <&mikro_uart_pins>;
				pinctrl-names = "default";
				status = "okay";
			};

			usb@58000 {
				/* CON3, nearest  power. */
				status = "okay";
			};

			usb3@f8000 {
				/* CON7 */
				status = "okay";
			};
		};

		pcie-controller {
			status = "okay";
			/*
			 * The two PCIe units are accessible through
			 * the mini-PCIe connectors on the board.
			 */
			pcie@2,0 {
				/* Port 1, Lane 0. CON3, nearest power. */
				reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
				status = "okay";
			};
		};
	};
};

&pinctrl {
	clearfog_i2c1_pins: i2c1-pins {
		/* SFP, PCIe, mSATA, mikrobus */
		marvell,pins = "mpp26", "mpp27";
		marvell,function = "i2c1";
	};
	clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
		marvell,pins = "mpp20";
		marvell,function = "gpio";
	};
	mikro_pins: mikro-pins {
		/* int: mpp22 rst: mpp29 */
		marvell,pins = "mpp22", "mpp29";
		marvell,function = "gpio";
	};
	mikro_spi_pins: mikro-spi-pins {
		marvell,pins = "mpp43";
		marvell,function = "spi1";
	};
	mikro_uart_pins: mikro-uart-pins {
		marvell,pins = "mpp24", "mpp25";
		marvell,function = "ua1";
	};
};

&spi1 {
	/*
	 * Add SPI CS pins for clearfog:
	 * CS0: W25Q32 (not populated on uSOM)
	 * CS1: PIC microcontroller (Pro models)
	 * CS2: mikrobus
	 */
	pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
	pinctrl-names = "default";
	status = "okay";
};
Commit	Line	Data
76138f94 RK	1	/*
	2	* Device Tree include file for SolidRun Clearfog 88F6828 based boards
	3	*
	4	* Copyright (C) 2015 Russell King
	5	*
	6	* This board is in development; the contents of this file work with
	7	* the A1 rev 2.0 of the board, which does not represent final
	8	* production board. Things will change, don't expect this file to
	9	* remain compatible info the future.
	10	*
	11	* This file is dual-licensed: you can use it either under the terms
	12	* of the GPL or the X11 license, at your option. Note that this dual
	13	* licensing only applies to this file, and not this project as a
	14	* whole.
	15	*
	16	* a) This file is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License
	18	* version 2 as published by the Free Software Foundation.
	19	*
	20	* This file is distributed in the hope that it will be useful
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* Or, alternatively
	26	*
	27	* b) Permission is hereby granted, free of charge, to any person
	28	* obtaining a copy of this software and associated documentation
	29	* files (the "Software"), to deal in the Software without
	30	* restriction, including without limitation the rights to use
	31	* copy, modify, merge, publish, distribute, sublicense, and/or
	32	* sell copies of the Software, and to permit persons to whom the
	33	* Software is furnished to do so, subject to the following
	34	* conditions:
	35	*
	36	* The above copyright notice and this permission notice shall be
	37	* included in all copies or substantial portions of the Software.
	38	*
	39	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	40	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	41	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	42	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	43	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	44	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	45	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	46	* OTHER DEALINGS IN THE SOFTWARE.
	47	*/
	48
	49	#include "armada-388.dtsi"
	50	#include "armada-38x-solidrun-microsom.dtsi"
	51
	52	/ {
	53	aliases {
	54	/* So that mvebu u-boot can update the MAC addresses */
	55	ethernet1 = &eth0;
	56	ethernet2 = &eth1;
	57	ethernet3 = &eth2;
	58	};
	59
	60	chosen {
	61	stdout-path = "serial0:115200n8";
	62	};
	63
	64	reg_3p3v: regulator-3p3v {
65	compatible = "regulator-fixed";
66	regulator-name = "3P3V";
67	regulator-min-microvolt = <3300000>;
68	regulator-max-microvolt = <3300000>;
69	regulator-always-on;
70	};
71
72	soc {
73	internal-regs {
74	ethernet@30000 {
75	phy-mode = "sgmii";
76	buffer-manager = <&bm>;
77	bm,pool-long = <2>;
78	bm,pool-short = <1>;
79	status = "okay";
76138f94 RK	80	};
	81
	82	ethernet@34000 {
	83	phy-mode = "sgmii";
	84	buffer-manager = <&bm>;
	85	bm,pool-long = <3>;
	86	bm,pool-short = <1>;
	87	status = "okay";
	88
	89	fixed-link {
	90	speed = <1000>;
	91	full-duplex;
	92	};
	93	};
	94
	95	i2c@11000 {
	96	/* Is there anything on this? */
	97	clock-frequency = <100000>;
	98	pinctrl-0 = <&i2c0_pins>;
	99	pinctrl-names = "default";
	100	status = "okay";
	101
	102	/*
	103	* PCA9655 GPIO expander, up to 1MHz clock.
	104	* 0-CON3 CLKREQ#
	105	* 1-CON3 PERST#
54f0ec0a	106	* 2-
76138f94	107	* 3-CON3 W_DISABLE
54f0ec0a	108	* 4-
76138f94 RK	109	* 5-USB3 overcurrent
76138f94 RK	110	* 6-USB3 power
54f0ec0a	111	* 7-
76138f94 RK	112	* 8-JP4 P1
	113	* 9-JP4 P4
	114	* 10-JP4 P5
	115	* 11-m.2 DEVSLP
	116	* 12-SFP_LOS
	117	* 13-SFP_TX_FAULT
	118	* 14-SFP_TX_DISABLE
	119	* 15-SFP_MOD_DEF0
	120	*/
	121	expander0: gpio-expander@20 {
	122	/*
	123	* This is how it should be:
	124	* compatible = "onnn,pca9655",
	125	* "nxp,pca9555";
	126	* but you can't do this because of
	127	* the way I2C works.
	128	*/
	129	compatible = "nxp,pca9555";
	130	gpio-controller;
	131	#gpio-cells = <2>;
	132	reg = <0x20>;
	133
	134	pcie1_0_clkreq {
	135	gpio-hog;
	136	gpios = <0 GPIO_ACTIVE_LOW>;
	137	input;
	138	line-name = "pcie1.0-clkreq";
	139	};
	140	pcie1_0_w_disable {
	141	gpio-hog;
	142	gpios = <3 GPIO_ACTIVE_LOW>;
	143	output-low;
	144	line-name = "pcie1.0-w-disable";
	145	};
76138f94 RK	146	usb3_ilimit {
	147	gpio-hog;
	148	gpios = <5 GPIO_ACTIVE_LOW>;
	149	input;
	150	line-name = "usb3-current-limit";
	151	};
	152	usb3_power {
	153	gpio-hog;
	154	gpios = <6 GPIO_ACTIVE_HIGH>;
	155	output-high;
	156	line-name = "usb3-power";
	157	};
	158	m2_devslp {
	159	gpio-hog;
	160	gpios = <11 GPIO_ACTIVE_HIGH>;
	161	output-low;
	162	line-name = "m.2 devslp";
	163	};
	164	sfp_los {
	165	/* SFP loss of signal */
	166	gpio-hog;
	167	gpios = <12 GPIO_ACTIVE_HIGH>;
	168	input;
	169	line-name = "sfp-los";
	170	};
	171	sfp_tx_fault {
	172	/* SFP laser fault */
	173	gpio-hog;
	174	gpios = <13 GPIO_ACTIVE_HIGH>;
	175	input;
	176	line-name = "sfp-tx-fault";
	177	};
	178	sfp_tx_disable {
	179	/* SFP transmit disable */
	180	gpio-hog;
	181	gpios = <14 GPIO_ACTIVE_HIGH>;
	182	output-low;
	183	line-name = "sfp-tx-disable";
	184	};
	185	sfp_mod_def0 {
	186	/* SFP module present */
	187	gpio-hog;
	188	gpios = <15 GPIO_ACTIVE_LOW>;
	189	input;
	190	line-name = "sfp-mod-def0";
	191	};
	192	};
	193
	194	/* The MCP3021 is 100kHz clock only */
	195	mikrobus_adc: mcp3021@4c {
	196	compatible = "microchip,mcp3021";
	197	reg = <0x4c>;
	198	};
	199
	200	/* Also something at 0x64 */
	201	};
	202
	203	i2c@11100 {
	204	/*
	205	* Routed to SFP, mikrobus, and PCIe.
	206	* SFP limits this to 100kHz, and requires
	207	* an AT24C01A/02/04 with address pins tied
	208	* low, which takes addresses 0x50 and 0x51.
	209	* Mikrobus doesn't specify beyond an I2C
210	* bus being present.
211	* PCIe uses ARP to assign addresses, or
212	* 0x63-0x64.
213	*/
214	clock-frequency = <100000>;
215	pinctrl-0 = <&clearfog_i2c1_pins>;
216	pinctrl-names = "default";
217	status = "okay";
218	};
219
76138f94 RK	220	sata@a8000 {
	221	/* pinctrl? */
	222	status = "okay";
	223	};
	224
	225	sata@e0000 {
	226	/* pinctrl? */
	227	status = "okay";
	228	};
	229
	230	sdhci@d8000 {
	231	bus-width = <4>;
	232	cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
	233	no-1-8-v;
	234	pinctrl-0 = <&microsom_sdhci_pins
	235	&clearfog_sdhci_cd_pins>;
	236	pinctrl-names = "default";
	237	status = "okay";
	238	vmmc = <&reg_3p3v>;
	239	wp-inverted;
	240	};
	241
	242	serial@12100 {
	243	/* mikrobus uart */
	244	pinctrl-0 = <&mikro_uart_pins>;
	245	pinctrl-names = "default";
	246	status = "okay";
	247	};
	248
	249	usb@58000 {
	250	/* CON3, nearest power. */
	251	status = "okay";
	252	};
	253
76138f94 RK	254	usb3@f8000 {
	255	/* CON7 */
	256	status = "okay";
	257	};
	258	};
	259
	260	pcie-controller {
	261	status = "okay";
	262	/*
	263	* The two PCIe units are accessible through
	264	* the mini-PCIe connectors on the board.
	265	*/
	266	pcie@2,0 {
	267	/* Port 1, Lane 0. CON3, nearest power. */
	268	reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
	269	status = "okay";
	270	};
76138f94 RK	271	};
76138f94 RK	272	};
76138f94 RK	273	};
76138f94 RK	274
fce54ee2 RK	275	&pinctrl {
	276	clearfog_i2c1_pins: i2c1-pins {
	277	/* SFP, PCIe, mSATA, mikrobus */
	278	marvell,pins = "mpp26", "mpp27";
	279	marvell,function = "i2c1";
	280	};
	281	clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
	282	marvell,pins = "mpp20";
	283	marvell,function = "gpio";
	284	};
	285	mikro_pins: mikro-pins {
	286	/* int: mpp22 rst: mpp29 */
	287	marvell,pins = "mpp22", "mpp29";
	288	marvell,function = "gpio";
	289	};
	290	mikro_spi_pins: mikro-spi-pins {
	291	marvell,pins = "mpp43";
	292	marvell,function = "spi1";
	293	};
	294	mikro_uart_pins: mikro-uart-pins {
	295	marvell,pins = "mpp24", "mpp25";
	296	marvell,function = "ua1";
	297	};
	298	};
	299
76138f94 RK	300	&spi1 {
	301	/*
	302	* Add SPI CS pins for clearfog:
	303	* CS0: W25Q32 (not populated on uSOM)
869fe59c	304	* CS1: PIC microcontroller (Pro models)
76138f94 RK	305	* CS2: mikrobus
76138f94 RK	306	*/
869fe59c	307	pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
76138f94 RK	308	pinctrl-names = "default";
	309	status = "okay";
	310	};