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928413bd GC |
1 | /* |
2 | * Device Tree file for Marvell Armada 385 development board | |
3 | * (RD-88F6820-GP) | |
4 | * | |
5 | * Copyright (C) 2014 Marvell | |
6 | * | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * | |
9 | * This file is dual-licensed: you can use it either under the terms | |
10 | * of the GPL or the X11 license, at your option. Note that this dual | |
11 | * licensing only applies to this file, and not this project as a | |
12 | * whole. | |
13 | * | |
14 | * a) This file is licensed under the terms of the GNU General Public | |
15 | * License version 2. This program is licensed "as is" without | |
16 | * any warranty of any kind, whether express or implied. | |
17 | * | |
18 | * Or, alternatively, | |
19 | * | |
20 | * b) Permission is hereby granted, free of charge, to any person | |
21 | * obtaining a copy of this software and associated documentation | |
22 | * files (the "Software"), to deal in the Software without | |
23 | * restriction, including without limitation the rights to use, | |
24 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
25 | * sell copies of the Software, and to permit persons to whom the | |
26 | * Software is furnished to do so, subject to the following | |
27 | * conditions: | |
28 | * | |
29 | * The above copyright notice and this permission notice shall be | |
30 | * included in all copies or substantial portions of the Software. | |
31 | * | |
32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
33 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
34 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
35 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
36 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
37 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
38 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
39 | * OTHER DEALINGS IN THE SOFTWARE. | |
40 | */ | |
41 | ||
42 | /dts-v1/; | |
43 | #include "armada-388.dtsi" | |
44 | #include <dt-bindings/gpio/gpio.h> | |
45 | ||
46 | / { | |
05abb975 TP |
47 | model = "Marvell Armada 388 DB-88F6820-GP"; |
48 | compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380"; | |
928413bd GC |
49 | |
50 | chosen { | |
9552203c | 51 | stdout-path = "serial0:115200n8"; |
928413bd GC |
52 | }; |
53 | ||
54 | memory { | |
55 | device_type = "memory"; | |
56 | reg = <0x00000000 0x80000000>; /* 2 GB */ | |
57 | }; | |
58 | ||
59 | soc { | |
60 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | |
d716f2e8 BB |
61 | MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 |
62 | MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 | |
c49e99c2 MW |
63 | MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 |
64 | MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; | |
928413bd GC |
65 | |
66 | internal-regs { | |
928413bd GC |
67 | i2c@11000 { |
68 | pinctrl-names = "default"; | |
69 | pinctrl-0 = <&i2c0_pins>; | |
70 | status = "okay"; | |
71 | clock-frequency = <100000>; | |
928413bd GC |
72 | |
73 | expander0: pca9555@20 { | |
74 | compatible = "nxp,pca9555"; | |
75 | pinctrl-names = "default"; | |
76 | pinctrl-0 = <&pca0_pins>; | |
77 | interrupt-parent = <&gpio0>; | |
8d451417 | 78 | interrupts = <18 IRQ_TYPE_LEVEL_LOW>; |
928413bd GC |
79 | gpio-controller; |
80 | #gpio-cells = <2>; | |
81 | interrupt-controller; | |
82 | #interrupt-cells = <2>; | |
83 | reg = <0x20>; | |
84 | }; | |
85 | ||
86 | expander1: pca9555@21 { | |
87 | compatible = "nxp,pca9555"; | |
88 | pinctrl-names = "default"; | |
89 | interrupt-parent = <&gpio0>; | |
8d451417 | 90 | interrupts = <18 IRQ_TYPE_LEVEL_LOW>; |
928413bd GC |
91 | gpio-controller; |
92 | #gpio-cells = <2>; | |
93 | interrupt-controller; | |
94 | #interrupt-cells = <2>; | |
95 | reg = <0x21>; | |
96 | }; | |
97 | ||
7e5308be TP |
98 | eeprom@57 { |
99 | compatible = "atmel,24c64"; | |
100 | reg = <0x57>; | |
101 | }; | |
928413bd GC |
102 | }; |
103 | ||
104 | serial@12000 { | |
105 | /* | |
106 | * Exported on the micro USB connector CON16 | |
107 | * through an FTDI | |
108 | */ | |
109 | ||
110 | pinctrl-names = "default"; | |
111 | pinctrl-0 = <&uart0_pins>; | |
112 | status = "okay"; | |
113 | }; | |
114 | ||
115 | /* GE1 CON15 */ | |
116 | ethernet@30000 { | |
117 | pinctrl-names = "default"; | |
118 | pinctrl-0 = <&ge1_rgmii_pins>; | |
119 | status = "okay"; | |
120 | phy = <&phy1>; | |
121 | phy-mode = "rgmii-id"; | |
c49e99c2 MW |
122 | buffer-manager = <&bm>; |
123 | bm,pool-long = <2>; | |
124 | bm,pool-short = <3>; | |
928413bd GC |
125 | }; |
126 | ||
127 | /* CON4 */ | |
a165c3b6 | 128 | usb@58000 { |
928413bd GC |
129 | vcc-supply = <®_usb2_0_vbus>; |
130 | status = "okay"; | |
131 | }; | |
132 | ||
133 | /* GE0 CON1 */ | |
134 | ethernet@70000 { | |
135 | pinctrl-names = "default"; | |
136 | /* | |
137 | * The Reference Clock 0 is used to provide a | |
138 | * clock to the PHY | |
139 | */ | |
140 | pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; | |
141 | status = "okay"; | |
142 | phy = <&phy0>; | |
143 | phy-mode = "rgmii-id"; | |
c49e99c2 MW |
144 | buffer-manager = <&bm>; |
145 | bm,pool-long = <0>; | |
146 | bm,pool-short = <1>; | |
928413bd GC |
147 | }; |
148 | ||
149 | ||
150 | mdio@72004 { | |
151 | pinctrl-names = "default"; | |
152 | pinctrl-0 = <&mdio_pins>; | |
153 | ||
154 | phy0: ethernet-phy@1 { | |
155 | reg = <1>; | |
156 | }; | |
157 | ||
158 | phy1: ethernet-phy@0 { | |
159 | reg = <0>; | |
160 | }; | |
161 | }; | |
162 | ||
163 | sata@a8000 { | |
164 | pinctrl-names = "default"; | |
165 | pinctrl-0 = <&sata0_pins>, <&sata1_pins>; | |
166 | status = "okay"; | |
167 | #address-cells = <1>; | |
168 | #size-cells = <0>; | |
0df5a6cc GC |
169 | |
170 | sata0: sata-port@0 { | |
171 | reg = <0>; | |
172 | target-supply = <®_5v_sata0>; | |
173 | }; | |
174 | ||
175 | sata1: sata-port@1 { | |
176 | reg = <1>; | |
177 | target-supply = <®_5v_sata1>; | |
178 | }; | |
928413bd GC |
179 | }; |
180 | ||
c49e99c2 MW |
181 | bm@c8000 { |
182 | status = "okay"; | |
183 | }; | |
184 | ||
928413bd GC |
185 | sata@e0000 { |
186 | pinctrl-names = "default"; | |
187 | pinctrl-0 = <&sata2_pins>, <&sata3_pins>; | |
188 | status = "okay"; | |
189 | #address-cells = <1>; | |
190 | #size-cells = <0>; | |
0df5a6cc GC |
191 | |
192 | sata2: sata-port@0 { | |
193 | reg = <0>; | |
194 | target-supply = <®_5v_sata2>; | |
195 | }; | |
196 | ||
197 | sata3: sata-port@1 { | |
198 | reg = <1>; | |
199 | target-supply = <®_5v_sata3>; | |
200 | }; | |
928413bd GC |
201 | }; |
202 | ||
203 | sdhci@d8000 { | |
204 | pinctrl-names = "default"; | |
205 | pinctrl-0 = <&sdhci_pins>; | |
928413bd | 206 | no-1-8-v; |
6b61f249 MW |
207 | /* |
208 | * A388-GP board v1.5 and higher replace | |
209 | * hitherto card detection method based on GPIO | |
210 | * with the one using DAT3 pin. As they are | |
211 | * incompatible, software-based polling is | |
212 | * enabled with 'broken-cd' property. For boards | |
213 | * older than v1.5 it can be replaced with: | |
214 | * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;', | |
215 | * whereas for the newer ones following can be | |
216 | * used instead: | |
217 | * 'dat3-cd;' | |
218 | * 'cd-inverted;' | |
219 | */ | |
220 | broken-cd; | |
928413bd GC |
221 | wp-inverted; |
222 | bus-width = <8>; | |
223 | status = "okay"; | |
224 | }; | |
225 | ||
226 | /* CON5 */ | |
227 | usb3@f0000 { | |
96c78e2b | 228 | usb-phy = <&usb2_1_phy>; |
928413bd GC |
229 | status = "okay"; |
230 | }; | |
231 | ||
232 | /* CON7 */ | |
233 | usb3@f8000 { | |
96c78e2b | 234 | usb-phy = <&usb3_phy>; |
928413bd GC |
235 | status = "okay"; |
236 | }; | |
237 | }; | |
238 | ||
c49e99c2 MW |
239 | bm-bppi { |
240 | status = "okay"; | |
241 | }; | |
242 | ||
928413bd GC |
243 | pcie-controller { |
244 | status = "okay"; | |
245 | /* | |
246 | * One PCIe units is accessible through | |
247 | * standard PCIe slot on the board. | |
248 | */ | |
249 | pcie@1,0 { | |
250 | /* Port 0, Lane 0 */ | |
251 | status = "okay"; | |
252 | }; | |
253 | ||
254 | /* | |
255 | * The two other PCIe units are accessible | |
256 | * through mini PCIe slot on the board. | |
257 | */ | |
258 | pcie@2,0 { | |
259 | /* Port 1, Lane 0 */ | |
260 | status = "okay"; | |
261 | }; | |
262 | pcie@3,0 { | |
263 | /* Port 2, Lane 0 */ | |
264 | status = "okay"; | |
265 | }; | |
266 | }; | |
267 | ||
268 | gpio-fan { | |
269 | compatible = "gpio-fan"; | |
270 | gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; | |
271 | gpio-fan,speed-map = < 0 0 | |
272 | 3000 1>; | |
273 | }; | |
274 | }; | |
275 | ||
96c78e2b GC |
276 | usb2_1_phy: usb2_1_phy { |
277 | compatible = "usb-nop-xceiv"; | |
278 | vcc-supply = <®_usb2_1_vbus>; | |
279 | }; | |
280 | ||
281 | usb3_phy: usb3_phy { | |
282 | compatible = "usb-nop-xceiv"; | |
283 | vcc-supply = <®_usb3_vbus>; | |
284 | }; | |
285 | ||
928413bd GC |
286 | reg_usb3_vbus: usb3-vbus { |
287 | compatible = "regulator-fixed"; | |
288 | regulator-name = "usb3-vbus"; | |
289 | regulator-min-microvolt = <5000000>; | |
290 | regulator-max-microvolt = <5000000>; | |
291 | enable-active-high; | |
928413bd GC |
292 | gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; |
293 | }; | |
294 | ||
295 | reg_usb2_0_vbus: v5-vbus0 { | |
296 | compatible = "regulator-fixed"; | |
297 | regulator-name = "v5.0-vbus0"; | |
298 | regulator-min-microvolt = <5000000>; | |
299 | regulator-max-microvolt = <5000000>; | |
300 | enable-active-high; | |
301 | regulator-always-on; | |
302 | gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; | |
303 | }; | |
304 | ||
305 | reg_usb2_1_vbus: v5-vbus1 { | |
306 | compatible = "regulator-fixed"; | |
928413bd GC |
307 | regulator-name = "v5.0-vbus1"; |
308 | regulator-min-microvolt = <5000000>; | |
309 | regulator-max-microvolt = <5000000>; | |
310 | enable-active-high; | |
928413bd GC |
311 | gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; |
312 | }; | |
0df5a6cc GC |
313 | |
314 | reg_sata0: pwr-sata0 { | |
315 | compatible = "regulator-fixed"; | |
316 | regulator-name = "pwr_en_sata0"; | |
b5999dcb TP |
317 | regulator-min-microvolt = <12000000>; |
318 | regulator-max-microvolt = <12000000>; | |
0df5a6cc | 319 | enable-active-high; |
a8409c65 | 320 | regulator-boot-on; |
b5999dcb | 321 | gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; |
0df5a6cc GC |
322 | }; |
323 | ||
324 | reg_5v_sata0: v5-sata0 { | |
325 | compatible = "regulator-fixed"; | |
326 | regulator-name = "v5.0-sata0"; | |
327 | regulator-min-microvolt = <5000000>; | |
328 | regulator-max-microvolt = <5000000>; | |
0df5a6cc GC |
329 | vin-supply = <®_sata0>; |
330 | }; | |
331 | ||
332 | reg_12v_sata0: v12-sata0 { | |
333 | compatible = "regulator-fixed"; | |
334 | regulator-name = "v12.0-sata0"; | |
335 | regulator-min-microvolt = <12000000>; | |
336 | regulator-max-microvolt = <12000000>; | |
0df5a6cc GC |
337 | vin-supply = <®_sata0>; |
338 | }; | |
339 | ||
340 | reg_sata1: pwr-sata1 { | |
341 | regulator-name = "pwr_en_sata1"; | |
342 | compatible = "regulator-fixed"; | |
343 | regulator-min-microvolt = <12000000>; | |
344 | regulator-max-microvolt = <12000000>; | |
345 | enable-active-high; | |
a8409c65 | 346 | regulator-boot-on; |
0df5a6cc GC |
347 | gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; |
348 | }; | |
349 | ||
350 | reg_5v_sata1: v5-sata1 { | |
351 | compatible = "regulator-fixed"; | |
352 | regulator-name = "v5.0-sata1"; | |
353 | regulator-min-microvolt = <5000000>; | |
354 | regulator-max-microvolt = <5000000>; | |
0df5a6cc GC |
355 | vin-supply = <®_sata1>; |
356 | }; | |
357 | ||
358 | reg_12v_sata1: v12-sata1 { | |
359 | compatible = "regulator-fixed"; | |
360 | regulator-name = "v12.0-sata1"; | |
361 | regulator-min-microvolt = <12000000>; | |
362 | regulator-max-microvolt = <12000000>; | |
0df5a6cc GC |
363 | vin-supply = <®_sata1>; |
364 | }; | |
365 | ||
366 | reg_sata2: pwr-sata2 { | |
367 | compatible = "regulator-fixed"; | |
368 | regulator-name = "pwr_en_sata2"; | |
369 | enable-active-high; | |
a8409c65 | 370 | regulator-boot-on; |
0df5a6cc GC |
371 | gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; |
372 | }; | |
373 | ||
374 | reg_5v_sata2: v5-sata2 { | |
375 | compatible = "regulator-fixed"; | |
376 | regulator-name = "v5.0-sata2"; | |
377 | regulator-min-microvolt = <5000000>; | |
378 | regulator-max-microvolt = <5000000>; | |
0df5a6cc GC |
379 | vin-supply = <®_sata2>; |
380 | }; | |
381 | ||
382 | reg_12v_sata2: v12-sata2 { | |
383 | compatible = "regulator-fixed"; | |
384 | regulator-name = "v12.0-sata2"; | |
385 | regulator-min-microvolt = <12000000>; | |
386 | regulator-max-microvolt = <12000000>; | |
0df5a6cc GC |
387 | vin-supply = <®_sata2>; |
388 | }; | |
389 | ||
390 | reg_sata3: pwr-sata3 { | |
391 | compatible = "regulator-fixed"; | |
392 | regulator-name = "pwr_en_sata3"; | |
393 | enable-active-high; | |
a8409c65 | 394 | regulator-boot-on; |
0df5a6cc GC |
395 | gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; |
396 | }; | |
397 | ||
398 | reg_5v_sata3: v5-sata3 { | |
399 | compatible = "regulator-fixed"; | |
400 | regulator-name = "v5.0-sata3"; | |
401 | regulator-min-microvolt = <5000000>; | |
402 | regulator-max-microvolt = <5000000>; | |
0df5a6cc GC |
403 | vin-supply = <®_sata3>; |
404 | }; | |
405 | ||
406 | reg_12v_sata3: v12-sata3 { | |
407 | compatible = "regulator-fixed"; | |
408 | regulator-name = "v12.0-sata3"; | |
409 | regulator-min-microvolt = <12000000>; | |
410 | regulator-max-microvolt = <12000000>; | |
0df5a6cc GC |
411 | vin-supply = <®_sata3>; |
412 | }; | |
928413bd GC |
413 | }; |
414 | ||
415 | &pinctrl { | |
416 | pca0_pins: pca0_pins { | |
417 | marvell,pins = "mpp18"; | |
418 | marvell,function = "gpio"; | |
419 | }; | |
420 | }; | |
0160a4b6 SR |
421 | |
422 | &spi0 { | |
423 | pinctrl-names = "default"; | |
424 | pinctrl-0 = <&spi0_pins>; | |
425 | status = "okay"; | |
426 | ||
427 | spi-flash@0 { | |
428 | #address-cells = <1>; | |
429 | #size-cells = <1>; | |
430 | compatible = "st,m25p128", "jedec,spi-nor"; | |
431 | reg = <0>; /* Chip select 0 */ | |
432 | spi-max-frequency = <50000000>; | |
433 | m25p,fast-read; | |
434 | }; | |
435 | }; |