[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / armada-xp-98dx3236.dtsi

/*
 * Device Tree Include file for Marvell 98dx3236 family SoC
 *
 * Copyright (C) 2016 Allied Telesis Labs
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * Contains definitions specific to the 98dx3236 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-370-xp.dtsi"

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	model = "Marvell 98DX3236 SoC";
	compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,98dx3236-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
			clock-latency = <1000000>;
		};
	};

	soc {
		compatible = "marvell,armadaxp-mbus", "simple-bus";

		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
			  MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
			  MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		/*
		 * 98DX3236 has 1 x1 PCIe unit Gen2.0
		 */
		pciec: pcie@82000000 {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */>;

			pcie1: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};
		};

		internal-regs {
			sdramc@1400 {
				compatible = "marvell,armada-xp-sdram-controller";
				reg = <0x1400 0x500>;
			};

			L2: l2-cache@8000 {
				compatible = "marvell,aurora-system-cache";
				reg = <0x08000 0x1000>;
				cache-id-part = <0x100>;
				cache-level = <2>;
				cache-unified;
				wt-override;
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			/* does not exist */
			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				status = "disabled";
			};

			gpio2: gpio@18180 { /* rework some properties */
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <1>; /* only gpio #32 */
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>;
			};

			systemc: system-controller@18200 {
				compatible = "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x500>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,mv98dx3236-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			cpuclk: clock-complex@18700 {
				#clock-cells = <1>;
				compatible = "marvell,mv98dx3236-cpu-clock";
				reg = <0x18700 0x24>, <0x1c054 0x10>;
				clocks = <&coreclk 1>;
			};

			corediv-clock@18740 {
				status = "disabled";
			};

			cpu-config@21000 {
				compatible = "marvell,armada-xp-cpu-config";
				reg = <0x21000 0x8>;
			};

			ethernet@70000 {
				compatible = "marvell,armada-xp-neta";
			};

			ethernet@74000 {
				compatible = "marvell,armada-xp-neta";
			};

			xor1: xor@f0800 {
				compatible = "marvell,orion-xor";
				reg = <0xf0800 0x100
				       0xf0a00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor10 {
					interrupts = <51>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <52>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			nand: nand@d0000 {
				clocks = <&dfx_coredivclk 0>;
			};

			xor0: xor@f0900 {
				compatible = "marvell,orion-xor";
				reg = <0xF0900 0x100
				       0xF0B00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor00 {
					interrupts = <94>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <95>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};
		};

		dfx: dfx-server@ac000000 {
			compatible = "marvell,dfx-server", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;

			coreclk: mvebu-sar@f8204 {
				compatible = "marvell,mv98dx3236-core-clock";
				reg = <0xf8204 0x4>;
				#clock-cells = <1>;
			};

			dfx_coredivclk: corediv-clock@f8268 {
				compatible = "marvell,mv98dx3236-corediv-clock";
				reg = <0xf8268 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};
		};

		switch: switch@a8000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;

			pp0: packet-processor@0 {
				compatible = "marvell,prestera-98dx3236";
				reg = <0 0x4000000>;
				interrupts = <33>, <34>, <35>;
				dfx = <&dfx>;
			};
		};
	};

	clocks {
		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};

&i2c0 {
	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	reg = <0x11000 0x100>;
};

&i2c1 {
	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	reg = <0x11100 0x100>;
};

&mpic {
	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};

&rtc {
	status = "disabled";
};

&timer {
	compatible = "marvell,armada-xp-timer";
	clocks = <&coreclk 2>, <&refclk>;
	clock-names = "nbclk", "fixed";
};

&watchdog {
	compatible = "marvell,armada-xp-wdt";
	clocks = <&coreclk 2>, <&refclk>;
	clock-names = "nbclk", "fixed";
};

&cpurst {
	reg = <0x20800 0x20>;
};

&usb0 {
	clocks = <&gateclk 18>;
};

&usb1 {
	clocks = <&gateclk 19>;
};

&pinctrl {
	compatible = "marvell,98dx3236-pinctrl";

	spi0_pins: spi0-pins {
		marvell,pins = "mpp0", "mpp1",
			       "mpp2", "mpp3";
		marvell,function = "spi0";
	};
};

&spi0 {
	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
	pinctrl-0 = <&spi0_pins>;
	pinctrl-names = "default";
};

&sdio {
	status = "disabled";
};
Commit	Line	Data
3f81df55 CP	1	/*
	2	* Device Tree Include file for Marvell 98dx3236 family SoC
	3	*
	4	* Copyright (C) 2016 Allied Telesis Labs
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*
	44	* Contains definitions specific to the 98dx3236 SoC that are not
	45	* common to all Armada XP SoCs.
	46	*/
	47
43e28ba8	48	#include "armada-370-xp.dtsi"
3f81df55 CP	49
3f81df55 CP	50	/ {
43e28ba8 CP	51	#address-cells = <2>;
	52	#size-cells = <2>;
	53
3f81df55	54	model = "Marvell 98DX3236 SoC";
43e28ba8	55	compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
3f81df55 CP	56
	57	aliases {
	58	gpio0 = &gpio0;
	59	gpio1 = &gpio1;
	60	gpio2 = &gpio2;
	61	};
	62
	63	cpus {
	64	#address-cells = <1>;
	65	#size-cells = <0>;
	66	enable-method = "marvell,98dx3236-smp";
	67
	68	cpu@0 {
	69	device_type = "cpu";
	70	compatible = "marvell,sheeva-v7";
	71	reg = <0>;
	72	clocks = <&cpuclk 0>;
	73	clock-latency = <1000000>;
	74	};
	75	};
	76
	77	soc {
43e28ba8 CP	78	compatible = "marvell,armadaxp-mbus", "simple-bus";
43e28ba8 CP	79
3f81df55 CP	80	ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
	81	MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
	82	MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
	83	MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
	84	MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
	85
43e28ba8 CP	86	bootrom {
	87	compatible = "marvell,bootrom";
	88	reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
	89	};
	90
3f81df55 CP	91	/*
	92	* 98DX3236 has 1 x1 PCIe unit Gen2.0
	93	*/
28fbb9c5	94	pciec: pcie@82000000 {
3f81df55 CP	95	compatible = "marvell,armada-xp-pcie";
	96	status = "disabled";
	97	device_type = "pci";
	98
	99	#address-cells = <3>;
	100	#size-cells = <2>;
	101
	102	msi-parent = <&mpic>;
	103	bus-range = <0x00 0xff>;
	104
	105	ranges =
	106	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
	107	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
23988bab	108	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
3f81df55 CP	109
	110	pcie1: pcie@1,0 {
	111	device_type = "pci";
	112	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	113	reg = <0x0800 0 0 0 0>;
	114	#address-cells = <3>;
	115	#size-cells = <2>;
	116	#interrupt-cells = <1>;
	117	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	118	0x81000000 0 0 0x81000000 0x1 0 1 0>;
28fbb9c5	119	bus-range = <0x00 0xff>;
3f81df55 CP	120	interrupt-map-mask = <0 0 0 0>;
	121	interrupt-map = <0 0 0 0 &mpic 58>;
	122	marvell,pcie-port = <0>;
	123	marvell,pcie-lane = <0>;
	124	clocks = <&gateclk 5>;
	125	status = "disabled";
	126	};
	127	};
	128
	129	internal-regs {
43e28ba8 CP	130	sdramc@1400 {
	131	compatible = "marvell,armada-xp-sdram-controller";
	132	reg = <0x1400 0x500>;
	133	};
	134
	135	L2: l2-cache@8000 {
	136	compatible = "marvell,aurora-system-cache";
	137	reg = <0x08000 0x1000>;
	138	cache-id-part = <0x100>;
	139	cache-level = <2>;
	140	cache-unified;
	141	wt-override;
	142	};
	143
	144	gpio0: gpio@18100 {
	145	compatible = "marvell,orion-gpio";
	146	reg = <0x18100 0x40>;
	147	ngpios = <32>;
	148	gpio-controller;
	149	#gpio-cells = <2>;
	150	interrupt-controller;
	151	#interrupt-cells = <2>;
	152	interrupts = <82>, <83>, <84>, <85>;
	153	};
	154
	155	/* does not exist */
	156	gpio1: gpio@18140 {
	157	compatible = "marvell,orion-gpio";
	158	reg = <0x18140 0x40>;
	159	status = "disabled";
	160	};
	161
	162	gpio2: gpio@18180 { /* rework some properties */
	163	compatible = "marvell,orion-gpio";
	164	reg = <0x18180 0x40>;
	165	ngpios = <1>; /* only gpio #32 */
	166	gpio-controller;
	167	#gpio-cells = <2>;
	168	interrupt-controller;
	169	#interrupt-cells = <2>;
	170	interrupts = <87>;
	171	};
	172
	173	systemc: system-controller@18200 {
	174	compatible = "marvell,armada-370-xp-system-controller";
	175	reg = <0x18200 0x500>;
	176	};
	177
	178	gateclk: clock-gating-control@18220 {
b4bcfccb	179	compatible = "marvell,mv98dx3236-gating-clock";
43e28ba8 CP	180	reg = <0x18220 0x4>;
	181	clocks = <&coreclk 0>;
	182	#clock-cells = <1>;
	183	};
	184
3f81df55	185	cpuclk: clock-complex@18700 {
43e28ba8	186	#clock-cells = <1>;
3f81df55	187	compatible = "marvell,mv98dx3236-cpu-clock";
43e28ba8 CP	188	reg = <0x18700 0x24>, <0x1c054 0x10>;
43e28ba8 CP	189	clocks = <&coreclk 1>;
3f81df55 CP	190	};
	191
	192	corediv-clock@18740 {
	193	status = "disabled";
	194	};
	195
43e28ba8 CP	196	cpu-config@21000 {
	197	compatible = "marvell,armada-xp-cpu-config";
	198	reg = <0x21000 0x8>;
3f81df55 CP	199	};
3f81df55 CP	200
43e28ba8 CP	201	ethernet@70000 {
43e28ba8 CP	202	compatible = "marvell,armada-xp-neta";
3f81df55 CP	203	};
3f81df55 CP	204
43e28ba8 CP	205	ethernet@74000 {
43e28ba8 CP	206	compatible = "marvell,armada-xp-neta";
3f81df55 CP	207	};
3f81df55 CP	208
43e28ba8	209	xor1: xor@f0800 {
3f81df55 CP	210	compatible = "marvell,orion-xor";
	211	reg = <0xf0800 0x100
	212	0xf0a00 0x100>;
	213	clocks = <&gateclk 22>;
	214	status = "okay";
	215
	216	xor10 {
	217	interrupts = <51>;
	218	dmacap,memcpy;
	219	dmacap,xor;
	220	};
	221	xor11 {
	222	interrupts = <52>;
	223	dmacap,memcpy;
	224	dmacap,xor;
	225	dmacap,memset;
	226	};
	227	};
	228
43e28ba8 CP	229	nand: nand@d0000 {
43e28ba8 CP	230	clocks = <&dfx_coredivclk 0>;
3f81df55 CP	231	};
3f81df55 CP	232
43e28ba8 CP	233	xor0: xor@f0900 {
	234	compatible = "marvell,orion-xor";
	235	reg = <0xF0900 0x100
	236	0xF0B00 0x100>;
	237	clocks = <&gateclk 28>;
	238	status = "okay";
3f81df55	239
43e28ba8 CP	240	xor00 {
	241	interrupts = <94>;
	242	dmacap,memcpy;
	243	dmacap,xor;
	244	};
	245	xor01 {
	246	interrupts = <95>;
	247	dmacap,memcpy;
	248	dmacap,xor;
	249	dmacap,memset;
	250	};
3f81df55 CP	251	};
	252	};
	253
35a647f1 CP	254	dfx: dfx-server@ac000000 {
35a647f1 CP	255	compatible = "marvell,dfx-server", "simple-bus";
3f81df55 CP	256	#address-cells = <1>;
	257	#size-cells = <1>;
	258	ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
35a647f1	259	reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
3f81df55	260
b4bcfccb CP	261	coreclk: mvebu-sar@f8204 {
	262	compatible = "marvell,mv98dx3236-core-clock";
	263	reg = <0xf8204 0x4>;
	264	#clock-cells = <1>;
	265	};
	266
3f81df55 CP	267	dfx_coredivclk: corediv-clock@f8268 {
	268	compatible = "marvell,mv98dx3236-corediv-clock";
	269	reg = <0xf8268 0xc>;
	270	#clock-cells = <1>;
	271	clocks = <&mainpll>;
	272	clock-output-names = "nand";
	273	};
3f81df55 CP	274	};
	275
	276	switch: switch@a8000000 {
	277	compatible = "simple-bus";
	278	#address-cells = <1>;
	279	#size-cells = <1>;
	280	ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
	281
	282	pp0: packet-processor@0 {
	283	compatible = "marvell,prestera-98dx3236";
	284	reg = <0 0x4000000>;
	285	interrupts = <33>, <34>, <35>;
	286	dfx = <&dfx>;
	287	};
	288	};
	289	};
43e28ba8 CP	290
	291	clocks {
	292	/* 25 MHz reference crystal */
	293	refclk: oscillator {
	294	compatible = "fixed-clock";
	295	#clock-cells = <0>;
	296	clock-frequency = <25000000>;
	297	};
	298	};
	299	};
	300
	301	&i2c0 {
	302	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	303	reg = <0x11000 0x100>;
	304	};
	305
	306	&i2c1 {
	307	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	308	reg = <0x11100 0x100>;
	309	};
	310
	311	&mpic {
	312	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	313	};
	314
3bef2ac4 CP	315	&rtc {
	316	status = "disabled";
	317	};
	318
43e28ba8 CP	319	&timer {
	320	compatible = "marvell,armada-xp-timer";
	321	clocks = <&coreclk 2>, <&refclk>;
	322	clock-names = "nbclk", "fixed";
	323	};
	324
	325	&watchdog {
	326	compatible = "marvell,armada-xp-wdt";
	327	clocks = <&coreclk 2>, <&refclk>;
	328	clock-names = "nbclk", "fixed";
	329	};
	330
	331	&cpurst {
	332	reg = <0x20800 0x20>;
	333	};
	334
	335	&usb0 {
	336	clocks = <&gateclk 18>;
	337	};
	338
	339	&usb1 {
	340	clocks = <&gateclk 19>;
3f81df55 CP	341	};
	342
	343	&pinctrl {
	344	compatible = "marvell,98dx3236-pinctrl";
	345
	346	spi0_pins: spi0-pins {
	347	marvell,pins = "mpp0", "mpp1",
	348	"mpp2", "mpp3";
	349	marvell,function = "spi0";
	350	};
	351	};
	352
43e28ba8 CP	353	&spi0 {
	354	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
	355	pinctrl-0 = <&spi0_pins>;
	356	pinctrl-names = "default";
3f81df55 CP	357	};
3f81df55 CP	358
43e28ba8	359	&sdio {
3f81df55 CP	360	status = "disabled";
	361	};
	362