[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / armada-xp-axpwifiap.dts

/*
 * Device Tree file for Marvell RD-AXPWiFiAP.
 *
 * Note: this board is shipped with a new generation boot loader that
 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
 * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
 * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
 *
 * Copyright (C) 2013 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-xp-mv78230.dtsi"

/ {
	model = "Marvell RD-AXPWiFiAP";
	compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;

		pcie-controller {
			status = "okay";

			/* First mini-PCIe port */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			/* Second mini-PCIe port */
			pcie@2,0 {
				/* Port 0, Lane 1 */
				status = "okay";
			};

			/* Renesas uPD720202 USB 3.0 controller */
			pcie@3,0 {
				/* Port 0, Lane 3 */
				status = "okay";
			};
		};

		internal-regs {
			/* UART0 */
			serial@12000 {
				status = "okay";
			};

			/* UART1 */
			serial@12100 {
				status = "okay";
			};

			sata@a0000 {
				nr-ports = <1>;
				status = "okay";
			};

			mdio {
				phy0: ethernet-phy@0 {
					reg = <0>;
				};

				phy1: ethernet-phy@1 {
					reg = <1>;
				};
			};

			ethernet@70000 {
				pinctrl-0 = <&ge0_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};
			ethernet@74000 {
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
			};

			spi0: spi@10600 {
				status = "okay";

				spi-flash@0 {
					#address-cells = <1>;
					#size-cells = <1>;
					compatible = "n25q128a13";
					reg = <0>; /* Chip select 0 */
					spi-max-frequency = <108000000>;
				};
			};
		};
	};

	gpio_keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-0 = <&keys_pin>;
		pinctrl-names = "default";

		button@1 {
			label = "Factory Reset Button";
			linux,code = <KEY_SETUP>;
			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
		};
	};
};

&pinctrl {
	pinctrl-0 = <&phy_int_pin>;
	pinctrl-names = "default";

	keys_pin: keys-pin {
		marvell,pins = "mpp33";
		marvell,function = "gpio";
	};

	phy_int_pin: phy-int-pin {
		marvell,pins = "mpp32";
		marvell,function = "gpio";
	};
};
Commit	Line	Data
c7841473 TP	1	/*
	2	* Device Tree file for Marvell RD-AXPWiFiAP.
	3	*
	4	* Note: this board is shipped with a new generation boot loader that
	5	* remaps internal registers at 0xf1000000. Therefore, if earlyprintk
6cc082a8 PB	6	* is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
6cc082a8 PB	7	* CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
c7841473 TP	8	*
	9	* Copyright (C) 2013 Marvell
	10	*
	11	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	12	*
ebb56676 GC	13	* This file is dual-licensed: you can use it either under the terms
	14	* of the GPL or the X11 license, at your option. Note that this dual
	15	* licensing only applies to this file, and not this project as a
	16	* whole.
	17	*
	18	* a) This file is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License as
	20	* published by the Free Software Foundation; either version 2 of the
	21	* License, or (at your option) any later version.
	22	*
	23	* This file is distributed in the hope that it will be useful
	24	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	25	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	26	* GNU General Public License for more details.
	27	*
	28	* Or, alternatively
	29	*
	30	* b) Permission is hereby granted, free of charge, to any person
	31	* obtaining a copy of this software and associated documentation
	32	* files (the "Software"), to deal in the Software without
	33	* restriction, including without limitation the rights to use
	34	* copy, modify, merge, publish, distribute, sublicense, and/or
	35	* sell copies of the Software, and to permit persons to whom the
	36	* Software is furnished to do so, subject to the following
	37	* conditions:
	38	*
	39	* The above copyright notice and this permission notice shall be
	40	* included in all copies or substantial portions of the Software.
	41	*
	42	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	43	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	44	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	45	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	46	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	47	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	48	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	49	* OTHER DEALINGS IN THE SOFTWARE.
c7841473 TP	50	*/
	51
	52	/dts-v1/;
29e74f8b	53	#include <dt-bindings/gpio/gpio.h>
5c0169d1	54	#include <dt-bindings/input/input.h>
d10ff4d7	55	#include "armada-xp-mv78230.dtsi"
c7841473 TP	56
	57	/ {
	58	model = "Marvell RD-AXPWiFiAP";
	59	compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
	60
	61	chosen {
9552203c	62	stdout-path = "serial0:115200n8";
c7841473 TP	63	};
	64
	65	memory {
	66	device_type = "memory";
	67	reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
	68	};
	69
	70	soc {
d10ff4d7 EG	71	ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
	72	MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
	73
	74	pcie-controller {
	75	status = "okay";
	76
	77	/* First mini-PCIe port */
	78	pcie@1,0 {
	79	/* Port 0, Lane 0 */
	80	status = "okay";
	81	};
	82
	83	/* Second mini-PCIe port */
	84	pcie@2,0 {
	85	/* Port 0, Lane 1 */
	86	status = "okay";
	87	};
	88
	89	/* Renesas uPD720202 USB 3.0 controller */
	90	pcie@3,0 {
	91	/* Port 0, Lane 3 */
	92	status = "okay";
	93	};
	94	};
c7841473 TP	95
c7841473 TP	96	internal-regs {
6cc082a8	97	/* UART0 */
c7841473	98	serial@12000 {
c7841473 TP	99	status = "okay";
	100	};
	101
6cc082a8	102	/* UART1 */
c7841473	103	serial@12100 {
c7841473 TP	104	status = "okay";
	105	};
	106
	107	sata@a0000 {
	108	nr-ports = <1>;
	109	status = "okay";
	110	};
	111
	112	mdio {
	113	phy0: ethernet-phy@0 {
	114	reg = <0>;
	115	};
	116
	117	phy1: ethernet-phy@1 {
	118	reg = <1>;
	119	};
	120	};
	121
	122	ethernet@70000 {
70ee4e9d	123	pinctrl-0 = <&ge0_rgmii_pins>;
c7841473 TP	124	pinctrl-names = "default";
	125	status = "okay";
	126	phy = <&phy0>;
	127	phy-mode = "rgmii-id";
	128	};
	129	ethernet@74000 {
70ee4e9d	130	pinctrl-0 = <&ge1_rgmii_pins>;
c7841473 TP	131	pinctrl-names = "default";
	132	status = "okay";
	133	phy = <&phy1>;
	134	phy-mode = "rgmii-id";
	135	};
	136
	137	spi0: spi@10600 {
	138	status = "okay";
c7841473 TP	139
	140	spi-flash@0 {
	141	#address-cells = <1>;
	142	#size-cells = <1>;
	143	compatible = "n25q128a13";
	144	reg = <0>; /* Chip select 0 */
	145	spi-max-frequency = <108000000>;
	146	};
	147	};
c7841473 TP	148	};
	149	};
	150
	151	gpio_keys {
	152	compatible = "gpio-keys";
	153	#address-cells = <1>;
	154	#size-cells = <0>;
70ee4e9d	155	pinctrl-0 = <&keys_pin>;
c7841473 TP	156	pinctrl-names = "default";
	157
	158	button@1 {
	159	label = "Factory Reset Button";
5c0169d1	160	linux,code = <KEY_SETUP>;
29e74f8b	161	gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
c7841473 TP	162	};
	163	};
	164	};
01c43422 SH	165
01c43422 SH	166	&pinctrl {
70ee4e9d	167	pinctrl-0 = <&phy_int_pin>;
01c43422 SH	168	pinctrl-names = "default";
01c43422 SH	169
70ee4e9d	170	keys_pin: keys-pin {
01c43422 SH	171	marvell,pins = "mpp33";
	172	marvell,function = "gpio";
	173	};
	174
70ee4e9d	175	phy_int_pin: phy-int-pin {
01c43422 SH	176	marvell,pins = "mpp32";
	177	marvell,function = "gpio";
	178	};
	179	};