]>
Commit | Line | Data |
---|---|---|
9ae6f740 TP |
1 | /* |
2 | * Device Tree file for Marvell Armada XP evaluation board | |
3 | * (DB-78460-BP) | |
4 | * | |
82066bdb | 5 | * Copyright (C) 2012-2014 Marvell |
9ae6f740 TP |
6 | * |
7 | * Lior Amsalem <alior@marvell.com> | |
8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
10 | * | |
d5272edd GC |
11 | * This file is dual-licensed: you can use it either under the terms |
12 | * of the GPL or the X11 license, at your option. Note that this dual | |
13 | * licensing only applies to this file, and not this project as a | |
14 | * whole. | |
15 | * | |
16 | * a) This file is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of the | |
19 | * License, or (at your option) any later version. | |
20 | * | |
24f0b6fe | 21 | * This file is distributed in the hope that it will be useful, |
d5272edd GC |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
24f0b6fe | 26 | * Or, alternatively, |
d5272edd GC |
27 | * |
28 | * b) Permission is hereby granted, free of charge, to any person | |
29 | * obtaining a copy of this software and associated documentation | |
30 | * files (the "Software"), to deal in the Software without | |
24f0b6fe | 31 | * restriction, including without limitation the rights to use, |
d5272edd GC |
32 | * copy, modify, merge, publish, distribute, sublicense, and/or |
33 | * sell copies of the Software, and to permit persons to whom the | |
34 | * Software is furnished to do so, subject to the following | |
35 | * conditions: | |
36 | * | |
37 | * The above copyright notice and this permission notice shall be | |
38 | * included in all copies or substantial portions of the Software. | |
39 | * | |
24f0b6fe | 40 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
d5272edd GC |
41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
24f0b6fe | 44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
d5272edd GC |
45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
47 | * OTHER DEALINGS IN THE SOFTWARE. | |
82066bdb TP |
48 | * |
49 | * Note: this Device Tree assumes that the bootloader has remapped the | |
50 | * internal registers to 0xf1000000 (instead of the default | |
51 | * 0xd0000000). The 0xf1000000 is the default used by the recent, | |
52 | * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier | |
53 | * boards were delivered with an older version of the bootloader that | |
54 | * left internal registers mapped at 0xd0000000. If you are in this | |
55 | * situation, you should either update your bootloader (preferred | |
56 | * solution) or the below Device Tree should be adjusted. | |
9ae6f740 TP |
57 | */ |
58 | ||
59 | /dts-v1/; | |
38149887 | 60 | #include "armada-xp-mv78460.dtsi" |
9ae6f740 TP |
61 | |
62 | / { | |
63 | model = "Marvell Armada XP Evaluation Board"; | |
0bec30a7 | 64 | compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; |
9ae6f740 TP |
65 | |
66 | chosen { | |
9552203c | 67 | stdout-path = "serial0:115200n8"; |
9ae6f740 TP |
68 | }; |
69 | ||
6f477f43 | 70 | memory@0 { |
9ae6f740 | 71 | device_type = "memory"; |
74898364 | 72 | reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ |
9ae6f740 TP |
73 | }; |
74 | ||
75 | soc { | |
82066bdb | 76 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 |
de1af8d4 | 77 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
c466d997 | 78 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000 |
d7d5a43c | 79 | MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 |
1200b680 | 80 | MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000 |
9dd7a57e | 81 | MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>; |
de1af8d4 EG |
82 | |
83 | devbus-bootcs { | |
84 | status = "okay"; | |
85 | ||
86 | /* Device Bus parameters are required */ | |
87 | ||
88 | /* Read parameters */ | |
f3aec8f3 | 89 | devbus,bus-width = <16>; |
de1af8d4 EG |
90 | devbus,turn-off-ps = <60000>; |
91 | devbus,badr-skew-ps = <0>; | |
92 | devbus,acc-first-ps = <124000>; | |
93 | devbus,acc-next-ps = <248000>; | |
94 | devbus,rd-setup-ps = <0>; | |
95 | devbus,rd-hold-ps = <0>; | |
96 | ||
97 | /* Write parameters */ | |
98 | devbus,sync-enable = <0>; | |
99 | devbus,wr-high-ps = <60000>; | |
100 | devbus,wr-low-ps = <60000>; | |
101 | devbus,ale-wr-ps = <60000>; | |
102 | ||
103 | /* NOR 16 MiB */ | |
104 | nor@0 { | |
105 | compatible = "cfi-flash"; | |
106 | reg = <0 0x1000000>; | |
107 | bank-width = <2>; | |
108 | }; | |
109 | }; | |
b484ff42 | 110 | |
467f54b2 GC |
111 | internal-regs { |
112 | serial@12000 { | |
467f54b2 | 113 | status = "okay"; |
f01959a9 | 114 | }; |
467f54b2 | 115 | serial@12100 { |
467f54b2 | 116 | status = "okay"; |
f01959a9 | 117 | }; |
467f54b2 | 118 | serial@12200 { |
467f54b2 | 119 | status = "okay"; |
f01959a9 | 120 | }; |
467f54b2 | 121 | serial@12300 { |
467f54b2 | 122 | status = "okay"; |
f01959a9 | 123 | }; |
200506b1 | 124 | |
467f54b2 GC |
125 | sata@a0000 { |
126 | nr-ports = <2>; | |
127 | status = "okay"; | |
128 | }; | |
200506b1 | 129 | |
467f54b2 GC |
130 | ethernet@70000 { |
131 | status = "okay"; | |
132 | phy = <&phy0>; | |
133 | phy-mode = "rgmii-id"; | |
9dd7a57e MW |
134 | buffer-manager = <&bm>; |
135 | bm,pool-long = <0>; | |
467f54b2 GC |
136 | }; |
137 | ethernet@74000 { | |
138 | status = "okay"; | |
139 | phy = <&phy1>; | |
140 | phy-mode = "rgmii-id"; | |
9dd7a57e MW |
141 | buffer-manager = <&bm>; |
142 | bm,pool-long = <1>; | |
467f54b2 GC |
143 | }; |
144 | ethernet@30000 { | |
145 | status = "okay"; | |
146 | phy = <&phy2>; | |
147 | phy-mode = "sgmii"; | |
9dd7a57e MW |
148 | buffer-manager = <&bm>; |
149 | bm,pool-long = <2>; | |
467f54b2 GC |
150 | }; |
151 | ethernet@34000 { | |
152 | status = "okay"; | |
153 | phy = <&phy3>; | |
154 | phy-mode = "sgmii"; | |
9dd7a57e MW |
155 | buffer-manager = <&bm>; |
156 | bm,pool-long = <3>; | |
157 | }; | |
158 | ||
159 | bm@c0000 { | |
160 | status = "okay"; | |
467f54b2 | 161 | }; |
bf4f9c63 | 162 | |
467f54b2 GC |
163 | mvsdio@d4000 { |
164 | pinctrl-0 = <&sdio_pins>; | |
165 | pinctrl-names = "default"; | |
bf4f9c63 | 166 | status = "okay"; |
467f54b2 | 167 | /* No CD or WP GPIOs */ |
d87b5fbb | 168 | broken-cd; |
bf4f9c63 | 169 | }; |
467f54b2 GC |
170 | |
171 | usb@50000 { | |
bf4f9c63 TP |
172 | status = "okay"; |
173 | }; | |
467f54b2 GC |
174 | |
175 | usb@51000 { | |
bf4f9c63 TP |
176 | status = "okay"; |
177 | }; | |
467f54b2 GC |
178 | |
179 | usb@52000 { | |
bf4f9c63 TP |
180 | status = "okay"; |
181 | }; | |
467f54b2 | 182 | |
af5ece39 TP |
183 | nand@d0000 { |
184 | status = "okay"; | |
185 | num-cs = <1>; | |
186 | marvell,nand-keep-config; | |
187 | marvell,nand-enable-arbiter; | |
188 | nand-on-flash-bbt; | |
189 | ||
190 | partitions { | |
191 | compatible = "fixed-partitions"; | |
192 | #address-cells = <1>; | |
193 | #size-cells = <1>; | |
194 | ||
195 | partition@0 { | |
196 | label = "U-Boot"; | |
197 | reg = <0 0x800000>; | |
198 | }; | |
199 | partition@800000 { | |
200 | label = "Linux"; | |
201 | reg = <0x800000 0x800000>; | |
202 | }; | |
203 | partition@1000000 { | |
204 | label = "Filesystem"; | |
205 | reg = <0x1000000 0x3f000000>; | |
206 | ||
207 | }; | |
208 | }; | |
209 | }; | |
bf4f9c63 | 210 | }; |
9dd7a57e MW |
211 | |
212 | bm-bppi { | |
213 | status = "okay"; | |
214 | }; | |
9ae6f740 TP |
215 | }; |
216 | }; | |
0160a4b6 | 217 | |
007d05d8 GC |
218 | &pciec { |
219 | status = "okay"; | |
220 | ||
221 | /* | |
222 | * All 6 slots are physically present as | |
223 | * standard PCIe slots on the board. | |
224 | */ | |
225 | pcie@1,0 { | |
226 | /* Port 0, Lane 0 */ | |
227 | status = "okay"; | |
228 | }; | |
229 | pcie@2,0 { | |
230 | /* Port 0, Lane 1 */ | |
231 | status = "okay"; | |
232 | }; | |
233 | pcie@3,0 { | |
234 | /* Port 0, Lane 2 */ | |
235 | status = "okay"; | |
236 | }; | |
237 | pcie@4,0 { | |
238 | /* Port 0, Lane 3 */ | |
239 | status = "okay"; | |
240 | }; | |
241 | pcie@9,0 { | |
242 | /* Port 2, Lane 0 */ | |
243 | status = "okay"; | |
244 | }; | |
245 | pcie@10,0 { | |
246 | /* Port 3, Lane 0 */ | |
247 | status = "okay"; | |
248 | }; | |
249 | }; | |
250 | ||
1fc21295 GC |
251 | &mdio { |
252 | phy0: ethernet-phy@0 { | |
253 | reg = <0>; | |
254 | }; | |
255 | ||
256 | phy1: ethernet-phy@1 { | |
257 | reg = <1>; | |
258 | }; | |
259 | ||
260 | phy2: ethernet-phy@2 { | |
261 | reg = <25>; | |
262 | }; | |
263 | ||
264 | phy3: ethernet-phy@3 { | |
265 | reg = <27>; | |
266 | }; | |
267 | }; | |
268 | ||
0160a4b6 SR |
269 | &spi0 { |
270 | status = "okay"; | |
271 | ||
272 | spi-flash@0 { | |
273 | #address-cells = <1>; | |
274 | #size-cells = <1>; | |
275 | compatible = "m25p64", "jedec,spi-nor"; | |
276 | reg = <0>; /* Chip select 0 */ | |
277 | spi-max-frequency = <20000000>; | |
278 | }; | |
279 | }; |