[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / armada-xp-mv78230.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * Contains definitions specific to the Armada XP MV78230 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78230 SoC";
	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-xp-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
			clock-latency = <1000000>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
			clock-latency = <1000000>;
		};
	};

	soc {
		/*
		 * MV78230 has 2 PCIe units Gen2.0: One unit can be
		 * configured as x4 or quad x1 lanes. One unit is
		 * x1 only.
		 */
		pciec: pcie-controller@82000000 {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
				0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
				0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
				0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
				0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
				0x82000000 0x5 0       MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
				0x81000000 0x5 0       MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */>;

			pcie1: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie2: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 59>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

			pcie3: pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 60>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 7>;
				status = "disabled";
			};

			pcie4: pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 61>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 8>;
				status = "disabled";
			};

			pcie5: pcie@5,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
				reg = <0x2800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 62>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};
		};

		internal-regs {
			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <17>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>;
			};
		};
	};
};

&pinctrl {
	compatible = "marvell,mv78230-pinctrl";
};
Commit	Line	Data
f3b42b7c TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	7	*
6cb51fac GC	8	* This file is dual-licensed: you can use it either under the terms
	9	* of the GPL or the X11 license, at your option. Note that this dual
	10	* licensing only applies to this file, and not this project as a
	11	* whole.
	12	*
	13	* a) This file is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of the
	16	* License, or (at your option) any later version.
	17	*
	18	* This file is distributed in the hope that it will be useful
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* Or, alternatively
	24	*
	25	* b) Permission is hereby granted, free of charge, to any person
	26	* obtaining a copy of this software and associated documentation
	27	* files (the "Software"), to deal in the Software without
	28	* restriction, including without limitation the rights to use
	29	* copy, modify, merge, publish, distribute, sublicense, and/or
	30	* sell copies of the Software, and to permit persons to whom the
	31	* Software is furnished to do so, subject to the following
	32	* conditions:
	33	*
	34	* The above copyright notice and this permission notice shall be
	35	* included in all copies or substantial portions of the Software.
	36	*
	37	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	38	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	39	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	40	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	41	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	42	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	43	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	44	* OTHER DEALINGS IN THE SOFTWARE.
f3b42b7c TP	45	*
	46	* Contains definitions specific to the Armada XP MV78230 SoC that are not
	47	* common to all Armada XP SoCs.
	48	*/
	49
f72b720f	50	#include "armada-xp.dtsi"
f3b42b7c TP	51
	52	/ {
	53	model = "Marvell Armada XP MV78230 SoC";
	54	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
	55
397d59f3 TP	56	aliases {
	57	gpio0 = &gpio0;
	58	gpio1 = &gpio1;
	59	};
	60
9d202783	61	cpus {
1b2529d0 TP	62	#address-cells = <1>;
1b2529d0 TP	63	#size-cells = <0>;
23157856	64	enable-method = "marvell,armada-xp-smp";
9d202783	65
1b2529d0 TP	66	cpu@0 {
	67	device_type = "cpu";
	68	compatible = "marvell,sheeva-v7";
	69	reg = <0>;
	70	clocks = <&cpuclk 0>;
38436078	71	clock-latency = <1000000>;
1b2529d0	72	};
44cfae9a	73
1b2529d0 TP	74	cpu@1 {
	75	device_type = "cpu";
	76	compatible = "marvell,sheeva-v7";
	77	reg = <1>;
	78	clocks = <&cpuclk 1>;
38436078	79	clock-latency = <1000000>;
1b2529d0	80	};
41be8dc1	81	};
9d202783	82
f3b42b7c	83	soc {
14fd8ed0 EG	84	/*
	85	* MV78230 has 2 PCIe units Gen2.0: One unit can be
	86	* configured as x4 or quad x1 lanes. One unit is
12b69a59	87	* x1 only.
14fd8ed0	88	*/
007d05d8	89	pciec: pcie-controller@82000000 {
14fd8ed0 EG	90	compatible = "marvell,armada-xp-pcie";
	91	status = "disabled";
	92	device_type = "pci";
	93
	94	#address-cells = <3>;
	95	#size-cells = <2>;
	96
d4fa9941	97	msi-parent = <&mpic>;
14fd8ed0 EG	98	bus-range = <0x00 0xff>;
	99
	100	ranges =
	101	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
14fd8ed0 EG	102	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
	103	0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
	104	0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
12b69a59	105	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
14fd8ed0 EG	106	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	107	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	108	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
	109	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
	110	0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
	111	0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
	112	0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
	113	0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
12b69a59 AE	114	0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
12b69a59 AE	115	0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
14fd8ed0	116
11f7135b	117	pcie1: pcie@1,0 {
14fd8ed0 EG	118	device_type = "pci";
	119	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	120	reg = <0x0800 0 0 0 0>;
	121	#address-cells = <3>;
	122	#size-cells = <2>;
	123	#interrupt-cells = <1>;
	124	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	125	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	126	interrupt-map-mask = <0 0 0 0>;
	127	interrupt-map = <0 0 0 0 &mpic 58>;
	128	marvell,pcie-port = <0>;
	129	marvell,pcie-lane = <0>;
	130	clocks = <&gateclk 5>;
	131	status = "disabled";
	132	};
	133
11f7135b	134	pcie2: pcie@2,0 {
14fd8ed0 EG	135	device_type = "pci";
	136	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	137	reg = <0x1000 0 0 0 0>;
	138	#address-cells = <3>;
	139	#size-cells = <2>;
	140	#interrupt-cells = <1>;
	141	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	142	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	143	interrupt-map-mask = <0 0 0 0>;
	144	interrupt-map = <0 0 0 0 &mpic 59>;
	145	marvell,pcie-port = <0>;
	146	marvell,pcie-lane = <1>;
	147	clocks = <&gateclk 6>;
	148	status = "disabled";
	149	};
	150
11f7135b	151	pcie3: pcie@3,0 {
14fd8ed0 EG	152	device_type = "pci";
	153	assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
	154	reg = <0x1800 0 0 0 0>;
	155	#address-cells = <3>;
	156	#size-cells = <2>;
	157	#interrupt-cells = <1>;
	158	ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
	159	0x81000000 0 0 0x81000000 0x3 0 1 0>;
	160	interrupt-map-mask = <0 0 0 0>;
	161	interrupt-map = <0 0 0 0 &mpic 60>;
	162	marvell,pcie-port = <0>;
	163	marvell,pcie-lane = <2>;
	164	clocks = <&gateclk 7>;
	165	status = "disabled";
	166	};
	167
11f7135b	168	pcie4: pcie@4,0 {
14fd8ed0 EG	169	device_type = "pci";
	170	assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
	171	reg = <0x2000 0 0 0 0>;
	172	#address-cells = <3>;
	173	#size-cells = <2>;
	174	#interrupt-cells = <1>;
	175	ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
	176	0x81000000 0 0 0x81000000 0x4 0 1 0>;
	177	interrupt-map-mask = <0 0 0 0>;
	178	interrupt-map = <0 0 0 0 &mpic 61>;
	179	marvell,pcie-port = <0>;
	180	marvell,pcie-lane = <3>;
	181	clocks = <&gateclk 8>;
	182	status = "disabled";
	183	};
	184
11f7135b	185	pcie5: pcie@5,0 {
14fd8ed0	186	device_type = "pci";
12b69a59 AE	187	assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
12b69a59 AE	188	reg = <0x2800 0 0 0 0>;
14fd8ed0 EG	189	#address-cells = <3>;
	190	#size-cells = <2>;
	191	#interrupt-cells = <1>;
12b69a59 AE	192	ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
12b69a59 AE	193	0x81000000 0 0 0x81000000 0x5 0 1 0>;
14fd8ed0	194	interrupt-map-mask = <0 0 0 0>;
12b69a59 AE	195	interrupt-map = <0 0 0 0 &mpic 62>;
12b69a59 AE	196	marvell,pcie-port = <1>;
14fd8ed0	197	marvell,pcie-lane = <0>;
12b69a59	198	clocks = <&gateclk 9>;
14fd8ed0 EG	199	status = "disabled";
	200	};
	201	};
	202
467f54b2	203	internal-regs {
467f54b2 GC	204	gpio0: gpio@18100 {
	205	compatible = "marvell,orion-gpio";
	206	reg = <0x18100 0x40>;
	207	ngpios = <32>;
	208	gpio-controller;
	209	#gpio-cells = <2>;
	210	interrupt-controller;
ca60985c	211	#interrupt-cells = <2>;
467f54b2	212	interrupts = <82>, <83>, <84>, <85>;
9d8f44f0 TP	213	};
9d8f44f0 TP	214
467f54b2 GC	215	gpio1: gpio@18140 {
	216	compatible = "marvell,orion-gpio";
	217	reg = <0x18140 0x40>;
	218	ngpios = <17>;
	219	gpio-controller;
	220	#gpio-cells = <2>;
	221	interrupt-controller;
ca60985c	222	#interrupt-cells = <2>;
467f54b2	223	interrupts = <87>, <88>, <89>;
9d8f44f0	224	};
9d8f44f0	225	};
f3b42b7c TP	226	};
f3b42b7c TP	227	};
01c43422 SH	228
	229	&pinctrl {
	230	compatible = "marvell,mv78230-pinctrl";
	231	};