[mirror_ubuntu-focal-kernel.git] / arch / arm / boot / dts / armada-xp-mv78230.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Contains definitions specific to the Armada XP MV78230 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78230 SoC";
	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-xp-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
			clock-latency = <1000000>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
			clock-latency = <1000000>;
		};
	};

	soc {
		/*
		 * MV78230 has 2 PCIe units Gen2.0: One unit can be
		 * configured as x4 or quad x1 lanes. One unit is
		 * x1 only.
		 */
		pcie-controller {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
				0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
				0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
				0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
				0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
				0x82000000 0x5 0       MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
				0x81000000 0x5 0       MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */>;

			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 59>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

			pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 60>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 7>;
				status = "disabled";
			};

			pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 61>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 8>;
				status = "disabled";
			};

			pcie@5,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
				reg = <0x2800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 62>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};
		};

		internal-regs {
			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <17>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>;
			};
		};
	};
};

&pinctrl {
	compatible = "marvell,mv78230-pinctrl";
};
Commit	Line	Data
f3b42b7c TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*
	12	* Contains definitions specific to the Armada XP MV78230 SoC that are not
	13	* common to all Armada XP SoCs.
	14	*/
	15
f72b720f	16	#include "armada-xp.dtsi"
f3b42b7c TP	17
	18	/ {
	19	model = "Marvell Armada XP MV78230 SoC";
	20	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
	21
397d59f3 TP	22	aliases {
	23	gpio0 = &gpio0;
	24	gpio1 = &gpio1;
	25	};
	26
9d202783	27	cpus {
1b2529d0 TP	28	#address-cells = <1>;
1b2529d0 TP	29	#size-cells = <0>;
23157856	30	enable-method = "marvell,armada-xp-smp";
9d202783	31
1b2529d0 TP	32	cpu@0 {
	33	device_type = "cpu";
	34	compatible = "marvell,sheeva-v7";
	35	reg = <0>;
	36	clocks = <&cpuclk 0>;
38436078	37	clock-latency = <1000000>;
1b2529d0	38	};
44cfae9a	39
1b2529d0 TP	40	cpu@1 {
	41	device_type = "cpu";
	42	compatible = "marvell,sheeva-v7";
	43	reg = <1>;
	44	clocks = <&cpuclk 1>;
38436078	45	clock-latency = <1000000>;
1b2529d0	46	};
41be8dc1	47	};
9d202783	48
f3b42b7c	49	soc {
14fd8ed0 EG	50	/*
	51	* MV78230 has 2 PCIe units Gen2.0: One unit can be
	52	* configured as x4 or quad x1 lanes. One unit is
12b69a59	53	* x1 only.
14fd8ed0 EG	54	*/
	55	pcie-controller {
	56	compatible = "marvell,armada-xp-pcie";
	57	status = "disabled";
	58	device_type = "pci";
	59
	60	#address-cells = <3>;
	61	#size-cells = <2>;
	62
d4fa9941	63	msi-parent = <&mpic>;
14fd8ed0 EG	64	bus-range = <0x00 0xff>;
	65
	66	ranges =
	67	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
14fd8ed0 EG	68	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
	69	0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
	70	0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
12b69a59	71	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
14fd8ed0 EG	72	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	73	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	74	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
	75	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
	76	0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
	77	0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
	78	0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
	79	0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
12b69a59 AE	80	0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
12b69a59 AE	81	0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
14fd8ed0 EG	82
	83	pcie@1,0 {
	84	device_type = "pci";
	85	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	86	reg = <0x0800 0 0 0 0>;
	87	#address-cells = <3>;
	88	#size-cells = <2>;
	89	#interrupt-cells = <1>;
	90	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	91	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	92	interrupt-map-mask = <0 0 0 0>;
	93	interrupt-map = <0 0 0 0 &mpic 58>;
	94	marvell,pcie-port = <0>;
	95	marvell,pcie-lane = <0>;
	96	clocks = <&gateclk 5>;
	97	status = "disabled";
	98	};
	99
	100	pcie@2,0 {
	101	device_type = "pci";
	102	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	103	reg = <0x1000 0 0 0 0>;
	104	#address-cells = <3>;
	105	#size-cells = <2>;
	106	#interrupt-cells = <1>;
	107	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	108	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	109	interrupt-map-mask = <0 0 0 0>;
	110	interrupt-map = <0 0 0 0 &mpic 59>;
	111	marvell,pcie-port = <0>;
	112	marvell,pcie-lane = <1>;
	113	clocks = <&gateclk 6>;
	114	status = "disabled";
	115	};
	116
	117	pcie@3,0 {
	118	device_type = "pci";
	119	assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
	120	reg = <0x1800 0 0 0 0>;
	121	#address-cells = <3>;
	122	#size-cells = <2>;
	123	#interrupt-cells = <1>;
	124	ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
	125	0x81000000 0 0 0x81000000 0x3 0 1 0>;
	126	interrupt-map-mask = <0 0 0 0>;
	127	interrupt-map = <0 0 0 0 &mpic 60>;
	128	marvell,pcie-port = <0>;
	129	marvell,pcie-lane = <2>;
	130	clocks = <&gateclk 7>;
	131	status = "disabled";
	132	};
	133
	134	pcie@4,0 {
	135	device_type = "pci";
	136	assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
	137	reg = <0x2000 0 0 0 0>;
	138	#address-cells = <3>;
	139	#size-cells = <2>;
	140	#interrupt-cells = <1>;
	141	ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
	142	0x81000000 0 0 0x81000000 0x4 0 1 0>;
	143	interrupt-map-mask = <0 0 0 0>;
	144	interrupt-map = <0 0 0 0 &mpic 61>;
	145	marvell,pcie-port = <0>;
146	marvell,pcie-lane = <3>;
147	clocks = <&gateclk 8>;
148	status = "disabled";
149	};
150
12b69a59	151	pcie@5,0 {
14fd8ed0	152	device_type = "pci";
12b69a59 AE	153	assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
12b69a59 AE	154	reg = <0x2800 0 0 0 0>;
14fd8ed0 EG	155	#address-cells = <3>;
	156	#size-cells = <2>;
	157	#interrupt-cells = <1>;
12b69a59 AE	158	ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
12b69a59 AE	159	0x81000000 0 0 0x81000000 0x5 0 1 0>;
14fd8ed0	160	interrupt-map-mask = <0 0 0 0>;
12b69a59 AE	161	interrupt-map = <0 0 0 0 &mpic 62>;
12b69a59 AE	162	marvell,pcie-port = <1>;
14fd8ed0	163	marvell,pcie-lane = <0>;
12b69a59	164	clocks = <&gateclk 9>;
14fd8ed0 EG	165	status = "disabled";
	166	};
	167	};
	168
467f54b2	169	internal-regs {
467f54b2 GC	170	gpio0: gpio@18100 {
	171	compatible = "marvell,orion-gpio";
	172	reg = <0x18100 0x40>;
	173	ngpios = <32>;
	174	gpio-controller;
	175	#gpio-cells = <2>;
	176	interrupt-controller;
ca60985c	177	#interrupt-cells = <2>;
467f54b2	178	interrupts = <82>, <83>, <84>, <85>;
9d8f44f0 TP	179	};
9d8f44f0 TP	180
467f54b2 GC	181	gpio1: gpio@18140 {
	182	compatible = "marvell,orion-gpio";
	183	reg = <0x18140 0x40>;
	184	ngpios = <17>;
	185	gpio-controller;
	186	#gpio-cells = <2>;
	187	interrupt-controller;
ca60985c	188	#interrupt-cells = <2>;
467f54b2	189	interrupts = <87>, <88>, <89>;
9d8f44f0	190	};
9d8f44f0	191	};
f3b42b7c TP	192	};
f3b42b7c TP	193	};
01c43422 SH	194
	195	&pinctrl {
	196	compatible = "marvell,mv78230-pinctrl";
	197	};