[mirror_ubuntu-jammy-kernel.git] / arch / arm / boot / dts / armada-xp-mv78230.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Contains definitions specific to the Armada XP MV78230 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78230 SoC";
	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
		};
	};

	soc {
		/*
		 * MV78230 has 2 PCIe units Gen2.0: One unit can be
		 * configured as x4 or quad x1 lanes. One unit is
		 * x1 only.
		 */
		pcie-controller {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
				0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
				0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
				0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
				0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
				0x82000000 0x5 0       MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
				0x81000000 0x5 0       MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */>;

			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 59>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

			pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 60>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 7>;
				status = "disabled";
			};

			pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 61>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 8>;
				status = "disabled";
			};

			pcie@5,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
				reg = <0x2800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 62>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};
		};

		internal-regs {
			pinctrl {
				compatible = "marvell,mv78230-pinctrl";
				reg = <0x18000 0x38>;

				sdio_pins: sdio-pins {
					marvell,pins = "mpp30", "mpp31", "mpp32",
						       "mpp33", "mpp34", "mpp35";
					marvell,function = "sd0";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <17>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>;
			};
		};
	};
};
Commit	Line	Data
f3b42b7c TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*
	12	* Contains definitions specific to the Armada XP MV78230 SoC that are not
	13	* common to all Armada XP SoCs.
	14	*/
	15
f72b720f	16	#include "armada-xp.dtsi"
f3b42b7c TP	17
	18	/ {
	19	model = "Marvell Armada XP MV78230 SoC";
	20	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
	21
397d59f3 TP	22	aliases {
	23	gpio0 = &gpio0;
	24	gpio1 = &gpio1;
	25	};
	26
9d202783	27	cpus {
1b2529d0 TP	28	#address-cells = <1>;
1b2529d0 TP	29	#size-cells = <0>;
9d202783	30
1b2529d0 TP	31	cpu@0 {
	32	device_type = "cpu";
	33	compatible = "marvell,sheeva-v7";
	34	reg = <0>;
	35	clocks = <&cpuclk 0>;
	36	};
44cfae9a	37
1b2529d0 TP	38	cpu@1 {
	39	device_type = "cpu";
	40	compatible = "marvell,sheeva-v7";
	41	reg = <1>;
	42	clocks = <&cpuclk 1>;
	43	};
41be8dc1	44	};
9d202783	45
f3b42b7c	46	soc {
14fd8ed0 EG	47	/*
	48	* MV78230 has 2 PCIe units Gen2.0: One unit can be
	49	* configured as x4 or quad x1 lanes. One unit is
12b69a59	50	* x1 only.
14fd8ed0 EG	51	*/
	52	pcie-controller {
	53	compatible = "marvell,armada-xp-pcie";
	54	status = "disabled";
	55	device_type = "pci";
	56
	57	#address-cells = <3>;
	58	#size-cells = <2>;
	59
d4fa9941	60	msi-parent = <&mpic>;
14fd8ed0 EG	61	bus-range = <0x00 0xff>;
	62
	63	ranges =
	64	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
14fd8ed0 EG	65	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
	66	0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
	67	0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
12b69a59	68	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
14fd8ed0 EG	69	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	70	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	71	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
	72	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
	73	0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
	74	0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
	75	0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
	76	0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
12b69a59 AE	77	0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
12b69a59 AE	78	0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
14fd8ed0 EG	79
	80	pcie@1,0 {
	81	device_type = "pci";
	82	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	83	reg = <0x0800 0 0 0 0>;
	84	#address-cells = <3>;
	85	#size-cells = <2>;
	86	#interrupt-cells = <1>;
	87	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	88	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	89	interrupt-map-mask = <0 0 0 0>;
	90	interrupt-map = <0 0 0 0 &mpic 58>;
	91	marvell,pcie-port = <0>;
	92	marvell,pcie-lane = <0>;
	93	clocks = <&gateclk 5>;
	94	status = "disabled";
	95	};
	96
	97	pcie@2,0 {
	98	device_type = "pci";
	99	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	100	reg = <0x1000 0 0 0 0>;
	101	#address-cells = <3>;
	102	#size-cells = <2>;
	103	#interrupt-cells = <1>;
	104	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	105	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	106	interrupt-map-mask = <0 0 0 0>;
	107	interrupt-map = <0 0 0 0 &mpic 59>;
	108	marvell,pcie-port = <0>;
	109	marvell,pcie-lane = <1>;
	110	clocks = <&gateclk 6>;
	111	status = "disabled";
	112	};
	113
	114	pcie@3,0 {
	115	device_type = "pci";
	116	assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
	117	reg = <0x1800 0 0 0 0>;
	118	#address-cells = <3>;
	119	#size-cells = <2>;
	120	#interrupt-cells = <1>;
	121	ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
	122	0x81000000 0 0 0x81000000 0x3 0 1 0>;
	123	interrupt-map-mask = <0 0 0 0>;
	124	interrupt-map = <0 0 0 0 &mpic 60>;
	125	marvell,pcie-port = <0>;
	126	marvell,pcie-lane = <2>;
	127	clocks = <&gateclk 7>;
	128	status = "disabled";
	129	};
	130
	131	pcie@4,0 {
	132	device_type = "pci";
	133	assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
	134	reg = <0x2000 0 0 0 0>;
	135	#address-cells = <3>;
	136	#size-cells = <2>;
	137	#interrupt-cells = <1>;
	138	ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
	139	0x81000000 0 0 0x81000000 0x4 0 1 0>;
	140	interrupt-map-mask = <0 0 0 0>;
	141	interrupt-map = <0 0 0 0 &mpic 61>;
	142	marvell,pcie-port = <0>;
143	marvell,pcie-lane = <3>;
144	clocks = <&gateclk 8>;
145	status = "disabled";
146	};
147
12b69a59	148	pcie@5,0 {
14fd8ed0	149	device_type = "pci";
12b69a59 AE	150	assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
12b69a59 AE	151	reg = <0x2800 0 0 0 0>;
14fd8ed0 EG	152	#address-cells = <3>;
	153	#size-cells = <2>;
	154	#interrupt-cells = <1>;
12b69a59 AE	155	ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
12b69a59 AE	156	0x81000000 0 0 0x81000000 0x5 0 1 0>;
14fd8ed0	157	interrupt-map-mask = <0 0 0 0>;
12b69a59 AE	158	interrupt-map = <0 0 0 0 &mpic 62>;
12b69a59 AE	159	marvell,pcie-port = <1>;
14fd8ed0	160	marvell,pcie-lane = <0>;
12b69a59	161	clocks = <&gateclk 9>;
14fd8ed0 EG	162	status = "disabled";
	163	};
	164	};
	165
467f54b2 GC	166	internal-regs {
	167	pinctrl {
	168	compatible = "marvell,mv78230-pinctrl";
	169	reg = <0x18000 0x38>;
	170
	171	sdio_pins: sdio-pins {
	172	marvell,pins = "mpp30", "mpp31", "mpp32",
	173	"mpp33", "mpp34", "mpp35";
	174	marvell,function = "sd0";
	175	};
6d36e8e0	176	};
9d8f44f0	177
467f54b2 GC	178	gpio0: gpio@18100 {
	179	compatible = "marvell,orion-gpio";
	180	reg = <0x18100 0x40>;
	181	ngpios = <32>;
	182	gpio-controller;
	183	#gpio-cells = <2>;
	184	interrupt-controller;
ca60985c	185	#interrupt-cells = <2>;
467f54b2	186	interrupts = <82>, <83>, <84>, <85>;
9d8f44f0 TP	187	};
9d8f44f0 TP	188
467f54b2 GC	189	gpio1: gpio@18140 {
	190	compatible = "marvell,orion-gpio";
	191	reg = <0x18140 0x40>;
	192	ngpios = <17>;
	193	gpio-controller;
	194	#gpio-cells = <2>;
	195	interrupt-controller;
ca60985c	196	#interrupt-cells = <2>;
467f54b2	197	interrupts = <87>, <88>, <89>;
9d8f44f0	198	};
9d8f44f0	199	};
f3b42b7c TP	200	};
f3b42b7c TP	201	};