[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / armada-xp-mv78260.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Contains definitions specific to the Armada XP MV78260 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78260 SoC";
	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		eth3 = &eth3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-xp-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
		};
	};

	soc {
		/*
		 * MV78260 has 3 PCIe units Gen2.0: Two units can be
		 * configured as x4 or quad x1 lanes. One unit is
		 * x4 only.
		 */
		pcie-controller {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
				0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
				0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
				0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
				0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
				0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
				0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
				0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
				0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */

				0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
				0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
				0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
				0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
				0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
				0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
				0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
				0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */

				0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
				0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */>;

			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 59>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

			pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 60>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 7>;
				status = "disabled";
			};

			pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 61>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 8>;
				status = "disabled";
			};

			pcie@5,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
				reg = <0x2800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 62>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};

			pcie@6,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
				reg = <0x3000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
					  0x81000000 0 0 0x81000000 0x6 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 63>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 10>;
				status = "disabled";
			};

			pcie@7,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
				reg = <0x3800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
					  0x81000000 0 0 0x81000000 0x7 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 64>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 11>;
				status = "disabled";
			};

			pcie@8,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
				reg = <0x4000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
					  0x81000000 0 0 0x81000000 0x8 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 65>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 12>;
				status = "disabled";
			};

			pcie@9,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
				reg = <0x4800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
					  0x81000000 0 0 0x81000000 0x9 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 99>;
				marvell,pcie-port = <2>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 26>;
				status = "disabled";
			};
		};

		internal-regs {
			pinctrl {
				compatible = "marvell,mv78260-pinctrl";
				reg = <0x18000 0x38>;

				sdio_pins: sdio-pins {
					marvell,pins = "mpp30", "mpp31", "mpp32",
						       "mpp33", "mpp34", "mpp35";
					marvell,function = "sd0";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>, <90>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <91>;
			};

			eth3: ethernet@34000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x34000 0x4000>;
				interrupts = <14>;
				clocks = <&gateclk 1>;
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
f3b42b7c TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*
	12	* Contains definitions specific to the Armada XP MV78260 SoC that are not
	13	* common to all Armada XP SoCs.
	14	*/
	15
38149887	16	#include "armada-xp.dtsi"
f3b42b7c TP	17
	18	/ {
	19	model = "Marvell Armada XP MV78260 SoC";
	20	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
	21
397d59f3 TP	22	aliases {
	23	gpio0 = &gpio0;
	24	gpio1 = &gpio1;
	25	gpio2 = &gpio2;
14cfa4bd	26	eth3 = &eth3;
397d59f3 TP	27	};
397d59f3 TP	28
9d202783	29	cpus {
1b2529d0 TP	30	#address-cells = <1>;
1b2529d0 TP	31	#size-cells = <0>;
23157856	32	enable-method = "marvell,armada-xp-smp";
9d202783	33
1b2529d0 TP	34	cpu@0 {
	35	device_type = "cpu";
	36	compatible = "marvell,sheeva-v7";
	37	reg = <0>;
	38	clocks = <&cpuclk 0>;
	39	};
9d202783	40
1b2529d0 TP	41	cpu@1 {
	42	device_type = "cpu";
	43	compatible = "marvell,sheeva-v7";
	44	reg = <1>;
	45	clocks = <&cpuclk 1>;
	46	};
9d202783 GC	47	};
9d202783 GC	48
f3b42b7c	49	soc {
14fd8ed0 EG	50	/*
	51	* MV78260 has 3 PCIe units Gen2.0: Two units can be
	52	* configured as x4 or quad x1 lanes. One unit is
2163e61c	53	* x4 only.
14fd8ed0 EG	54	*/
	55	pcie-controller {
	56	compatible = "marvell,armada-xp-pcie";
	57	status = "disabled";
	58	device_type = "pci";
	59
	60	#address-cells = <3>;
	61	#size-cells = <2>;
	62
d4fa9941	63	msi-parent = <&mpic>;
14fd8ed0 EG	64	bus-range = <0x00 0xff>;
	65
	66	ranges =
	67	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
	68	0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
	69	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
	70	0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
	71	0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
	72	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
2163e61c AE	73	0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
	74	0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
	75	0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
14fd8ed0 EG	76	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	77	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	78	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
	79	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
	80	0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
	81	0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
	82	0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
	83	0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
2163e61c AE	84
	85	0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
	86	0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
	87	0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
	88	0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
	89	0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
	90	0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
	91	0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
	92	0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
	93
	94	0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
	95	0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
14fd8ed0 EG	96
	97	pcie@1,0 {
	98	device_type = "pci";
	99	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	100	reg = <0x0800 0 0 0 0>;
	101	#address-cells = <3>;
	102	#size-cells = <2>;
	103	#interrupt-cells = <1>;
	104	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	105	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	106	interrupt-map-mask = <0 0 0 0>;
	107	interrupt-map = <0 0 0 0 &mpic 58>;
	108	marvell,pcie-port = <0>;
	109	marvell,pcie-lane = <0>;
	110	clocks = <&gateclk 5>;
	111	status = "disabled";
	112	};
	113
	114	pcie@2,0 {
	115	device_type = "pci";
	116	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	117	reg = <0x1000 0 0 0 0>;
	118	#address-cells = <3>;
	119	#size-cells = <2>;
	120	#interrupt-cells = <1>;
2163e61c AE	121	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
2163e61c AE	122	0x81000000 0 0 0x81000000 0x2 0 1 0>;
14fd8ed0 EG	123	interrupt-map-mask = <0 0 0 0>;
	124	interrupt-map = <0 0 0 0 &mpic 59>;
	125	marvell,pcie-port = <0>;
	126	marvell,pcie-lane = <1>;
	127	clocks = <&gateclk 6>;
	128	status = "disabled";
	129	};
	130
	131	pcie@3,0 {
	132	device_type = "pci";
	133	assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
	134	reg = <0x1800 0 0 0 0>;
	135	#address-cells = <3>;
	136	#size-cells = <2>;
	137	#interrupt-cells = <1>;
	138	ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
	139	0x81000000 0 0 0x81000000 0x3 0 1 0>;
	140	interrupt-map-mask = <0 0 0 0>;
	141	interrupt-map = <0 0 0 0 &mpic 60>;
	142	marvell,pcie-port = <0>;
	143	marvell,pcie-lane = <2>;
	144	clocks = <&gateclk 7>;
	145	status = "disabled";
	146	};
	147
	148	pcie@4,0 {
	149	device_type = "pci";
	150	assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
	151	reg = <0x2000 0 0 0 0>;
	152	#address-cells = <3>;
	153	#size-cells = <2>;
	154	#interrupt-cells = <1>;
	155	ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
	156	0x81000000 0 0 0x81000000 0x4 0 1 0>;
	157	interrupt-map-mask = <0 0 0 0>;
	158	interrupt-map = <0 0 0 0 &mpic 61>;
	159	marvell,pcie-port = <0>;
	160	marvell,pcie-lane = <3>;
	161	clocks = <&gateclk 8>;
	162	status = "disabled";
	163	};
	164
2163e61c	165	pcie@5,0 {
14fd8ed0	166	device_type = "pci";
2163e61c AE	167	assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
2163e61c AE	168	reg = <0x2800 0 0 0 0>;
14fd8ed0 EG	169	#address-cells = <3>;
	170	#size-cells = <2>;
	171	#interrupt-cells = <1>;
2163e61c AE	172	ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
2163e61c AE	173	0x81000000 0 0 0x81000000 0x5 0 1 0>;
14fd8ed0	174	interrupt-map-mask = <0 0 0 0>;
2163e61c AE	175	interrupt-map = <0 0 0 0 &mpic 62>;
2163e61c AE	176	marvell,pcie-port = <1>;
14fd8ed0	177	marvell,pcie-lane = <0>;
2163e61c	178	clocks = <&gateclk 9>;
14fd8ed0 EG	179	status = "disabled";
	180	};
	181
2163e61c	182	pcie@6,0 {
14fd8ed0	183	device_type = "pci";
2163e61c AE	184	assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
2163e61c AE	185	reg = <0x3000 0 0 0 0>;
14fd8ed0 EG	186	#address-cells = <3>;
	187	#size-cells = <2>;
	188	#interrupt-cells = <1>;
2163e61c AE	189	ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
2163e61c AE	190	0x81000000 0 0 0x81000000 0x6 0 1 0>;
14fd8ed0	191	interrupt-map-mask = <0 0 0 0>;
2163e61c AE	192	interrupt-map = <0 0 0 0 &mpic 63>;
	193	marvell,pcie-port = <1>;
	194	marvell,pcie-lane = <1>;
	195	clocks = <&gateclk 10>;
	196	status = "disabled";
	197	};
	198
	199	pcie@7,0 {
	200	device_type = "pci";
	201	assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
	202	reg = <0x3800 0 0 0 0>;
	203	#address-cells = <3>;
	204	#size-cells = <2>;
	205	#interrupt-cells = <1>;
	206	ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
	207	0x81000000 0 0 0x81000000 0x7 0 1 0>;
	208	interrupt-map-mask = <0 0 0 0>;
	209	interrupt-map = <0 0 0 0 &mpic 64>;
	210	marvell,pcie-port = <1>;
	211	marvell,pcie-lane = <2>;
	212	clocks = <&gateclk 11>;
	213	status = "disabled";
	214	};
	215
	216	pcie@8,0 {
	217	device_type = "pci";
	218	assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
	219	reg = <0x4000 0 0 0 0>;
	220	#address-cells = <3>;
	221	#size-cells = <2>;
	222	#interrupt-cells = <1>;
	223	ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
	224	0x81000000 0 0 0x81000000 0x8 0 1 0>;
	225	interrupt-map-mask = <0 0 0 0>;
	226	interrupt-map = <0 0 0 0 &mpic 65>;
	227	marvell,pcie-port = <1>;
	228	marvell,pcie-lane = <3>;
	229	clocks = <&gateclk 12>;
	230	status = "disabled";
	231	};
	232
	233	pcie@9,0 {
	234	device_type = "pci";
	235	assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
	236	reg = <0x4800 0 0 0 0>;
	237	#address-cells = <3>;
	238	#size-cells = <2>;
	239	#interrupt-cells = <1>;
	240	ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
	241	0x81000000 0 0 0x81000000 0x9 0 1 0>;
	242	interrupt-map-mask = <0 0 0 0>;
	243	interrupt-map = <0 0 0 0 &mpic 99>;
	244	marvell,pcie-port = <2>;
14fd8ed0	245	marvell,pcie-lane = <0>;
2163e61c	246	clocks = <&gateclk 26>;
14fd8ed0 EG	247	status = "disabled";
	248	};
	249	};
	250
467f54b2 GC	251	internal-regs {
	252	pinctrl {
	253	compatible = "marvell,mv78260-pinctrl";
	254	reg = <0x18000 0x38>;
	255
	256	sdio_pins: sdio-pins {
	257	marvell,pins = "mpp30", "mpp31", "mpp32",
	258	"mpp33", "mpp34", "mpp35";
	259	marvell,function = "sd0";
	260	};
6d36e8e0	261	};
397d59f3	262
467f54b2 GC	263	gpio0: gpio@18100 {
	264	compatible = "marvell,orion-gpio";
	265	reg = <0x18100 0x40>;
	266	ngpios = <32>;
	267	gpio-controller;
	268	#gpio-cells = <2>;
	269	interrupt-controller;
ca60985c	270	#interrupt-cells = <2>;
467f54b2 GC	271	interrupts = <82>, <83>, <84>, <85>;
467f54b2 GC	272	};
397d59f3	273
467f54b2 GC	274	gpio1: gpio@18140 {
	275	compatible = "marvell,orion-gpio";
	276	reg = <0x18140 0x40>;
	277	ngpios = <32>;
	278	gpio-controller;
	279	#gpio-cells = <2>;
	280	interrupt-controller;
ca60985c	281	#interrupt-cells = <2>;
467f54b2 GC	282	interrupts = <87>, <88>, <89>, <90>;
467f54b2 GC	283	};
397d59f3	284
467f54b2 GC	285	gpio2: gpio@18180 {
	286	compatible = "marvell,orion-gpio";
	287	reg = <0x18180 0x40>;
	288	ngpios = <3>;
	289	gpio-controller;
	290	#gpio-cells = <2>;
	291	interrupt-controller;
ca60985c	292	#interrupt-cells = <2>;
467f54b2 GC	293	interrupts = <91>;
467f54b2 GC	294	};
77916519	295
14cfa4bd	296	eth3: ethernet@34000 {
77916519	297	compatible = "marvell,armada-370-neta";
cdd8e498	298	reg = <0x34000 0x4000>;
77916519 TP	299	interrupts = <14>;
	300	clocks = <&gateclk 1>;
	301	status = "disabled";
9d8f44f0	302	};
9d8f44f0	303	};
f3b42b7c TP	304	};
f3b42b7c TP	305	};