]>
Commit | Line | Data |
---|---|---|
f3b42b7c TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada XP family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | * | |
12 | * Contains definitions specific to the Armada XP MV78260 SoC that are not | |
13 | * common to all Armada XP SoCs. | |
14 | */ | |
15 | ||
16 | /include/ "armada-xp.dtsi" | |
17 | ||
18 | / { | |
19 | model = "Marvell Armada XP MV78260 SoC"; | |
20 | compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; | |
21 | ||
397d59f3 TP |
22 | aliases { |
23 | gpio0 = &gpio0; | |
24 | gpio1 = &gpio1; | |
25 | gpio2 = &gpio2; | |
26 | }; | |
27 | ||
9d202783 | 28 | cpus { |
1b2529d0 TP |
29 | #address-cells = <1>; |
30 | #size-cells = <0>; | |
9d202783 | 31 | |
1b2529d0 TP |
32 | cpu@0 { |
33 | device_type = "cpu"; | |
34 | compatible = "marvell,sheeva-v7"; | |
35 | reg = <0>; | |
36 | clocks = <&cpuclk 0>; | |
37 | }; | |
9d202783 | 38 | |
1b2529d0 TP |
39 | cpu@1 { |
40 | device_type = "cpu"; | |
41 | compatible = "marvell,sheeva-v7"; | |
42 | reg = <1>; | |
43 | clocks = <&cpuclk 1>; | |
44 | }; | |
9d202783 GC |
45 | }; |
46 | ||
f3b42b7c | 47 | soc { |
467f54b2 GC |
48 | internal-regs { |
49 | pinctrl { | |
50 | compatible = "marvell,mv78260-pinctrl"; | |
51 | reg = <0x18000 0x38>; | |
52 | ||
53 | sdio_pins: sdio-pins { | |
54 | marvell,pins = "mpp30", "mpp31", "mpp32", | |
55 | "mpp33", "mpp34", "mpp35"; | |
56 | marvell,function = "sd0"; | |
57 | }; | |
6d36e8e0 | 58 | }; |
397d59f3 | 59 | |
467f54b2 GC |
60 | gpio0: gpio@18100 { |
61 | compatible = "marvell,orion-gpio"; | |
62 | reg = <0x18100 0x40>; | |
63 | ngpios = <32>; | |
64 | gpio-controller; | |
65 | #gpio-cells = <2>; | |
66 | interrupt-controller; | |
67 | #interrupts-cells = <2>; | |
68 | interrupts = <82>, <83>, <84>, <85>; | |
69 | }; | |
397d59f3 | 70 | |
467f54b2 GC |
71 | gpio1: gpio@18140 { |
72 | compatible = "marvell,orion-gpio"; | |
73 | reg = <0x18140 0x40>; | |
74 | ngpios = <32>; | |
75 | gpio-controller; | |
76 | #gpio-cells = <2>; | |
77 | interrupt-controller; | |
78 | #interrupts-cells = <2>; | |
79 | interrupts = <87>, <88>, <89>, <90>; | |
80 | }; | |
397d59f3 | 81 | |
467f54b2 GC |
82 | gpio2: gpio@18180 { |
83 | compatible = "marvell,orion-gpio"; | |
84 | reg = <0x18180 0x40>; | |
85 | ngpios = <3>; | |
86 | gpio-controller; | |
87 | #gpio-cells = <2>; | |
88 | interrupt-controller; | |
89 | #interrupts-cells = <2>; | |
90 | interrupts = <91>; | |
91 | }; | |
77916519 | 92 | |
467f54b2 | 93 | ethernet@34000 { |
77916519 | 94 | compatible = "marvell,armada-370-neta"; |
cdd8e498 | 95 | reg = <0x34000 0x4000>; |
77916519 TP |
96 | interrupts = <14>; |
97 | clocks = <&gateclk 1>; | |
98 | status = "disabled"; | |
9d8f44f0 TP |
99 | }; |
100 | ||
467f54b2 GC |
101 | /* |
102 | * MV78260 has 3 PCIe units Gen2.0: Two units can be | |
103 | * configured as x4 or quad x1 lanes. One unit is | |
104 | * x4/x1. | |
105 | */ | |
106 | pcie-controller { | |
107 | compatible = "marvell,armada-xp-pcie"; | |
9d8f44f0 | 108 | status = "disabled"; |
9d8f44f0 | 109 | device_type = "pci"; |
9d8f44f0 | 110 | |
9d8f44f0 TP |
111 | #address-cells = <3>; |
112 | #size-cells = <2>; | |
9d8f44f0 | 113 | |
467f54b2 GC |
114 | bus-range = <0x00 0xff>; |
115 | ||
116 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ | |
117 | 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ | |
118 | 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ | |
119 | 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ | |
120 | 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ | |
121 | 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ | |
122 | 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ | |
123 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | |
124 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | |
125 | ||
126 | pcie@1,0 { | |
127 | device_type = "pci"; | |
128 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
129 | reg = <0x0800 0 0 0 0>; | |
130 | #address-cells = <3>; | |
131 | #size-cells = <2>; | |
132 | #interrupt-cells = <1>; | |
133 | ranges; | |
134 | interrupt-map-mask = <0 0 0 0>; | |
135 | interrupt-map = <0 0 0 0 &mpic 58>; | |
136 | marvell,pcie-port = <0>; | |
137 | marvell,pcie-lane = <0>; | |
138 | clocks = <&gateclk 5>; | |
139 | status = "disabled"; | |
140 | }; | |
141 | ||
142 | pcie@2,0 { | |
143 | device_type = "pci"; | |
144 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | |
145 | reg = <0x1000 0 0 0 0>; | |
146 | #address-cells = <3>; | |
147 | #size-cells = <2>; | |
148 | #interrupt-cells = <1>; | |
149 | ranges; | |
150 | interrupt-map-mask = <0 0 0 0>; | |
151 | interrupt-map = <0 0 0 0 &mpic 59>; | |
152 | marvell,pcie-port = <0>; | |
153 | marvell,pcie-lane = <1>; | |
154 | clocks = <&gateclk 6>; | |
155 | status = "disabled"; | |
156 | }; | |
157 | ||
158 | pcie@3,0 { | |
159 | device_type = "pci"; | |
160 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | |
161 | reg = <0x1800 0 0 0 0>; | |
162 | #address-cells = <3>; | |
163 | #size-cells = <2>; | |
164 | #interrupt-cells = <1>; | |
165 | ranges; | |
166 | interrupt-map-mask = <0 0 0 0>; | |
167 | interrupt-map = <0 0 0 0 &mpic 60>; | |
168 | marvell,pcie-port = <0>; | |
169 | marvell,pcie-lane = <2>; | |
170 | clocks = <&gateclk 7>; | |
171 | status = "disabled"; | |
172 | }; | |
173 | ||
174 | pcie@4,0 { | |
175 | device_type = "pci"; | |
176 | assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; | |
177 | reg = <0x2000 0 0 0 0>; | |
178 | #address-cells = <3>; | |
179 | #size-cells = <2>; | |
180 | #interrupt-cells = <1>; | |
181 | ranges; | |
182 | interrupt-map-mask = <0 0 0 0>; | |
183 | interrupt-map = <0 0 0 0 &mpic 61>; | |
184 | marvell,pcie-port = <0>; | |
185 | marvell,pcie-lane = <3>; | |
186 | clocks = <&gateclk 8>; | |
187 | status = "disabled"; | |
188 | }; | |
189 | ||
190 | pcie@9,0 { | |
191 | device_type = "pci"; | |
192 | assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; | |
193 | reg = <0x4800 0 0 0 0>; | |
194 | #address-cells = <3>; | |
195 | #size-cells = <2>; | |
196 | #interrupt-cells = <1>; | |
197 | ranges; | |
198 | interrupt-map-mask = <0 0 0 0>; | |
199 | interrupt-map = <0 0 0 0 &mpic 99>; | |
200 | marvell,pcie-port = <2>; | |
201 | marvell,pcie-lane = <0>; | |
202 | clocks = <&gateclk 26>; | |
203 | status = "disabled"; | |
204 | }; | |
205 | ||
206 | pcie@10,0 { | |
207 | device_type = "pci"; | |
208 | assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; | |
209 | reg = <0x5000 0 0 0 0>; | |
210 | #address-cells = <3>; | |
211 | #size-cells = <2>; | |
212 | #interrupt-cells = <1>; | |
213 | ranges; | |
214 | interrupt-map-mask = <0 0 0 0>; | |
215 | interrupt-map = <0 0 0 0 &mpic 103>; | |
216 | marvell,pcie-port = <3>; | |
217 | marvell,pcie-lane = <0>; | |
218 | clocks = <&gateclk 27>; | |
219 | status = "disabled"; | |
220 | }; | |
9d8f44f0 TP |
221 | }; |
222 | }; | |
f3b42b7c TP |
223 | }; |
224 | }; |