[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / armada-xp-mv78260.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * Contains definitions specific to the Armada XP MV78260 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78260 SoC";
	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-xp-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
			clock-latency = <1000000>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
			clock-latency = <1000000>;
		};
	};

	soc {
		/*
		 * MV78260 has 3 PCIe units Gen2.0: Two units can be
		 * configured as x4 or quad x1 lanes. One unit is
		 * x4 only.
		 */
		pciec: pcie@82000000 {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
				0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
				0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
				0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
				0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
				0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
				0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
				0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
				0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */

				0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
				0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
				0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
				0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
				0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
				0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
				0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
				0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */

				0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
				0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */>;

			pcie1: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie2: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 59>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

			pcie3: pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 60>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 7>;
				status = "disabled";
			};

			pcie4: pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 61>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 8>;
				status = "disabled";
			};

			pcie5: pcie@5,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
				reg = <0x2800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 62>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};

			pcie6: pcie@6,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
				reg = <0x3000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
					  0x81000000 0 0 0x81000000 0x6 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 63>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 10>;
				status = "disabled";
			};

			pcie7: pcie@7,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
				reg = <0x3800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
					  0x81000000 0 0 0x81000000 0x7 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 64>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 11>;
				status = "disabled";
			};

			pcie8: pcie@8,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
				reg = <0x4000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
					  0x81000000 0 0 0x81000000 0x8 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 65>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 12>;
				status = "disabled";
			};

			pcie9: pcie@9,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
				reg = <0x4800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
					  0x81000000 0 0 0x81000000 0x9 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 99>;
				marvell,pcie-port = <2>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 26>;
				status = "disabled";
			};
		};

		internal-regs {
			gpio0: gpio@18100 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18100 0x40>, <0x181c0 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
				clocks = <&coreclk 0>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18140 0x40>, <0x181c8 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>, <90>;
				clocks = <&coreclk 0>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <91>;
			};

			eth3: ethernet@34000 {
				compatible = "marvell,armada-xp-neta";
				reg = <0x34000 0x4000>;
				interrupts = <14>;
				clocks = <&gateclk 1>;
				status = "disabled";
			};
		};
	};
};

&pinctrl {
	compatible = "marvell,mv78260-pinctrl";
};
Commit	Line	Data
f3b42b7c TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	7	*
3f0526bf GC	8	* This file is dual-licensed: you can use it either under the terms
	9	* of the GPL or the X11 license, at your option. Note that this dual
	10	* licensing only applies to this file, and not this project as a
	11	* whole.
	12	*
	13	* a) This file is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of the
	16	* License, or (at your option) any later version.
	17	*
24f0b6fe	18	* This file is distributed in the hope that it will be useful,
3f0526bf GC	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
24f0b6fe	23	* Or, alternatively,
3f0526bf GC	24	*
	25	* b) Permission is hereby granted, free of charge, to any person
	26	* obtaining a copy of this software and associated documentation
	27	* files (the "Software"), to deal in the Software without
24f0b6fe	28	* restriction, including without limitation the rights to use,
3f0526bf GC	29	* copy, modify, merge, publish, distribute, sublicense, and/or
	30	* sell copies of the Software, and to permit persons to whom the
	31	* Software is furnished to do so, subject to the following
	32	* conditions:
	33	*
	34	* The above copyright notice and this permission notice shall be
	35	* included in all copies or substantial portions of the Software.
	36	*
24f0b6fe	37	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3f0526bf GC	38	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	39	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	40	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
24f0b6fe	41	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3f0526bf GC	42	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	43	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	44	* OTHER DEALINGS IN THE SOFTWARE.
f3b42b7c TP	45	*
	46	* Contains definitions specific to the Armada XP MV78260 SoC that are not
	47	* common to all Armada XP SoCs.
	48	*/
	49
38149887	50	#include "armada-xp.dtsi"
f3b42b7c TP	51
	52	/ {
	53	model = "Marvell Armada XP MV78260 SoC";
	54	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
	55
397d59f3 TP	56	aliases {
	57	gpio0 = &gpio0;
	58	gpio1 = &gpio1;
	59	gpio2 = &gpio2;
	60	};
	61
9d202783	62	cpus {
1b2529d0 TP	63	#address-cells = <1>;
1b2529d0 TP	64	#size-cells = <0>;
23157856	65	enable-method = "marvell,armada-xp-smp";
9d202783	66
1b2529d0 TP	67	cpu@0 {
	68	device_type = "cpu";
	69	compatible = "marvell,sheeva-v7";
	70	reg = <0>;
	71	clocks = <&cpuclk 0>;
38436078	72	clock-latency = <1000000>;
1b2529d0	73	};
9d202783	74
1b2529d0 TP	75	cpu@1 {
	76	device_type = "cpu";
	77	compatible = "marvell,sheeva-v7";
	78	reg = <1>;
	79	clocks = <&cpuclk 1>;
38436078	80	clock-latency = <1000000>;
1b2529d0	81	};
9d202783 GC	82	};
9d202783 GC	83
f3b42b7c	84	soc {
14fd8ed0 EG	85	/*
	86	* MV78260 has 3 PCIe units Gen2.0: Two units can be
	87	* configured as x4 or quad x1 lanes. One unit is
2163e61c	88	* x4 only.
14fd8ed0	89	*/
28fbb9c5	90	pciec: pcie@82000000 {
14fd8ed0 EG	91	compatible = "marvell,armada-xp-pcie";
	92	status = "disabled";
	93	device_type = "pci";
	94
	95	#address-cells = <3>;
	96	#size-cells = <2>;
	97
d4fa9941	98	msi-parent = <&mpic>;
14fd8ed0 EG	99	bus-range = <0x00 0xff>;
	100
	101	ranges =
	102	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
	103	0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
	104	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
	105	0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
	106	0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
	107	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
2163e61c AE	108	0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
	109	0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
	110	0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
14fd8ed0 EG	111	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	112	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	113	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
	114	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
	115	0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
	116	0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
	117	0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
	118	0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
2163e61c AE	119
	120	0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
	121	0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
	122	0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
	123	0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
	124	0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
	125	0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
	126	0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
	127	0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
	128
	129	0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
	130	0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
14fd8ed0	131
11f7135b	132	pcie1: pcie@1,0 {
14fd8ed0 EG	133	device_type = "pci";
	134	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	135	reg = <0x0800 0 0 0 0>;
	136	#address-cells = <3>;
	137	#size-cells = <2>;
	138	#interrupt-cells = <1>;
	139	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	140	0x81000000 0 0 0x81000000 0x1 0 1 0>;
28fbb9c5	141	bus-range = <0x00 0xff>;
14fd8ed0 EG	142	interrupt-map-mask = <0 0 0 0>;
	143	interrupt-map = <0 0 0 0 &mpic 58>;
	144	marvell,pcie-port = <0>;
	145	marvell,pcie-lane = <0>;
	146	clocks = <&gateclk 5>;
	147	status = "disabled";
	148	};
	149
11f7135b	150	pcie2: pcie@2,0 {
14fd8ed0 EG	151	device_type = "pci";
	152	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	153	reg = <0x1000 0 0 0 0>;
	154	#address-cells = <3>;
	155	#size-cells = <2>;
	156	#interrupt-cells = <1>;
2163e61c AE	157	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
2163e61c AE	158	0x81000000 0 0 0x81000000 0x2 0 1 0>;
28fbb9c5	159	bus-range = <0x00 0xff>;
14fd8ed0 EG	160	interrupt-map-mask = <0 0 0 0>;
	161	interrupt-map = <0 0 0 0 &mpic 59>;
	162	marvell,pcie-port = <0>;
	163	marvell,pcie-lane = <1>;
	164	clocks = <&gateclk 6>;
	165	status = "disabled";
	166	};
	167
11f7135b	168	pcie3: pcie@3,0 {
14fd8ed0 EG	169	device_type = "pci";
	170	assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
	171	reg = <0x1800 0 0 0 0>;
	172	#address-cells = <3>;
	173	#size-cells = <2>;
	174	#interrupt-cells = <1>;
	175	ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
	176	0x81000000 0 0 0x81000000 0x3 0 1 0>;
28fbb9c5	177	bus-range = <0x00 0xff>;
14fd8ed0 EG	178	interrupt-map-mask = <0 0 0 0>;
	179	interrupt-map = <0 0 0 0 &mpic 60>;
	180	marvell,pcie-port = <0>;
	181	marvell,pcie-lane = <2>;
	182	clocks = <&gateclk 7>;
	183	status = "disabled";
	184	};
	185
11f7135b	186	pcie4: pcie@4,0 {
14fd8ed0 EG	187	device_type = "pci";
	188	assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
	189	reg = <0x2000 0 0 0 0>;
	190	#address-cells = <3>;
	191	#size-cells = <2>;
	192	#interrupt-cells = <1>;
	193	ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
	194	0x81000000 0 0 0x81000000 0x4 0 1 0>;
28fbb9c5	195	bus-range = <0x00 0xff>;
14fd8ed0 EG	196	interrupt-map-mask = <0 0 0 0>;
	197	interrupt-map = <0 0 0 0 &mpic 61>;
	198	marvell,pcie-port = <0>;
	199	marvell,pcie-lane = <3>;
	200	clocks = <&gateclk 8>;
	201	status = "disabled";
	202	};
	203
11f7135b	204	pcie5: pcie@5,0 {
14fd8ed0	205	device_type = "pci";
2163e61c AE	206	assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
2163e61c AE	207	reg = <0x2800 0 0 0 0>;
14fd8ed0 EG	208	#address-cells = <3>;
	209	#size-cells = <2>;
	210	#interrupt-cells = <1>;
2163e61c AE	211	ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
2163e61c AE	212	0x81000000 0 0 0x81000000 0x5 0 1 0>;
28fbb9c5	213	bus-range = <0x00 0xff>;
14fd8ed0	214	interrupt-map-mask = <0 0 0 0>;
2163e61c AE	215	interrupt-map = <0 0 0 0 &mpic 62>;
2163e61c AE	216	marvell,pcie-port = <1>;
14fd8ed0	217	marvell,pcie-lane = <0>;
2163e61c	218	clocks = <&gateclk 9>;
14fd8ed0 EG	219	status = "disabled";
	220	};
	221
11f7135b	222	pcie6: pcie@6,0 {
14fd8ed0	223	device_type = "pci";
2163e61c AE	224	assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
2163e61c AE	225	reg = <0x3000 0 0 0 0>;
14fd8ed0 EG	226	#address-cells = <3>;
	227	#size-cells = <2>;
	228	#interrupt-cells = <1>;
2163e61c AE	229	ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
2163e61c AE	230	0x81000000 0 0 0x81000000 0x6 0 1 0>;
28fbb9c5	231	bus-range = <0x00 0xff>;
14fd8ed0	232	interrupt-map-mask = <0 0 0 0>;
2163e61c AE	233	interrupt-map = <0 0 0 0 &mpic 63>;
	234	marvell,pcie-port = <1>;
	235	marvell,pcie-lane = <1>;
	236	clocks = <&gateclk 10>;
	237	status = "disabled";
	238	};
	239
11f7135b	240	pcie7: pcie@7,0 {
2163e61c AE	241	device_type = "pci";
	242	assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
	243	reg = <0x3800 0 0 0 0>;
	244	#address-cells = <3>;
	245	#size-cells = <2>;
	246	#interrupt-cells = <1>;
	247	ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
	248	0x81000000 0 0 0x81000000 0x7 0 1 0>;
28fbb9c5	249	bus-range = <0x00 0xff>;
2163e61c AE	250	interrupt-map-mask = <0 0 0 0>;
	251	interrupt-map = <0 0 0 0 &mpic 64>;
	252	marvell,pcie-port = <1>;
	253	marvell,pcie-lane = <2>;
	254	clocks = <&gateclk 11>;
	255	status = "disabled";
	256	};
	257
11f7135b	258	pcie8: pcie@8,0 {
2163e61c AE	259	device_type = "pci";
	260	assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
	261	reg = <0x4000 0 0 0 0>;
	262	#address-cells = <3>;
	263	#size-cells = <2>;
	264	#interrupt-cells = <1>;
	265	ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
	266	0x81000000 0 0 0x81000000 0x8 0 1 0>;
28fbb9c5	267	bus-range = <0x00 0xff>;
2163e61c AE	268	interrupt-map-mask = <0 0 0 0>;
	269	interrupt-map = <0 0 0 0 &mpic 65>;
	270	marvell,pcie-port = <1>;
	271	marvell,pcie-lane = <3>;
	272	clocks = <&gateclk 12>;
	273	status = "disabled";
	274	};
	275
11f7135b	276	pcie9: pcie@9,0 {
2163e61c AE	277	device_type = "pci";
	278	assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
	279	reg = <0x4800 0 0 0 0>;
	280	#address-cells = <3>;
	281	#size-cells = <2>;
	282	#interrupt-cells = <1>;
	283	ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
	284	0x81000000 0 0 0x81000000 0x9 0 1 0>;
28fbb9c5	285	bus-range = <0x00 0xff>;
2163e61c AE	286	interrupt-map-mask = <0 0 0 0>;
	287	interrupt-map = <0 0 0 0 &mpic 99>;
	288	marvell,pcie-port = <2>;
14fd8ed0	289	marvell,pcie-lane = <0>;
2163e61c	290	clocks = <&gateclk 26>;
14fd8ed0 EG	291	status = "disabled";
	292	};
	293	};
	294
467f54b2	295	internal-regs {
467f54b2	296	gpio0: gpio@18100 {
0c8c9ff8 AL	297	compatible = "marvell,armada-370-gpio",
	298	"marvell,orion-gpio";
	299	reg = <0x18100 0x40>, <0x181c0 0x08>;
	300	reg-names = "gpio", "pwm";
467f54b2 GC	301	ngpios = <32>;
	302	gpio-controller;
	303	#gpio-cells = <2>;
0c8c9ff8	304	#pwm-cells = <2>;
467f54b2	305	interrupt-controller;
ca60985c	306	#interrupt-cells = <2>;
467f54b2	307	interrupts = <82>, <83>, <84>, <85>;
0c8c9ff8	308	clocks = <&coreclk 0>;
467f54b2	309	};
397d59f3	310
467f54b2	311	gpio1: gpio@18140 {
0c8c9ff8 AL	312	compatible = "marvell,armada-370-gpio",
	313	"marvell,orion-gpio";
	314	reg = <0x18140 0x40>, <0x181c8 0x08>;
	315	reg-names = "gpio", "pwm";
467f54b2 GC	316	ngpios = <32>;
	317	gpio-controller;
	318	#gpio-cells = <2>;
0c8c9ff8	319	#pwm-cells = <2>;
467f54b2	320	interrupt-controller;
ca60985c	321	#interrupt-cells = <2>;
467f54b2	322	interrupts = <87>, <88>, <89>, <90>;
0c8c9ff8	323	clocks = <&coreclk 0>;
467f54b2	324	};
397d59f3	325
467f54b2	326	gpio2: gpio@18180 {
0c8c9ff8 AL	327	compatible = "marvell,armada-370-gpio",
0c8c9ff8 AL	328	"marvell,orion-gpio";
467f54b2 GC	329	reg = <0x18180 0x40>;
	330	ngpios = <3>;
	331	gpio-controller;
	332	#gpio-cells = <2>;
	333	interrupt-controller;
ca60985c	334	#interrupt-cells = <2>;
467f54b2 GC	335	interrupts = <91>;
467f54b2 GC	336	};
77916519	337
14cfa4bd	338	eth3: ethernet@34000 {
ea3b55fe	339	compatible = "marvell,armada-xp-neta";
cdd8e498	340	reg = <0x34000 0x4000>;
77916519 TP	341	interrupts = <14>;
	342	clocks = <&gateclk 1>;
	343	status = "disabled";
9d8f44f0	344	};
9d8f44f0	345	};
f3b42b7c TP	346	};
f3b42b7c TP	347	};
01c43422 SH	348
	349	&pinctrl {
	350	compatible = "marvell,mv78260-pinctrl";
	351	};