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Commit | Line | Data |
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f3b42b7c TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada XP family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | * | |
12 | * Contains definitions specific to the Armada XP MV78460 SoC that are not | |
13 | * common to all Armada XP SoCs. | |
14 | */ | |
15 | ||
38149887 | 16 | #include "armada-xp.dtsi" |
f3b42b7c TP |
17 | |
18 | / { | |
19 | model = "Marvell Armada XP MV78460 SoC"; | |
20 | compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; | |
21 | ||
397d59f3 TP |
22 | aliases { |
23 | gpio0 = &gpio0; | |
24 | gpio1 = &gpio1; | |
25 | gpio2 = &gpio2; | |
be5a9389 | 26 | eth3 = ð3; |
397d59f3 TP |
27 | }; |
28 | ||
9d202783 GC |
29 | |
30 | cpus { | |
1b2529d0 TP |
31 | #address-cells = <1>; |
32 | #size-cells = <0>; | |
23157856 | 33 | enable-method = "marvell,armada-xp-smp"; |
9d202783 | 34 | |
1b2529d0 TP |
35 | cpu@0 { |
36 | device_type = "cpu"; | |
37 | compatible = "marvell,sheeva-v7"; | |
38 | reg = <0>; | |
39 | clocks = <&cpuclk 0>; | |
38436078 | 40 | clock-latency = <1000000>; |
1b2529d0 | 41 | }; |
9d202783 | 42 | |
1b2529d0 TP |
43 | cpu@1 { |
44 | device_type = "cpu"; | |
45 | compatible = "marvell,sheeva-v7"; | |
46 | reg = <1>; | |
47 | clocks = <&cpuclk 1>; | |
38436078 | 48 | clock-latency = <1000000>; |
1b2529d0 | 49 | }; |
9d202783 | 50 | |
1b2529d0 TP |
51 | cpu@2 { |
52 | device_type = "cpu"; | |
53 | compatible = "marvell,sheeva-v7"; | |
54 | reg = <2>; | |
55 | clocks = <&cpuclk 2>; | |
38436078 | 56 | clock-latency = <1000000>; |
1b2529d0 | 57 | }; |
9d202783 | 58 | |
1b2529d0 TP |
59 | cpu@3 { |
60 | device_type = "cpu"; | |
61 | compatible = "marvell,sheeva-v7"; | |
62 | reg = <3>; | |
63 | clocks = <&cpuclk 3>; | |
38436078 | 64 | clock-latency = <1000000>; |
1b2529d0 | 65 | }; |
9d202783 GC |
66 | }; |
67 | ||
f3b42b7c | 68 | soc { |
14fd8ed0 EG |
69 | /* |
70 | * MV78460 has 4 PCIe units Gen2.0: Two units can be | |
71 | * configured as x4 or quad x1 lanes. Two units are | |
72 | * x4/x1. | |
73 | */ | |
74 | pcie-controller { | |
75 | compatible = "marvell,armada-xp-pcie"; | |
76 | status = "disabled"; | |
77 | device_type = "pci"; | |
78 | ||
79 | #address-cells = <3>; | |
80 | #size-cells = <2>; | |
81 | ||
d4fa9941 | 82 | msi-parent = <&mpic>; |
14fd8ed0 EG |
83 | bus-range = <0x00 0xff>; |
84 | ||
85 | ranges = | |
86 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ | |
87 | 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ | |
88 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ | |
89 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ | |
90 | 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ | |
91 | 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ | |
92 | 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ | |
93 | 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ | |
94 | 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ | |
95 | 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ | |
96 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | |
97 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ | |
98 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ | |
99 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ | |
100 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ | |
101 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ | |
102 | 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ | |
103 | 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ | |
104 | ||
105 | 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ | |
106 | 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ | |
107 | 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ | |
108 | 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ | |
109 | 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ | |
110 | 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ | |
111 | 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ | |
112 | 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ | |
113 | ||
114 | 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ | |
115 | 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ | |
116 | ||
117 | 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ | |
118 | 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; | |
119 | ||
120 | pcie@1,0 { | |
121 | device_type = "pci"; | |
122 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
123 | reg = <0x0800 0 0 0 0>; | |
124 | #address-cells = <3>; | |
125 | #size-cells = <2>; | |
126 | #interrupt-cells = <1>; | |
127 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
128 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
129 | interrupt-map-mask = <0 0 0 0>; | |
130 | interrupt-map = <0 0 0 0 &mpic 58>; | |
131 | marvell,pcie-port = <0>; | |
132 | marvell,pcie-lane = <0>; | |
133 | clocks = <&gateclk 5>; | |
134 | status = "disabled"; | |
135 | }; | |
136 | ||
137 | pcie@2,0 { | |
138 | device_type = "pci"; | |
139 | assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; | |
140 | reg = <0x1000 0 0 0 0>; | |
141 | #address-cells = <3>; | |
142 | #size-cells = <2>; | |
143 | #interrupt-cells = <1>; | |
144 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
145 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
146 | interrupt-map-mask = <0 0 0 0>; | |
147 | interrupt-map = <0 0 0 0 &mpic 59>; | |
148 | marvell,pcie-port = <0>; | |
149 | marvell,pcie-lane = <1>; | |
150 | clocks = <&gateclk 6>; | |
151 | status = "disabled"; | |
152 | }; | |
153 | ||
154 | pcie@3,0 { | |
155 | device_type = "pci"; | |
156 | assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; | |
157 | reg = <0x1800 0 0 0 0>; | |
158 | #address-cells = <3>; | |
159 | #size-cells = <2>; | |
160 | #interrupt-cells = <1>; | |
161 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | |
162 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | |
163 | interrupt-map-mask = <0 0 0 0>; | |
164 | interrupt-map = <0 0 0 0 &mpic 60>; | |
165 | marvell,pcie-port = <0>; | |
166 | marvell,pcie-lane = <2>; | |
167 | clocks = <&gateclk 7>; | |
168 | status = "disabled"; | |
169 | }; | |
170 | ||
171 | pcie@4,0 { | |
172 | device_type = "pci"; | |
173 | assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; | |
174 | reg = <0x2000 0 0 0 0>; | |
175 | #address-cells = <3>; | |
176 | #size-cells = <2>; | |
177 | #interrupt-cells = <1>; | |
178 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | |
179 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | |
180 | interrupt-map-mask = <0 0 0 0>; | |
181 | interrupt-map = <0 0 0 0 &mpic 61>; | |
182 | marvell,pcie-port = <0>; | |
183 | marvell,pcie-lane = <3>; | |
184 | clocks = <&gateclk 8>; | |
185 | status = "disabled"; | |
186 | }; | |
187 | ||
188 | pcie@5,0 { | |
189 | device_type = "pci"; | |
190 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | |
191 | reg = <0x2800 0 0 0 0>; | |
192 | #address-cells = <3>; | |
193 | #size-cells = <2>; | |
194 | #interrupt-cells = <1>; | |
195 | ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 | |
196 | 0x81000000 0 0 0x81000000 0x5 0 1 0>; | |
197 | interrupt-map-mask = <0 0 0 0>; | |
198 | interrupt-map = <0 0 0 0 &mpic 62>; | |
199 | marvell,pcie-port = <1>; | |
200 | marvell,pcie-lane = <0>; | |
201 | clocks = <&gateclk 9>; | |
202 | status = "disabled"; | |
203 | }; | |
204 | ||
205 | pcie@6,0 { | |
206 | device_type = "pci"; | |
207 | assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; | |
208 | reg = <0x3000 0 0 0 0>; | |
209 | #address-cells = <3>; | |
210 | #size-cells = <2>; | |
211 | #interrupt-cells = <1>; | |
212 | ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 | |
213 | 0x81000000 0 0 0x81000000 0x6 0 1 0>; | |
214 | interrupt-map-mask = <0 0 0 0>; | |
215 | interrupt-map = <0 0 0 0 &mpic 63>; | |
216 | marvell,pcie-port = <1>; | |
217 | marvell,pcie-lane = <1>; | |
218 | clocks = <&gateclk 10>; | |
219 | status = "disabled"; | |
220 | }; | |
221 | ||
222 | pcie@7,0 { | |
223 | device_type = "pci"; | |
224 | assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; | |
225 | reg = <0x3800 0 0 0 0>; | |
226 | #address-cells = <3>; | |
227 | #size-cells = <2>; | |
228 | #interrupt-cells = <1>; | |
229 | ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 | |
230 | 0x81000000 0 0 0x81000000 0x7 0 1 0>; | |
231 | interrupt-map-mask = <0 0 0 0>; | |
232 | interrupt-map = <0 0 0 0 &mpic 64>; | |
233 | marvell,pcie-port = <1>; | |
234 | marvell,pcie-lane = <2>; | |
235 | clocks = <&gateclk 11>; | |
236 | status = "disabled"; | |
237 | }; | |
238 | ||
239 | pcie@8,0 { | |
240 | device_type = "pci"; | |
241 | assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; | |
242 | reg = <0x4000 0 0 0 0>; | |
243 | #address-cells = <3>; | |
244 | #size-cells = <2>; | |
245 | #interrupt-cells = <1>; | |
246 | ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 | |
247 | 0x81000000 0 0 0x81000000 0x8 0 1 0>; | |
248 | interrupt-map-mask = <0 0 0 0>; | |
249 | interrupt-map = <0 0 0 0 &mpic 65>; | |
250 | marvell,pcie-port = <1>; | |
251 | marvell,pcie-lane = <3>; | |
252 | clocks = <&gateclk 12>; | |
253 | status = "disabled"; | |
254 | }; | |
255 | ||
256 | pcie@9,0 { | |
257 | device_type = "pci"; | |
258 | assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; | |
259 | reg = <0x4800 0 0 0 0>; | |
260 | #address-cells = <3>; | |
261 | #size-cells = <2>; | |
262 | #interrupt-cells = <1>; | |
263 | ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 | |
264 | 0x81000000 0 0 0x81000000 0x9 0 1 0>; | |
265 | interrupt-map-mask = <0 0 0 0>; | |
266 | interrupt-map = <0 0 0 0 &mpic 99>; | |
267 | marvell,pcie-port = <2>; | |
268 | marvell,pcie-lane = <0>; | |
269 | clocks = <&gateclk 26>; | |
270 | status = "disabled"; | |
271 | }; | |
272 | ||
273 | pcie@10,0 { | |
274 | device_type = "pci"; | |
275 | assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; | |
276 | reg = <0x5000 0 0 0 0>; | |
277 | #address-cells = <3>; | |
278 | #size-cells = <2>; | |
279 | #interrupt-cells = <1>; | |
280 | ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 | |
281 | 0x81000000 0 0 0x81000000 0xa 0 1 0>; | |
282 | interrupt-map-mask = <0 0 0 0>; | |
283 | interrupt-map = <0 0 0 0 &mpic 103>; | |
284 | marvell,pcie-port = <3>; | |
285 | marvell,pcie-lane = <0>; | |
286 | clocks = <&gateclk 27>; | |
287 | status = "disabled"; | |
288 | }; | |
289 | }; | |
290 | ||
467f54b2 | 291 | internal-regs { |
467f54b2 GC |
292 | gpio0: gpio@18100 { |
293 | compatible = "marvell,orion-gpio"; | |
294 | reg = <0x18100 0x40>; | |
295 | ngpios = <32>; | |
296 | gpio-controller; | |
297 | #gpio-cells = <2>; | |
298 | interrupt-controller; | |
ca60985c | 299 | #interrupt-cells = <2>; |
467f54b2 GC |
300 | interrupts = <82>, <83>, <84>, <85>; |
301 | }; | |
397d59f3 | 302 | |
467f54b2 GC |
303 | gpio1: gpio@18140 { |
304 | compatible = "marvell,orion-gpio"; | |
305 | reg = <0x18140 0x40>; | |
306 | ngpios = <32>; | |
307 | gpio-controller; | |
308 | #gpio-cells = <2>; | |
309 | interrupt-controller; | |
ca60985c | 310 | #interrupt-cells = <2>; |
467f54b2 GC |
311 | interrupts = <87>, <88>, <89>, <90>; |
312 | }; | |
397d59f3 | 313 | |
467f54b2 GC |
314 | gpio2: gpio@18180 { |
315 | compatible = "marvell,orion-gpio"; | |
316 | reg = <0x18180 0x40>; | |
317 | ngpios = <3>; | |
318 | gpio-controller; | |
319 | #gpio-cells = <2>; | |
320 | interrupt-controller; | |
ca60985c | 321 | #interrupt-cells = <2>; |
467f54b2 GC |
322 | interrupts = <91>; |
323 | }; | |
77916519 | 324 | |
be5a9389 | 325 | eth3: ethernet@34000 { |
77916519 | 326 | compatible = "marvell,armada-370-neta"; |
cf8088c5 | 327 | reg = <0x34000 0x4000>; |
77916519 TP |
328 | interrupts = <14>; |
329 | clocks = <&gateclk 1>; | |
330 | status = "disabled"; | |
467f54b2 | 331 | }; |
9d8f44f0 | 332 | }; |
f3b42b7c | 333 | }; |
1b2529d0 | 334 | }; |
01c43422 SH |
335 | |
336 | &pinctrl { | |
337 | compatible = "marvell,mv78460-pinctrl"; | |
338 | }; |