]>
Commit | Line | Data |
---|---|---|
9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada XP family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
ee2ff969 GC |
11 | * This file is dual-licensed: you can use it either under the terms |
12 | * of the GPL or the X11 license, at your option. Note that this dual | |
13 | * licensing only applies to this file, and not this project as a | |
14 | * whole. | |
15 | * | |
16 | * a) This file is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of the | |
19 | * License, or (at your option) any later version. | |
20 | * | |
21 | * This file is distributed in the hope that it will be useful | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * Or, alternatively | |
27 | * | |
28 | * b) Permission is hereby granted, free of charge, to any person | |
29 | * obtaining a copy of this software and associated documentation | |
30 | * files (the "Software"), to deal in the Software without | |
31 | * restriction, including without limitation the rights to use | |
32 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
33 | * sell copies of the Software, and to permit persons to whom the | |
34 | * Software is furnished to do so, subject to the following | |
35 | * conditions: | |
36 | * | |
37 | * The above copyright notice and this permission notice shall be | |
38 | * included in all copies or substantial portions of the Software. | |
39 | * | |
40 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
47 | * OTHER DEALINGS IN THE SOFTWARE. | |
9ae6f740 | 48 | * |
10b683cb | 49 | * Contains definitions specific to the Armada XP SoC that are not |
9ae6f740 TP |
50 | * common to all Armada SoCs. |
51 | */ | |
52 | ||
38149887 | 53 | #include "armada-370-xp.dtsi" |
9ae6f740 TP |
54 | |
55 | / { | |
56 | model = "Marvell Armada XP family SoC"; | |
57 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; | |
58 | ||
be5a9389 | 59 | aliases { |
bf6acf16 TP |
60 | serial2 = &uart2; |
61 | serial3 = &uart3; | |
be5a9389 WT |
62 | }; |
63 | ||
b18ea4dc | 64 | soc { |
5e12a613 EG |
65 | compatible = "marvell,armadaxp-mbus", "simple-bus"; |
66 | ||
0cd3754a EG |
67 | bootrom { |
68 | compatible = "marvell,bootrom"; | |
69 | reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; | |
70 | }; | |
71 | ||
467f54b2 | 72 | internal-regs { |
6e6db2be TP |
73 | sdramc@1400 { |
74 | compatible = "marvell,armada-xp-sdram-controller"; | |
75 | reg = <0x1400 0x500>; | |
76 | }; | |
77 | ||
467f54b2 GC |
78 | L2: l2-cache { |
79 | compatible = "marvell,aurora-system-cache"; | |
80 | reg = <0x08000 0x1000>; | |
81 | cache-id-part = <0x100>; | |
292a3546 | 82 | cache-level = <2>; |
a9ce1afb | 83 | cache-unified; |
467f54b2 GC |
84 | wt-override; |
85 | }; | |
2f96fbb7 | 86 | |
547c653b | 87 | spi0: spi@10600 { |
2d295928 GC |
88 | compatible = "marvell,armada-xp-spi", |
89 | "marvell,orion-spi"; | |
547c653b AE |
90 | pinctrl-0 = <&spi0_pins>; |
91 | pinctrl-names = "default"; | |
92 | }; | |
93 | ||
2d295928 GC |
94 | spi1: spi@10680 { |
95 | compatible = "marvell,armada-xp-spi", | |
96 | "marvell,orion-spi"; | |
97 | }; | |
98 | ||
99 | ||
a095b1c7 JC |
100 | i2c0: i2c@11000 { |
101 | compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; | |
102 | reg = <0x11000 0x100>; | |
467f54b2 | 103 | }; |
9ae6f740 | 104 | |
a095b1c7 JC |
105 | i2c1: i2c@11100 { |
106 | compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; | |
107 | reg = <0x11100 0x100>; | |
467f54b2 | 108 | }; |
9ae6f740 | 109 | |
181d9b28 | 110 | uart2: serial@12200 { |
b24212fb | 111 | compatible = "snps,dw-apb-uart"; |
d352f41e AE |
112 | pinctrl-0 = <&uart2_pins>; |
113 | pinctrl-names = "default"; | |
82a68267 | 114 | reg = <0x12200 0x100>; |
9ae6f740 TP |
115 | reg-shift = <2>; |
116 | interrupts = <43>; | |
e366154f | 117 | reg-io-width = <1>; |
64939dc5 | 118 | clocks = <&coreclk 0>; |
9ae6f740 | 119 | status = "disabled"; |
467f54b2 | 120 | }; |
181d9b28 AE |
121 | |
122 | uart3: serial@12300 { | |
b24212fb | 123 | compatible = "snps,dw-apb-uart"; |
d352f41e AE |
124 | pinctrl-0 = <&uart3_pins>; |
125 | pinctrl-names = "default"; | |
82a68267 | 126 | reg = <0x12300 0x100>; |
9ae6f740 TP |
127 | reg-shift = <2>; |
128 | interrupts = <44>; | |
e366154f | 129 | reg-io-width = <1>; |
64939dc5 | 130 | clocks = <&coreclk 0>; |
9ae6f740 | 131 | status = "disabled"; |
467f54b2 | 132 | }; |
9ae6f740 | 133 | |
a095b1c7 JC |
134 | system-controller@18200 { |
135 | compatible = "marvell,armada-370-xp-system-controller"; | |
136 | reg = <0x18200 0x500>; | |
137 | }; | |
138 | ||
139 | gateclk: clock-gating-control@18220 { | |
140 | compatible = "marvell,armada-xp-gating-clock"; | |
141 | reg = <0x18220 0x4>; | |
142 | clocks = <&coreclk 0>; | |
143 | #clock-cells = <1>; | |
467f54b2 | 144 | }; |
9ae6f740 | 145 | |
467f54b2 GC |
146 | coreclk: mvebu-sar@18230 { |
147 | compatible = "marvell,armada-xp-core-clock"; | |
148 | reg = <0x18230 0x08>; | |
149 | #clock-cells = <1>; | |
150 | }; | |
9d202783 | 151 | |
a095b1c7 JC |
152 | thermal@182b0 { |
153 | compatible = "marvell,armadaxp-thermal"; | |
154 | reg = <0x182b0 0x4 | |
155 | 0x184d0 0x4>; | |
156 | status = "okay"; | |
157 | }; | |
158 | ||
467f54b2 GC |
159 | cpuclk: clock-complex@18700 { |
160 | #clock-cells = <1>; | |
161 | compatible = "marvell,armada-xp-cpu-clock"; | |
b7f01842 | 162 | reg = <0x18700 0x24>, <0x1c054 0x10>; |
467f54b2 GC |
163 | clocks = <&coreclk 1>; |
164 | }; | |
9d202783 | 165 | |
24c2573b | 166 | interrupt-controller@20a00 { |
a095b1c7 | 167 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; |
467f54b2 | 168 | }; |
9d202783 | 169 | |
a095b1c7 JC |
170 | timer@20300 { |
171 | compatible = "marvell,armada-xp-timer"; | |
172 | clocks = <&coreclk 2>, <&refclk>; | |
173 | clock-names = "nbclk", "fixed"; | |
174 | }; | |
175 | ||
05afeeb9 EG |
176 | watchdog@20300 { |
177 | compatible = "marvell,armada-xp-wdt"; | |
178 | clocks = <&coreclk 2>, <&refclk>; | |
179 | clock-names = "nbclk", "fixed"; | |
180 | }; | |
181 | ||
b6249d4b GC |
182 | cpurst@20800 { |
183 | compatible = "marvell,armada-370-cpu-reset"; | |
184 | reg = <0x20800 0x20>; | |
467f54b2 | 185 | }; |
323c1010 | 186 | |
97dd823e TP |
187 | cpu-config@21000 { |
188 | compatible = "marvell,armada-xp-cpu-config"; | |
189 | reg = <0x21000 0x8>; | |
190 | }; | |
191 | ||
be5a9389 | 192 | eth2: ethernet@30000 { |
ea3b55fe | 193 | compatible = "marvell,armada-xp-neta"; |
cf8088c5 | 194 | reg = <0x30000 0x4000>; |
323c1010 | 195 | interrupts = <12>; |
4aa935a2 | 196 | clocks = <&gateclk 2>; |
323c1010 | 197 | status = "disabled"; |
a1d53dab | 198 | }; |
a1d53dab | 199 | |
a095b1c7 JC |
200 | usb@50000 { |
201 | clocks = <&gateclk 18>; | |
202 | }; | |
203 | ||
204 | usb@51000 { | |
205 | clocks = <&gateclk 19>; | |
206 | }; | |
207 | ||
208 | usb@52000 { | |
209 | compatible = "marvell,orion-ehci"; | |
210 | reg = <0x52000 0x500>; | |
211 | interrupts = <47>; | |
212 | clocks = <&gateclk 20>; | |
213 | status = "disabled"; | |
214 | }; | |
215 | ||
467f54b2 GC |
216 | xor@60900 { |
217 | compatible = "marvell,orion-xor"; | |
218 | reg = <0x60900 0x100 | |
219 | 0x60b00 0x100>; | |
220 | clocks = <&gateclk 22>; | |
221 | status = "okay"; | |
222 | ||
223 | xor10 { | |
224 | interrupts = <51>; | |
225 | dmacap,memcpy; | |
226 | dmacap,xor; | |
227 | }; | |
228 | xor11 { | |
229 | interrupts = <52>; | |
230 | dmacap,memcpy; | |
231 | dmacap,xor; | |
232 | dmacap,memset; | |
233 | }; | |
a1d53dab | 234 | }; |
467f54b2 | 235 | |
ea3b55fe SG |
236 | ethernet@70000 { |
237 | compatible = "marvell,armada-xp-neta"; | |
238 | }; | |
239 | ||
240 | ethernet@74000 { | |
241 | compatible = "marvell,armada-xp-neta"; | |
242 | }; | |
243 | ||
b2ee6b7b BB |
244 | crypto@90000 { |
245 | compatible = "marvell,armada-xp-crypto"; | |
246 | reg = <0x90000 0x10000>; | |
247 | reg-names = "regs"; | |
248 | interrupts = <48>, <49>; | |
249 | clocks = <&gateclk 23>, <&gateclk 23>; | |
250 | clock-names = "cesa0", "cesa1"; | |
251 | marvell,crypto-srams = <&crypto_sram0>, | |
252 | <&crypto_sram1>; | |
253 | marvell,crypto-sram-size = <0x800>; | |
254 | }; | |
255 | ||
ebae1376 MW |
256 | bm: bm@c0000 { |
257 | compatible = "marvell,armada-380-neta-bm"; | |
258 | reg = <0xc0000 0xac>; | |
259 | clocks = <&gateclk 13>; | |
260 | internal-mem = <&bm_bppi>; | |
261 | status = "disabled"; | |
262 | }; | |
263 | ||
467f54b2 GC |
264 | xor@f0900 { |
265 | compatible = "marvell,orion-xor"; | |
266 | reg = <0xF0900 0x100 | |
267 | 0xF0B00 0x100>; | |
268 | clocks = <&gateclk 28>; | |
269 | status = "okay"; | |
270 | ||
271 | xor00 { | |
272 | interrupts = <94>; | |
273 | dmacap,memcpy; | |
274 | dmacap,xor; | |
275 | }; | |
276 | xor01 { | |
277 | interrupts = <95>; | |
278 | dmacap,memcpy; | |
279 | dmacap,xor; | |
280 | dmacap,memset; | |
281 | }; | |
a1d53dab | 282 | }; |
693a56ea | 283 | }; |
b2ee6b7b BB |
284 | |
285 | crypto_sram0: sa-sram0 { | |
286 | compatible = "mmio-sram"; | |
287 | reg = <MBUS_ID(0x09, 0x09) 0 0x800>; | |
288 | clocks = <&gateclk 23>; | |
289 | #address-cells = <1>; | |
290 | #size-cells = <1>; | |
291 | ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; | |
292 | }; | |
293 | ||
294 | crypto_sram1: sa-sram1 { | |
295 | compatible = "mmio-sram"; | |
296 | reg = <MBUS_ID(0x09, 0x05) 0 0x800>; | |
297 | clocks = <&gateclk 23>; | |
298 | #address-cells = <1>; | |
299 | #size-cells = <1>; | |
300 | ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; | |
301 | }; | |
ebae1376 MW |
302 | |
303 | bm_bppi: bm-bppi { | |
304 | compatible = "mmio-sram"; | |
305 | reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; | |
306 | ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; | |
307 | #address-cells = <1>; | |
308 | #size-cells = <1>; | |
309 | clocks = <&gateclk 13>; | |
310 | no-memory-wc; | |
311 | status = "disabled"; | |
312 | }; | |
9ae6f740 | 313 | }; |
c1bbd430 EG |
314 | |
315 | clocks { | |
316 | /* 25 MHz reference crystal */ | |
317 | refclk: oscillator { | |
318 | compatible = "fixed-clock"; | |
319 | #clock-cells = <0>; | |
320 | clock-frequency = <25000000>; | |
321 | }; | |
322 | }; | |
9ae6f740 | 323 | }; |
4904a82a AE |
324 | |
325 | &pinctrl { | |
70ee4e9d | 326 | ge0_gmii_pins: ge0-gmii-pins { |
4904a82a AE |
327 | marvell,pins = |
328 | "mpp0", "mpp1", "mpp2", "mpp3", | |
329 | "mpp4", "mpp5", "mpp6", "mpp7", | |
330 | "mpp8", "mpp9", "mpp10", "mpp11", | |
331 | "mpp12", "mpp13", "mpp14", "mpp15", | |
332 | "mpp16", "mpp17", "mpp18", "mpp19", | |
333 | "mpp20", "mpp21", "mpp22", "mpp23"; | |
334 | marvell,function = "ge0"; | |
335 | }; | |
336 | ||
70ee4e9d | 337 | ge0_rgmii_pins: ge0-rgmii-pins { |
4904a82a AE |
338 | marvell,pins = |
339 | "mpp0", "mpp1", "mpp2", "mpp3", | |
340 | "mpp4", "mpp5", "mpp6", "mpp7", | |
341 | "mpp8", "mpp9", "mpp10", "mpp11"; | |
342 | marvell,function = "ge0"; | |
343 | }; | |
344 | ||
70ee4e9d | 345 | ge1_rgmii_pins: ge1-rgmii-pins { |
4904a82a AE |
346 | marvell,pins = |
347 | "mpp12", "mpp13", "mpp14", "mpp15", | |
348 | "mpp16", "mpp17", "mpp18", "mpp19", | |
349 | "mpp20", "mpp21", "mpp22", "mpp23"; | |
350 | marvell,function = "ge1"; | |
351 | }; | |
352 | ||
353 | sdio_pins: sdio-pins { | |
354 | marvell,pins = "mpp30", "mpp31", "mpp32", | |
355 | "mpp33", "mpp34", "mpp35"; | |
356 | marvell,function = "sd0"; | |
357 | }; | |
d352f41e | 358 | |
547c653b AE |
359 | spi0_pins: spi0-pins { |
360 | marvell,pins = "mpp36", "mpp37", | |
361 | "mpp38", "mpp39"; | |
8c19a731 | 362 | marvell,function = "spi0"; |
547c653b AE |
363 | }; |
364 | ||
d352f41e AE |
365 | uart2_pins: uart2-pins { |
366 | marvell,pins = "mpp42", "mpp43"; | |
367 | marvell,function = "uart2"; | |
368 | }; | |
369 | ||
370 | uart3_pins: uart3-pins { | |
371 | marvell,pins = "mpp44", "mpp45"; | |
372 | marvell,function = "uart3"; | |
373 | }; | |
4904a82a | 374 | }; |