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9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada XP family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | * | |
10b683cb | 15 | * Contains definitions specific to the Armada XP SoC that are not |
9ae6f740 TP |
16 | * common to all Armada SoCs. |
17 | */ | |
18 | ||
38149887 | 19 | #include "armada-370-xp.dtsi" |
9ae6f740 TP |
20 | |
21 | / { | |
22 | model = "Marvell Armada XP family SoC"; | |
23 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; | |
24 | ||
be5a9389 WT |
25 | aliases { |
26 | eth2 = ð2; | |
27 | }; | |
28 | ||
b18ea4dc | 29 | soc { |
5e12a613 EG |
30 | compatible = "marvell,armadaxp-mbus", "simple-bus"; |
31 | ||
0cd3754a EG |
32 | bootrom { |
33 | compatible = "marvell,bootrom"; | |
34 | reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; | |
35 | }; | |
36 | ||
467f54b2 GC |
37 | internal-regs { |
38 | L2: l2-cache { | |
39 | compatible = "marvell,aurora-system-cache"; | |
40 | reg = <0x08000 0x1000>; | |
41 | cache-id-part = <0x100>; | |
42 | wt-override; | |
43 | }; | |
2f96fbb7 | 44 | |
a095b1c7 JC |
45 | i2c0: i2c@11000 { |
46 | compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; | |
47 | reg = <0x11000 0x100>; | |
467f54b2 | 48 | }; |
9ae6f740 | 49 | |
a095b1c7 JC |
50 | i2c1: i2c@11100 { |
51 | compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; | |
52 | reg = <0x11100 0x100>; | |
467f54b2 | 53 | }; |
9ae6f740 | 54 | |
467f54b2 | 55 | serial@12200 { |
b24212fb | 56 | compatible = "snps,dw-apb-uart"; |
82a68267 | 57 | reg = <0x12200 0x100>; |
9ae6f740 TP |
58 | reg-shift = <2>; |
59 | interrupts = <43>; | |
e366154f | 60 | reg-io-width = <1>; |
64939dc5 | 61 | clocks = <&coreclk 0>; |
9ae6f740 | 62 | status = "disabled"; |
467f54b2 GC |
63 | }; |
64 | serial@12300 { | |
b24212fb | 65 | compatible = "snps,dw-apb-uart"; |
82a68267 | 66 | reg = <0x12300 0x100>; |
9ae6f740 TP |
67 | reg-shift = <2>; |
68 | interrupts = <44>; | |
e366154f | 69 | reg-io-width = <1>; |
64939dc5 | 70 | clocks = <&coreclk 0>; |
9ae6f740 | 71 | status = "disabled"; |
467f54b2 | 72 | }; |
9ae6f740 | 73 | |
a095b1c7 JC |
74 | system-controller@18200 { |
75 | compatible = "marvell,armada-370-xp-system-controller"; | |
76 | reg = <0x18200 0x500>; | |
77 | }; | |
78 | ||
79 | gateclk: clock-gating-control@18220 { | |
80 | compatible = "marvell,armada-xp-gating-clock"; | |
81 | reg = <0x18220 0x4>; | |
82 | clocks = <&coreclk 0>; | |
83 | #clock-cells = <1>; | |
467f54b2 | 84 | }; |
9ae6f740 | 85 | |
467f54b2 GC |
86 | coreclk: mvebu-sar@18230 { |
87 | compatible = "marvell,armada-xp-core-clock"; | |
88 | reg = <0x18230 0x08>; | |
89 | #clock-cells = <1>; | |
90 | }; | |
9d202783 | 91 | |
a095b1c7 JC |
92 | thermal@182b0 { |
93 | compatible = "marvell,armadaxp-thermal"; | |
94 | reg = <0x182b0 0x4 | |
95 | 0x184d0 0x4>; | |
96 | status = "okay"; | |
97 | }; | |
98 | ||
467f54b2 GC |
99 | cpuclk: clock-complex@18700 { |
100 | #clock-cells = <1>; | |
101 | compatible = "marvell,armada-xp-cpu-clock"; | |
38436078 | 102 | reg = <0x18700 0xA0>, <0x1c054 0x10>; |
467f54b2 GC |
103 | clocks = <&coreclk 1>; |
104 | }; | |
9d202783 | 105 | |
a095b1c7 JC |
106 | interrupt-controller@20000 { |
107 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
467f54b2 | 108 | }; |
9d202783 | 109 | |
a095b1c7 JC |
110 | timer@20300 { |
111 | compatible = "marvell,armada-xp-timer"; | |
112 | clocks = <&coreclk 2>, <&refclk>; | |
113 | clock-names = "nbclk", "fixed"; | |
114 | }; | |
115 | ||
05afeeb9 EG |
116 | watchdog@20300 { |
117 | compatible = "marvell,armada-xp-wdt"; | |
118 | clocks = <&coreclk 2>, <&refclk>; | |
119 | clock-names = "nbclk", "fixed"; | |
120 | }; | |
121 | ||
b6249d4b GC |
122 | cpurst@20800 { |
123 | compatible = "marvell,armada-370-cpu-reset"; | |
124 | reg = <0x20800 0x20>; | |
467f54b2 | 125 | }; |
323c1010 | 126 | |
be5a9389 | 127 | eth2: ethernet@30000 { |
323c1010 | 128 | compatible = "marvell,armada-370-neta"; |
cf8088c5 | 129 | reg = <0x30000 0x4000>; |
323c1010 | 130 | interrupts = <12>; |
4aa935a2 | 131 | clocks = <&gateclk 2>; |
323c1010 | 132 | status = "disabled"; |
a1d53dab | 133 | }; |
a1d53dab | 134 | |
a095b1c7 JC |
135 | usb@50000 { |
136 | clocks = <&gateclk 18>; | |
137 | }; | |
138 | ||
139 | usb@51000 { | |
140 | clocks = <&gateclk 19>; | |
141 | }; | |
142 | ||
143 | usb@52000 { | |
144 | compatible = "marvell,orion-ehci"; | |
145 | reg = <0x52000 0x500>; | |
146 | interrupts = <47>; | |
147 | clocks = <&gateclk 20>; | |
148 | status = "disabled"; | |
149 | }; | |
150 | ||
467f54b2 GC |
151 | xor@60900 { |
152 | compatible = "marvell,orion-xor"; | |
153 | reg = <0x60900 0x100 | |
154 | 0x60b00 0x100>; | |
155 | clocks = <&gateclk 22>; | |
156 | status = "okay"; | |
157 | ||
158 | xor10 { | |
159 | interrupts = <51>; | |
160 | dmacap,memcpy; | |
161 | dmacap,xor; | |
162 | }; | |
163 | xor11 { | |
164 | interrupts = <52>; | |
165 | dmacap,memcpy; | |
166 | dmacap,xor; | |
167 | dmacap,memset; | |
168 | }; | |
a1d53dab | 169 | }; |
467f54b2 GC |
170 | |
171 | xor@f0900 { | |
172 | compatible = "marvell,orion-xor"; | |
173 | reg = <0xF0900 0x100 | |
174 | 0xF0B00 0x100>; | |
175 | clocks = <&gateclk 28>; | |
176 | status = "okay"; | |
177 | ||
178 | xor00 { | |
179 | interrupts = <94>; | |
180 | dmacap,memcpy; | |
181 | dmacap,xor; | |
182 | }; | |
183 | xor01 { | |
184 | interrupts = <95>; | |
185 | dmacap,memcpy; | |
186 | dmacap,xor; | |
187 | dmacap,memset; | |
188 | }; | |
a1d53dab | 189 | }; |
693a56ea | 190 | }; |
9ae6f740 | 191 | }; |
c1bbd430 EG |
192 | |
193 | clocks { | |
194 | /* 25 MHz reference crystal */ | |
195 | refclk: oscillator { | |
196 | compatible = "fixed-clock"; | |
197 | #clock-cells = <0>; | |
198 | clock-frequency = <25000000>; | |
199 | }; | |
200 | }; | |
9ae6f740 | 201 | }; |