[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / armada-xp.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * Contains definitions specific to the Armada XP SoC that are not
 * common to all Armada SoCs.
 */

#include "armada-370-xp.dtsi"

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	model = "Marvell Armada XP family SoC";
	compatible = "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		serial2 = &uart2;
		serial3 = &uart3;
	};

	soc {
		compatible = "marvell,armadaxp-mbus", "simple-bus";

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		internal-regs {
			sdramc@1400 {
				compatible = "marvell,armada-xp-sdram-controller";
				reg = <0x1400 0x500>;
			};

			L2: l2-cache@8000 {
				compatible = "marvell,aurora-system-cache";
				reg = <0x08000 0x1000>;
				cache-id-part = <0x100>;
				cache-level = <2>;
				cache-unified;
				wt-override;
			};

			uart2: serial@12200 {
				compatible = "snps,dw-apb-uart";
				pinctrl-0 = <&uart2_pins>;
				pinctrl-names = "default";
				reg = <0x12200 0x100>;
				reg-shift = <2>;
				interrupts = <43>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart3: serial@12300 {
				compatible = "snps,dw-apb-uart";
				pinctrl-0 = <&uart3_pins>;
				pinctrl-names = "default";
				reg = <0x12300 0x100>;
				reg-shift = <2>;
				interrupts = <44>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			systemc: system-controller@18200 {
				compatible = "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x500>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-xp-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			coreclk: mvebu-sar@18230 {
				compatible = "marvell,armada-xp-core-clock";
				reg = <0x18230 0x08>;
				#clock-cells = <1>;
			};

			thermal: thermal@182b0 {
				compatible = "marvell,armadaxp-thermal";
				reg = <0x182b0 0x4
					0x184d0 0x4>;
				status = "okay";
			};

			cpuclk: clock-complex@18700 {
				#clock-cells = <1>;
				compatible = "marvell,armada-xp-cpu-clock";
				reg = <0x18700 0x24>, <0x1c054 0x10>;
				clocks = <&coreclk 1>;
			};

			cpu-config@21000 {
				compatible = "marvell,armada-xp-cpu-config";
				reg = <0x21000 0x8>;
			};

			eth2: ethernet@30000 {
				compatible = "marvell,armada-xp-neta";
				reg = <0x30000 0x4000>;
				interrupts = <12>;
				clocks = <&gateclk 2>;
				status = "disabled";
			};

			usb2: usb@52000 {
				compatible = "marvell,orion-ehci";
				reg = <0x52000 0x500>;
				interrupts = <47>;
				clocks = <&gateclk 20>;
				status = "disabled";
			};

			xor1: xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor10 {
					interrupts = <51>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <52>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			ethernet@70000 {
				compatible = "marvell,armada-xp-neta";
			};

			ethernet@74000 {
				compatible = "marvell,armada-xp-neta";
			};

			cesa: crypto@90000 {
				compatible = "marvell,armada-xp-crypto";
				reg = <0x90000 0x10000>;
				reg-names = "regs";
				interrupts = <48>, <49>;
				clocks = <&gateclk 23>, <&gateclk 23>;
				clock-names = "cesa0", "cesa1";
				marvell,crypto-srams = <&crypto_sram0>,
						       <&crypto_sram1>;
				marvell,crypto-sram-size = <0x800>;
			};

			bm: bm@c0000 {
				compatible = "marvell,armada-380-neta-bm";
				reg = <0xc0000 0xac>;
				clocks = <&gateclk 13>;
				internal-mem = <&bm_bppi>;
				status = "disabled";
			};

			xor0: xor@f0900 {
				compatible = "marvell,orion-xor";
				reg = <0xF0900 0x100
				       0xF0B00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor00 {
					interrupts = <94>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <95>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};
		};

		crypto_sram0: sa-sram0 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
			clocks = <&gateclk 23>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
		};

		crypto_sram1: sa-sram1 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
			clocks = <&gateclk 23>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
		};

		bm_bppi: bm-bppi {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
			ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&gateclk 13>;
			no-memory-wc;
			status = "disabled";
		};
	};

	clocks {
		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};

&i2c0 {
	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	reg = <0x11000 0x100>;
};

&i2c1 {
	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	reg = <0x11100 0x100>;
};

&mpic {
	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};

&timer {
	compatible = "marvell,armada-xp-timer";
	clocks = <&coreclk 2>, <&refclk>;
	clock-names = "nbclk", "fixed";
};

&watchdog {
	compatible = "marvell,armada-xp-wdt";
	clocks = <&coreclk 2>, <&refclk>;
	clock-names = "nbclk", "fixed";
};

&cpurst {
	reg = <0x20800 0x20>;
};

&usb0 {
	clocks = <&gateclk 18>;
};

&usb1 {
	clocks = <&gateclk 19>;
};

&pinctrl {
	ge0_gmii_pins: ge0-gmii-pins {
		marvell,pins =
		     "mpp0",  "mpp1",  "mpp2",  "mpp3",
		     "mpp4",  "mpp5",  "mpp6",  "mpp7",
		     "mpp8",  "mpp9",  "mpp10", "mpp11",
		     "mpp12", "mpp13", "mpp14", "mpp15",
		     "mpp16", "mpp17", "mpp18", "mpp19",
		     "mpp20", "mpp21", "mpp22", "mpp23";
		marvell,function = "ge0";
	};

	ge0_rgmii_pins: ge0-rgmii-pins {
		marvell,pins =
		     "mpp0", "mpp1", "mpp2", "mpp3",
		     "mpp4", "mpp5", "mpp6", "mpp7",
		     "mpp8", "mpp9", "mpp10", "mpp11";
		marvell,function = "ge0";
	};

	ge1_rgmii_pins: ge1-rgmii-pins {
		marvell,pins =
		     "mpp12", "mpp13", "mpp14", "mpp15",
		     "mpp16", "mpp17", "mpp18", "mpp19",
		     "mpp20", "mpp21", "mpp22", "mpp23";
		marvell,function = "ge1";
	};

	sdio_pins: sdio-pins {
		marvell,pins = "mpp30", "mpp31", "mpp32",
			       "mpp33", "mpp34", "mpp35";
		marvell,function = "sd0";
	};

	spi0_pins: spi0-pins {
		marvell,pins = "mpp36", "mpp37",
			       "mpp38", "mpp39";
		marvell,function = "spi0";
	};

	spi1_pins: spi1-pins {
		marvell,pins = "mpp13", "mpp14",
			       "mpp16", "mpp17";
		marvell,function = "spi1";
	};

	uart2_pins: uart2-pins {
		marvell,pins = "mpp42", "mpp43";
		marvell,function = "uart2";
	};

	uart3_pins: uart3-pins {
		marvell,pins = "mpp44", "mpp45";
		marvell,function = "uart3";
	};
};

&spi0 {
	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
	pinctrl-0 = <&spi0_pins>;
	pinctrl-names = "default";
};

&spi1 {
	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
	pinctrl-0 = <&spi1_pins>;
	pinctrl-names = "default";
};
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
ee2ff969 GC	11	* This file is dual-licensed: you can use it either under the terms
	12	* of the GPL or the X11 license, at your option. Note that this dual
	13	* licensing only applies to this file, and not this project as a
	14	* whole.
	15	*
	16	* a) This file is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of the
	19	* License, or (at your option) any later version.
	20	*
24f0b6fe	21	* This file is distributed in the hope that it will be useful,
ee2ff969 GC	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
24f0b6fe	26	* Or, alternatively,
ee2ff969 GC	27	*
	28	* b) Permission is hereby granted, free of charge, to any person
	29	* obtaining a copy of this software and associated documentation
	30	* files (the "Software"), to deal in the Software without
24f0b6fe	31	* restriction, including without limitation the rights to use,
ee2ff969 GC	32	* copy, modify, merge, publish, distribute, sublicense, and/or
	33	* sell copies of the Software, and to permit persons to whom the
	34	* Software is furnished to do so, subject to the following
	35	* conditions:
	36	*
	37	* The above copyright notice and this permission notice shall be
	38	* included in all copies or substantial portions of the Software.
	39	*
24f0b6fe	40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
ee2ff969 GC	41	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	42	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	43	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
24f0b6fe	44	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
ee2ff969 GC	45	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	46	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	47	* OTHER DEALINGS IN THE SOFTWARE.
9ae6f740	48	*
10b683cb	49	* Contains definitions specific to the Armada XP SoC that are not
9ae6f740 TP	50	* common to all Armada SoCs.
	51	*/
	52
38149887	53	#include "armada-370-xp.dtsi"
9ae6f740 TP	54
9ae6f740 TP	55	/ {
1cb92a98 GC	56	#address-cells = <2>;
	57	#size-cells = <2>;
	58
9ae6f740 TP	59	model = "Marvell Armada XP family SoC";
	60	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
	61
be5a9389	62	aliases {
bf6acf16 TP	63	serial2 = &uart2;
bf6acf16 TP	64	serial3 = &uart3;
be5a9389 WT	65	};
be5a9389 WT	66
b18ea4dc	67	soc {
5e12a613 EG	68	compatible = "marvell,armadaxp-mbus", "simple-bus";
5e12a613 EG	69
0cd3754a EG	70	bootrom {
	71	compatible = "marvell,bootrom";
	72	reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
	73	};
	74
467f54b2	75	internal-regs {
6e6db2be TP	76	sdramc@1400 {
	77	compatible = "marvell,armada-xp-sdram-controller";
	78	reg = <0x1400 0x500>;
	79	};
	80
3a729d7c	81	L2: l2-cache@8000 {
467f54b2 GC	82	compatible = "marvell,aurora-system-cache";
	83	reg = <0x08000 0x1000>;
	84	cache-id-part = <0x100>;
292a3546	85	cache-level = <2>;
a9ce1afb	86	cache-unified;
467f54b2 GC	87	wt-override;
467f54b2 GC	88	};
2f96fbb7	89
181d9b28	90	uart2: serial@12200 {
b24212fb	91	compatible = "snps,dw-apb-uart";
d352f41e AE	92	pinctrl-0 = <&uart2_pins>;
d352f41e AE	93	pinctrl-names = "default";
82a68267	94	reg = <0x12200 0x100>;
9ae6f740 TP	95	reg-shift = <2>;
9ae6f740 TP	96	interrupts = <43>;
e366154f	97	reg-io-width = <1>;
64939dc5	98	clocks = <&coreclk 0>;
9ae6f740	99	status = "disabled";
467f54b2	100	};
181d9b28 AE	101
181d9b28 AE	102	uart3: serial@12300 {
b24212fb	103	compatible = "snps,dw-apb-uart";
d352f41e AE	104	pinctrl-0 = <&uart3_pins>;
d352f41e AE	105	pinctrl-names = "default";
82a68267	106	reg = <0x12300 0x100>;
9ae6f740 TP	107	reg-shift = <2>;
9ae6f740 TP	108	interrupts = <44>;
e366154f	109	reg-io-width = <1>;
64939dc5	110	clocks = <&coreclk 0>;
9ae6f740	111	status = "disabled";
467f54b2	112	};
9ae6f740	113
11f7135b	114	systemc: system-controller@18200 {
a095b1c7 JC	115	compatible = "marvell,armada-370-xp-system-controller";
	116	reg = <0x18200 0x500>;
	117	};
	118
	119	gateclk: clock-gating-control@18220 {
	120	compatible = "marvell,armada-xp-gating-clock";
	121	reg = <0x18220 0x4>;
	122	clocks = <&coreclk 0>;
	123	#clock-cells = <1>;
467f54b2	124	};
9ae6f740	125
467f54b2 GC	126	coreclk: mvebu-sar@18230 {
	127	compatible = "marvell,armada-xp-core-clock";
	128	reg = <0x18230 0x08>;
	129	#clock-cells = <1>;
	130	};
9d202783	131
11f7135b	132	thermal: thermal@182b0 {
a095b1c7 JC	133	compatible = "marvell,armadaxp-thermal";
	134	reg = <0x182b0 0x4
	135	0x184d0 0x4>;
	136	status = "okay";
	137	};
	138
467f54b2 GC	139	cpuclk: clock-complex@18700 {
	140	#clock-cells = <1>;
	141	compatible = "marvell,armada-xp-cpu-clock";
b7f01842	142	reg = <0x18700 0x24>, <0x1c054 0x10>;
467f54b2 GC	143	clocks = <&coreclk 1>;
467f54b2 GC	144	};
9d202783	145
97dd823e TP	146	cpu-config@21000 {
	147	compatible = "marvell,armada-xp-cpu-config";
	148	reg = <0x21000 0x8>;
	149	};
	150
be5a9389	151	eth2: ethernet@30000 {
ea3b55fe	152	compatible = "marvell,armada-xp-neta";
cf8088c5	153	reg = <0x30000 0x4000>;
323c1010	154	interrupts = <12>;
4aa935a2	155	clocks = <&gateclk 2>;
323c1010	156	status = "disabled";
a1d53dab	157	};
a1d53dab	158
11f7135b	159	usb2: usb@52000 {
a095b1c7 JC	160	compatible = "marvell,orion-ehci";
	161	reg = <0x52000 0x500>;
	162	interrupts = <47>;
	163	clocks = <&gateclk 20>;
	164	status = "disabled";
	165	};
	166
11f7135b	167	xor1: xor@60900 {
467f54b2 GC	168	compatible = "marvell,orion-xor";
	169	reg = <0x60900 0x100
	170	0x60b00 0x100>;
	171	clocks = <&gateclk 22>;
	172	status = "okay";
	173
	174	xor10 {
	175	interrupts = <51>;
	176	dmacap,memcpy;
	177	dmacap,xor;
	178	};
	179	xor11 {
	180	interrupts = <52>;
	181	dmacap,memcpy;
	182	dmacap,xor;
	183	dmacap,memset;
	184	};
a1d53dab	185	};
467f54b2	186
ea3b55fe SG	187	ethernet@70000 {
	188	compatible = "marvell,armada-xp-neta";
	189	};
	190
	191	ethernet@74000 {
	192	compatible = "marvell,armada-xp-neta";
	193	};
	194
11f7135b	195	cesa: crypto@90000 {
b2ee6b7b BB	196	compatible = "marvell,armada-xp-crypto";
	197	reg = <0x90000 0x10000>;
	198	reg-names = "regs";
	199	interrupts = <48>, <49>;
	200	clocks = <&gateclk 23>, <&gateclk 23>;
	201	clock-names = "cesa0", "cesa1";
	202	marvell,crypto-srams = <&crypto_sram0>,
	203	<&crypto_sram1>;
	204	marvell,crypto-sram-size = <0x800>;
	205	};
	206
ebae1376 MW	207	bm: bm@c0000 {
	208	compatible = "marvell,armada-380-neta-bm";
	209	reg = <0xc0000 0xac>;
	210	clocks = <&gateclk 13>;
	211	internal-mem = <&bm_bppi>;
	212	status = "disabled";
	213	};
	214
11f7135b	215	xor0: xor@f0900 {
467f54b2 GC	216	compatible = "marvell,orion-xor";
	217	reg = <0xF0900 0x100
	218	0xF0B00 0x100>;
	219	clocks = <&gateclk 28>;
	220	status = "okay";
	221
	222	xor00 {
	223	interrupts = <94>;
	224	dmacap,memcpy;
	225	dmacap,xor;
	226	};
	227	xor01 {
	228	interrupts = <95>;
	229	dmacap,memcpy;
	230	dmacap,xor;
	231	dmacap,memset;
	232	};
a1d53dab	233	};
693a56ea	234	};
b2ee6b7b BB	235
	236	crypto_sram0: sa-sram0 {
	237	compatible = "mmio-sram";
	238	reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
	239	clocks = <&gateclk 23>;
	240	#address-cells = <1>;
	241	#size-cells = <1>;
	242	ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
	243	};
	244
	245	crypto_sram1: sa-sram1 {
	246	compatible = "mmio-sram";
	247	reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
	248	clocks = <&gateclk 23>;
	249	#address-cells = <1>;
	250	#size-cells = <1>;
	251	ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
	252	};
ebae1376 MW	253
	254	bm_bppi: bm-bppi {
	255	compatible = "mmio-sram";
	256	reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
	257	ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
	258	#address-cells = <1>;
	259	#size-cells = <1>;
	260	clocks = <&gateclk 13>;
	261	no-memory-wc;
	262	status = "disabled";
	263	};
9ae6f740	264	};
c1bbd430 EG	265
	266	clocks {
	267	/* 25 MHz reference crystal */
	268	refclk: oscillator {
	269	compatible = "fixed-clock";
	270	#clock-cells = <0>;
	271	clock-frequency = <25000000>;
	272	};
	273	};
9ae6f740	274	};
4904a82a	275
f60f9139 GC	276	&i2c0 {
	277	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	278	reg = <0x11000 0x100>;
	279	};
	280
	281	&i2c1 {
	282	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	283	reg = <0x11100 0x100>;
	284	};
	285
	286	&mpic {
	287	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	288	};
	289
	290	&timer {
	291	compatible = "marvell,armada-xp-timer";
	292	clocks = <&coreclk 2>, <&refclk>;
	293	clock-names = "nbclk", "fixed";
	294	};
	295
	296	&watchdog {
	297	compatible = "marvell,armada-xp-wdt";
	298	clocks = <&coreclk 2>, <&refclk>;
	299	clock-names = "nbclk", "fixed";
	300	};
	301
	302	&cpurst {
	303	reg = <0x20800 0x20>;
	304	};
	305
	306	&usb0 {
	307	clocks = <&gateclk 18>;
	308	};
	309
	310	&usb1 {
	311	clocks = <&gateclk 19>;
	312	};
	313
4904a82a	314	&pinctrl {
70ee4e9d	315	ge0_gmii_pins: ge0-gmii-pins {
4904a82a AE	316	marvell,pins =
	317	"mpp0", "mpp1", "mpp2", "mpp3",
	318	"mpp4", "mpp5", "mpp6", "mpp7",
	319	"mpp8", "mpp9", "mpp10", "mpp11",
	320	"mpp12", "mpp13", "mpp14", "mpp15",
	321	"mpp16", "mpp17", "mpp18", "mpp19",
	322	"mpp20", "mpp21", "mpp22", "mpp23";
	323	marvell,function = "ge0";
	324	};
	325
70ee4e9d	326	ge0_rgmii_pins: ge0-rgmii-pins {
4904a82a AE	327	marvell,pins =
	328	"mpp0", "mpp1", "mpp2", "mpp3",
	329	"mpp4", "mpp5", "mpp6", "mpp7",
	330	"mpp8", "mpp9", "mpp10", "mpp11";
	331	marvell,function = "ge0";
	332	};
	333
70ee4e9d	334	ge1_rgmii_pins: ge1-rgmii-pins {
4904a82a AE	335	marvell,pins =
	336	"mpp12", "mpp13", "mpp14", "mpp15",
	337	"mpp16", "mpp17", "mpp18", "mpp19",
	338	"mpp20", "mpp21", "mpp22", "mpp23";
	339	marvell,function = "ge1";
	340	};
	341
	342	sdio_pins: sdio-pins {
	343	marvell,pins = "mpp30", "mpp31", "mpp32",
	344	"mpp33", "mpp34", "mpp35";
	345	marvell,function = "sd0";
	346	};
d352f41e	347
547c653b AE	348	spi0_pins: spi0-pins {
	349	marvell,pins = "mpp36", "mpp37",
	350	"mpp38", "mpp39";
8c19a731	351	marvell,function = "spi0";
547c653b AE	352	};
547c653b AE	353
1113603e SR	354	spi1_pins: spi1-pins {
	355	marvell,pins = "mpp13", "mpp14",
	356	"mpp16", "mpp17";
	357	marvell,function = "spi1";
	358	};
	359
d352f41e AE	360	uart2_pins: uart2-pins {
	361	marvell,pins = "mpp42", "mpp43";
	362	marvell,function = "uart2";
	363	};
	364
	365	uart3_pins: uart3-pins {
	366	marvell,pins = "mpp44", "mpp45";
	367	marvell,function = "uart3";
	368	};
4904a82a	369	};
0160a4b6 SR	370
	371	&spi0 {
	372	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
	373	pinctrl-0 = <&spi0_pins>;
	374	pinctrl-names = "default";
	375	};
	376
	377	&spi1 {
	378	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
	379	pinctrl-0 = <&spi1_pins>;
	380	pinctrl-names = "default";
	381	};