[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / armada-xp.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * Contains definitions specific to the Armada XP SoC that are not
 * common to all Armada SoCs.
 */

#include "armada-370-xp.dtsi"

/ {
	model = "Marvell Armada XP family SoC";
	compatible = "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		serial2 = &uart2;
		serial3 = &uart3;
	};

	soc {
		compatible = "marvell,armadaxp-mbus", "simple-bus";

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		internal-regs {
			sdramc@1400 {
				compatible = "marvell,armada-xp-sdram-controller";
				reg = <0x1400 0x500>;
			};

			L2: l2-cache {
				compatible = "marvell,aurora-system-cache";
				reg = <0x08000 0x1000>;
				cache-id-part = <0x100>;
				cache-unified;
				wt-override;
			};

			spi0: spi@10600 {
				pinctrl-0 = <&spi0_pins>;
				pinctrl-names = "default";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
				reg = <0x11000 0x100>;
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
				reg = <0x11100 0x100>;
			};

			uart2: serial@12200 {
				compatible = "snps,dw-apb-uart";
				pinctrl-0 = <&uart2_pins>;
				pinctrl-names = "default";
				reg = <0x12200 0x100>;
				reg-shift = <2>;
				interrupts = <43>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart3: serial@12300 {
				compatible = "snps,dw-apb-uart";
				pinctrl-0 = <&uart3_pins>;
				pinctrl-names = "default";
				reg = <0x12300 0x100>;
				reg-shift = <2>;
				interrupts = <44>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			system-controller@18200 {
				compatible = "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x500>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-xp-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			coreclk: mvebu-sar@18230 {
				compatible = "marvell,armada-xp-core-clock";
				reg = <0x18230 0x08>;
				#clock-cells = <1>;
			};

			thermal@182b0 {
				compatible = "marvell,armadaxp-thermal";
				reg = <0x182b0 0x4
					0x184d0 0x4>;
				status = "okay";
			};

			cpuclk: clock-complex@18700 {
				#clock-cells = <1>;
				compatible = "marvell,armada-xp-cpu-clock";
				reg = <0x18700 0xA0>, <0x1c054 0x10>;
				clocks = <&coreclk 1>;
			};

			interrupt-controller@20a00 {
			      reg = <0x20a00 0x2d0>, <0x21070 0x58>;
			};

			timer@20300 {
				compatible = "marvell,armada-xp-timer";
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			watchdog@20300 {
				compatible = "marvell,armada-xp-wdt";
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x20>;
			};

			eth2: ethernet@30000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x30000 0x4000>;
				interrupts = <12>;
				clocks = <&gateclk 2>;
				status = "disabled";
			};

			usb@50000 {
				clocks = <&gateclk 18>;
			};

			usb@51000 {
				clocks = <&gateclk 19>;
			};

			usb@52000 {
				compatible = "marvell,orion-ehci";
				reg = <0x52000 0x500>;
				interrupts = <47>;
				clocks = <&gateclk 20>;
				status = "disabled";
			};

			xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor10 {
					interrupts = <51>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <52>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor@f0900 {
				compatible = "marvell,orion-xor";
				reg = <0xF0900 0x100
				       0xF0B00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor00 {
					interrupts = <94>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <95>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};
		};
	};

	clocks {
		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};

&pinctrl {
	ge0_gmii_pins: ge0-gmii-pins {
		marvell,pins =
		     "mpp0",  "mpp1",  "mpp2",  "mpp3",
		     "mpp4",  "mpp5",  "mpp6",  "mpp7",
		     "mpp8",  "mpp9",  "mpp10", "mpp11",
		     "mpp12", "mpp13", "mpp14", "mpp15",
		     "mpp16", "mpp17", "mpp18", "mpp19",
		     "mpp20", "mpp21", "mpp22", "mpp23";
		marvell,function = "ge0";
	};

	ge0_rgmii_pins: ge0-rgmii-pins {
		marvell,pins =
		     "mpp0", "mpp1", "mpp2", "mpp3",
		     "mpp4", "mpp5", "mpp6", "mpp7",
		     "mpp8", "mpp9", "mpp10", "mpp11";
		marvell,function = "ge0";
	};

	ge1_rgmii_pins: ge1-rgmii-pins {
		marvell,pins =
		     "mpp12", "mpp13", "mpp14", "mpp15",
		     "mpp16", "mpp17", "mpp18", "mpp19",
		     "mpp20", "mpp21", "mpp22", "mpp23";
		marvell,function = "ge1";
	};

	sdio_pins: sdio-pins {
		marvell,pins = "mpp30", "mpp31", "mpp32",
			       "mpp33", "mpp34", "mpp35";
		marvell,function = "sd0";
	};

	spi0_pins: spi0-pins {
		marvell,pins = "mpp36", "mpp37",
			       "mpp38", "mpp39";
		marvell,function = "spi";
	};

	uart2_pins: uart2-pins {
		marvell,pins = "mpp42", "mpp43";
		marvell,function = "uart2";
	};

	uart3_pins: uart3-pins {
		marvell,pins = "mpp44", "mpp45";
		marvell,function = "uart3";
	};
};
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
ee2ff969 GC	11	* This file is dual-licensed: you can use it either under the terms
	12	* of the GPL or the X11 license, at your option. Note that this dual
	13	* licensing only applies to this file, and not this project as a
	14	* whole.
	15	*
	16	* a) This file is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of the
	19	* License, or (at your option) any later version.
	20	*
	21	* This file is distributed in the hope that it will be useful
	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* Or, alternatively
	27	*
	28	* b) Permission is hereby granted, free of charge, to any person
	29	* obtaining a copy of this software and associated documentation
	30	* files (the "Software"), to deal in the Software without
	31	* restriction, including without limitation the rights to use
	32	* copy, modify, merge, publish, distribute, sublicense, and/or
	33	* sell copies of the Software, and to permit persons to whom the
	34	* Software is furnished to do so, subject to the following
	35	* conditions:
	36	*
	37	* The above copyright notice and this permission notice shall be
	38	* included in all copies or substantial portions of the Software.
	39	*
	40	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	41	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	42	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	43	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	44	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	45	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	46	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	47	* OTHER DEALINGS IN THE SOFTWARE.
9ae6f740	48	*
10b683cb	49	* Contains definitions specific to the Armada XP SoC that are not
9ae6f740 TP	50	* common to all Armada SoCs.
	51	*/
	52
38149887	53	#include "armada-370-xp.dtsi"
9ae6f740 TP	54
	55	/ {
	56	model = "Marvell Armada XP family SoC";
	57	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
	58
be5a9389	59	aliases {
bf6acf16 TP	60	serial2 = &uart2;
bf6acf16 TP	61	serial3 = &uart3;
be5a9389 WT	62	};
be5a9389 WT	63
b18ea4dc	64	soc {
5e12a613 EG	65	compatible = "marvell,armadaxp-mbus", "simple-bus";
5e12a613 EG	66
0cd3754a EG	67	bootrom {
	68	compatible = "marvell,bootrom";
	69	reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
	70	};
	71
467f54b2	72	internal-regs {
6e6db2be TP	73	sdramc@1400 {
	74	compatible = "marvell,armada-xp-sdram-controller";
	75	reg = <0x1400 0x500>;
	76	};
	77
467f54b2 GC	78	L2: l2-cache {
	79	compatible = "marvell,aurora-system-cache";
	80	reg = <0x08000 0x1000>;
	81	cache-id-part = <0x100>;
a9ce1afb	82	cache-unified;
467f54b2 GC	83	wt-override;
467f54b2 GC	84	};
2f96fbb7	85
547c653b AE	86	spi0: spi@10600 {
	87	pinctrl-0 = <&spi0_pins>;
	88	pinctrl-names = "default";
	89	};
	90
a095b1c7 JC	91	i2c0: i2c@11000 {
	92	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	93	reg = <0x11000 0x100>;
467f54b2	94	};
9ae6f740	95
a095b1c7 JC	96	i2c1: i2c@11100 {
	97	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	98	reg = <0x11100 0x100>;
467f54b2	99	};
9ae6f740	100
181d9b28	101	uart2: serial@12200 {
b24212fb	102	compatible = "snps,dw-apb-uart";
d352f41e AE	103	pinctrl-0 = <&uart2_pins>;
d352f41e AE	104	pinctrl-names = "default";
82a68267	105	reg = <0x12200 0x100>;
9ae6f740 TP	106	reg-shift = <2>;
9ae6f740 TP	107	interrupts = <43>;
e366154f	108	reg-io-width = <1>;
64939dc5	109	clocks = <&coreclk 0>;
9ae6f740	110	status = "disabled";
467f54b2	111	};
181d9b28 AE	112
181d9b28 AE	113	uart3: serial@12300 {
b24212fb	114	compatible = "snps,dw-apb-uart";
d352f41e AE	115	pinctrl-0 = <&uart3_pins>;
d352f41e AE	116	pinctrl-names = "default";
82a68267	117	reg = <0x12300 0x100>;
9ae6f740 TP	118	reg-shift = <2>;
9ae6f740 TP	119	interrupts = <44>;
e366154f	120	reg-io-width = <1>;
64939dc5	121	clocks = <&coreclk 0>;
9ae6f740	122	status = "disabled";
467f54b2	123	};
9ae6f740	124
a095b1c7 JC	125	system-controller@18200 {
	126	compatible = "marvell,armada-370-xp-system-controller";
	127	reg = <0x18200 0x500>;
	128	};
	129
	130	gateclk: clock-gating-control@18220 {
	131	compatible = "marvell,armada-xp-gating-clock";
	132	reg = <0x18220 0x4>;
	133	clocks = <&coreclk 0>;
	134	#clock-cells = <1>;
467f54b2	135	};
9ae6f740	136
467f54b2 GC	137	coreclk: mvebu-sar@18230 {
	138	compatible = "marvell,armada-xp-core-clock";
	139	reg = <0x18230 0x08>;
	140	#clock-cells = <1>;
	141	};
9d202783	142
a095b1c7 JC	143	thermal@182b0 {
	144	compatible = "marvell,armadaxp-thermal";
	145	reg = <0x182b0 0x4
	146	0x184d0 0x4>;
	147	status = "okay";
	148	};
	149
467f54b2 GC	150	cpuclk: clock-complex@18700 {
	151	#clock-cells = <1>;
	152	compatible = "marvell,armada-xp-cpu-clock";
38436078	153	reg = <0x18700 0xA0>, <0x1c054 0x10>;
467f54b2 GC	154	clocks = <&coreclk 1>;
467f54b2 GC	155	};
9d202783	156
24c2573b	157	interrupt-controller@20a00 {
a095b1c7	158	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
467f54b2	159	};
9d202783	160
a095b1c7 JC	161	timer@20300 {
	162	compatible = "marvell,armada-xp-timer";
	163	clocks = <&coreclk 2>, <&refclk>;
	164	clock-names = "nbclk", "fixed";
	165	};
	166
05afeeb9 EG	167	watchdog@20300 {
	168	compatible = "marvell,armada-xp-wdt";
	169	clocks = <&coreclk 2>, <&refclk>;
	170	clock-names = "nbclk", "fixed";
	171	};
	172
b6249d4b GC	173	cpurst@20800 {
	174	compatible = "marvell,armada-370-cpu-reset";
	175	reg = <0x20800 0x20>;
467f54b2	176	};
323c1010	177
be5a9389	178	eth2: ethernet@30000 {
323c1010	179	compatible = "marvell,armada-370-neta";
cf8088c5	180	reg = <0x30000 0x4000>;
323c1010	181	interrupts = <12>;
4aa935a2	182	clocks = <&gateclk 2>;
323c1010	183	status = "disabled";
a1d53dab	184	};
a1d53dab	185
a095b1c7 JC	186	usb@50000 {
	187	clocks = <&gateclk 18>;
	188	};
	189
	190	usb@51000 {
	191	clocks = <&gateclk 19>;
	192	};
	193
	194	usb@52000 {
	195	compatible = "marvell,orion-ehci";
	196	reg = <0x52000 0x500>;
	197	interrupts = <47>;
	198	clocks = <&gateclk 20>;
	199	status = "disabled";
	200	};
	201
467f54b2 GC	202	xor@60900 {
	203	compatible = "marvell,orion-xor";
	204	reg = <0x60900 0x100
	205	0x60b00 0x100>;
	206	clocks = <&gateclk 22>;
	207	status = "okay";
	208
	209	xor10 {
	210	interrupts = <51>;
	211	dmacap,memcpy;
	212	dmacap,xor;
	213	};
	214	xor11 {
	215	interrupts = <52>;
	216	dmacap,memcpy;
	217	dmacap,xor;
	218	dmacap,memset;
	219	};
a1d53dab	220	};
467f54b2 GC	221
	222	xor@f0900 {
	223	compatible = "marvell,orion-xor";
	224	reg = <0xF0900 0x100
	225	0xF0B00 0x100>;
	226	clocks = <&gateclk 28>;
	227	status = "okay";
	228
	229	xor00 {
	230	interrupts = <94>;
	231	dmacap,memcpy;
	232	dmacap,xor;
	233	};
	234	xor01 {
	235	interrupts = <95>;
	236	dmacap,memcpy;
	237	dmacap,xor;
	238	dmacap,memset;
	239	};
a1d53dab	240	};
693a56ea	241	};
9ae6f740	242	};
c1bbd430 EG	243
	244	clocks {
	245	/* 25 MHz reference crystal */
	246	refclk: oscillator {
	247	compatible = "fixed-clock";
	248	#clock-cells = <0>;
	249	clock-frequency = <25000000>;
	250	};
	251	};
9ae6f740	252	};
4904a82a AE	253
4904a82a AE	254	&pinctrl {
70ee4e9d	255	ge0_gmii_pins: ge0-gmii-pins {
4904a82a AE	256	marvell,pins =
	257	"mpp0", "mpp1", "mpp2", "mpp3",
	258	"mpp4", "mpp5", "mpp6", "mpp7",
	259	"mpp8", "mpp9", "mpp10", "mpp11",
	260	"mpp12", "mpp13", "mpp14", "mpp15",
	261	"mpp16", "mpp17", "mpp18", "mpp19",
	262	"mpp20", "mpp21", "mpp22", "mpp23";
	263	marvell,function = "ge0";
	264	};
	265
70ee4e9d	266	ge0_rgmii_pins: ge0-rgmii-pins {
4904a82a AE	267	marvell,pins =
	268	"mpp0", "mpp1", "mpp2", "mpp3",
	269	"mpp4", "mpp5", "mpp6", "mpp7",
	270	"mpp8", "mpp9", "mpp10", "mpp11";
	271	marvell,function = "ge0";
	272	};
	273
70ee4e9d	274	ge1_rgmii_pins: ge1-rgmii-pins {
4904a82a AE	275	marvell,pins =
	276	"mpp12", "mpp13", "mpp14", "mpp15",
	277	"mpp16", "mpp17", "mpp18", "mpp19",
	278	"mpp20", "mpp21", "mpp22", "mpp23";
	279	marvell,function = "ge1";
	280	};
	281
	282	sdio_pins: sdio-pins {
	283	marvell,pins = "mpp30", "mpp31", "mpp32",
	284	"mpp33", "mpp34", "mpp35";
	285	marvell,function = "sd0";
	286	};
d352f41e	287
547c653b AE	288	spi0_pins: spi0-pins {
	289	marvell,pins = "mpp36", "mpp37",
	290	"mpp38", "mpp39";
	291	marvell,function = "spi";
	292	};
	293
d352f41e AE	294	uart2_pins: uart2-pins {
	295	marvell,pins = "mpp42", "mpp43";
	296	marvell,function = "uart2";
	297	};
	298
	299	uart3_pins: uart3-pins {
	300	marvell,pins = "mpp44", "mpp45";
	301	marvell,function = "uart3";
	302	};
4904a82a	303	};