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9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada XP family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | * | |
10b683cb | 15 | * Contains definitions specific to the Armada XP SoC that are not |
9ae6f740 TP |
16 | * common to all Armada SoCs. |
17 | */ | |
18 | ||
38149887 | 19 | #include "armada-370-xp.dtsi" |
9ae6f740 TP |
20 | |
21 | / { | |
22 | model = "Marvell Armada XP family SoC"; | |
23 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; | |
24 | ||
be5a9389 WT |
25 | aliases { |
26 | eth2 = ð2; | |
27 | }; | |
28 | ||
b18ea4dc | 29 | soc { |
5e12a613 EG |
30 | compatible = "marvell,armadaxp-mbus", "simple-bus"; |
31 | ||
0cd3754a EG |
32 | bootrom { |
33 | compatible = "marvell,bootrom"; | |
34 | reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; | |
35 | }; | |
36 | ||
467f54b2 GC |
37 | internal-regs { |
38 | L2: l2-cache { | |
39 | compatible = "marvell,aurora-system-cache"; | |
40 | reg = <0x08000 0x1000>; | |
41 | cache-id-part = <0x100>; | |
a9ce1afb | 42 | cache-unified; |
467f54b2 GC |
43 | wt-override; |
44 | }; | |
2f96fbb7 | 45 | |
a095b1c7 JC |
46 | i2c0: i2c@11000 { |
47 | compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; | |
48 | reg = <0x11000 0x100>; | |
467f54b2 | 49 | }; |
9ae6f740 | 50 | |
a095b1c7 JC |
51 | i2c1: i2c@11100 { |
52 | compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; | |
53 | reg = <0x11100 0x100>; | |
467f54b2 | 54 | }; |
9ae6f740 | 55 | |
181d9b28 | 56 | uart2: serial@12200 { |
b24212fb | 57 | compatible = "snps,dw-apb-uart"; |
82a68267 | 58 | reg = <0x12200 0x100>; |
9ae6f740 TP |
59 | reg-shift = <2>; |
60 | interrupts = <43>; | |
e366154f | 61 | reg-io-width = <1>; |
64939dc5 | 62 | clocks = <&coreclk 0>; |
9ae6f740 | 63 | status = "disabled"; |
467f54b2 | 64 | }; |
181d9b28 AE |
65 | |
66 | uart3: serial@12300 { | |
b24212fb | 67 | compatible = "snps,dw-apb-uart"; |
82a68267 | 68 | reg = <0x12300 0x100>; |
9ae6f740 TP |
69 | reg-shift = <2>; |
70 | interrupts = <44>; | |
e366154f | 71 | reg-io-width = <1>; |
64939dc5 | 72 | clocks = <&coreclk 0>; |
9ae6f740 | 73 | status = "disabled"; |
467f54b2 | 74 | }; |
9ae6f740 | 75 | |
264a05e1 | 76 | pinctrl: pin-ctrl@18000 { |
b324fa60 SH |
77 | reg = <0x18000 0x38>; |
78 | ||
7254f6c5 SH |
79 | pmx_ge0_gmii: pmx-ge0-gmii { |
80 | marvell,pins = | |
81 | "mpp0", "mpp1", "mpp2", "mpp3", | |
82 | "mpp4", "mpp5", "mpp6", "mpp7", | |
83 | "mpp8", "mpp9", "mpp10", "mpp11", | |
84 | "mpp12", "mpp13", "mpp14", "mpp15", | |
85 | "mpp16", "mpp17", "mpp18", "mpp19", | |
86 | "mpp20", "mpp21", "mpp22", "mpp23"; | |
87 | marvell,function = "ge0"; | |
88 | }; | |
89 | ||
e5945143 SH |
90 | pmx_ge0_rgmii: pmx-ge0-rgmii { |
91 | marvell,pins = | |
92 | "mpp0", "mpp1", "mpp2", "mpp3", | |
93 | "mpp4", "mpp5", "mpp6", "mpp7", | |
94 | "mpp8", "mpp9", "mpp10", "mpp11"; | |
95 | marvell,function = "ge0"; | |
96 | }; | |
97 | ||
98 | pmx_ge1_rgmii: pmx-ge1-rgmii { | |
99 | marvell,pins = | |
100 | "mpp12", "mpp13", "mpp14", "mpp15", | |
101 | "mpp16", "mpp17", "mpp18", "mpp19", | |
102 | "mpp20", "mpp21", "mpp22", "mpp23"; | |
103 | marvell,function = "ge1"; | |
104 | }; | |
105 | ||
b324fa60 SH |
106 | sdio_pins: sdio-pins { |
107 | marvell,pins = "mpp30", "mpp31", "mpp32", | |
108 | "mpp33", "mpp34", "mpp35"; | |
109 | marvell,function = "sd0"; | |
110 | }; | |
111 | }; | |
112 | ||
a095b1c7 JC |
113 | system-controller@18200 { |
114 | compatible = "marvell,armada-370-xp-system-controller"; | |
115 | reg = <0x18200 0x500>; | |
116 | }; | |
117 | ||
118 | gateclk: clock-gating-control@18220 { | |
119 | compatible = "marvell,armada-xp-gating-clock"; | |
120 | reg = <0x18220 0x4>; | |
121 | clocks = <&coreclk 0>; | |
122 | #clock-cells = <1>; | |
467f54b2 | 123 | }; |
9ae6f740 | 124 | |
467f54b2 GC |
125 | coreclk: mvebu-sar@18230 { |
126 | compatible = "marvell,armada-xp-core-clock"; | |
127 | reg = <0x18230 0x08>; | |
128 | #clock-cells = <1>; | |
129 | }; | |
9d202783 | 130 | |
a095b1c7 JC |
131 | thermal@182b0 { |
132 | compatible = "marvell,armadaxp-thermal"; | |
133 | reg = <0x182b0 0x4 | |
134 | 0x184d0 0x4>; | |
135 | status = "okay"; | |
136 | }; | |
137 | ||
467f54b2 GC |
138 | cpuclk: clock-complex@18700 { |
139 | #clock-cells = <1>; | |
140 | compatible = "marvell,armada-xp-cpu-clock"; | |
38436078 | 141 | reg = <0x18700 0xA0>, <0x1c054 0x10>; |
467f54b2 GC |
142 | clocks = <&coreclk 1>; |
143 | }; | |
9d202783 | 144 | |
a095b1c7 JC |
145 | interrupt-controller@20000 { |
146 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
467f54b2 | 147 | }; |
9d202783 | 148 | |
a095b1c7 JC |
149 | timer@20300 { |
150 | compatible = "marvell,armada-xp-timer"; | |
151 | clocks = <&coreclk 2>, <&refclk>; | |
152 | clock-names = "nbclk", "fixed"; | |
153 | }; | |
154 | ||
05afeeb9 EG |
155 | watchdog@20300 { |
156 | compatible = "marvell,armada-xp-wdt"; | |
157 | clocks = <&coreclk 2>, <&refclk>; | |
158 | clock-names = "nbclk", "fixed"; | |
159 | }; | |
160 | ||
b6249d4b GC |
161 | cpurst@20800 { |
162 | compatible = "marvell,armada-370-cpu-reset"; | |
163 | reg = <0x20800 0x20>; | |
467f54b2 | 164 | }; |
323c1010 | 165 | |
be5a9389 | 166 | eth2: ethernet@30000 { |
323c1010 | 167 | compatible = "marvell,armada-370-neta"; |
cf8088c5 | 168 | reg = <0x30000 0x4000>; |
323c1010 | 169 | interrupts = <12>; |
4aa935a2 | 170 | clocks = <&gateclk 2>; |
323c1010 | 171 | status = "disabled"; |
a1d53dab | 172 | }; |
a1d53dab | 173 | |
a095b1c7 JC |
174 | usb@50000 { |
175 | clocks = <&gateclk 18>; | |
176 | }; | |
177 | ||
178 | usb@51000 { | |
179 | clocks = <&gateclk 19>; | |
180 | }; | |
181 | ||
182 | usb@52000 { | |
183 | compatible = "marvell,orion-ehci"; | |
184 | reg = <0x52000 0x500>; | |
185 | interrupts = <47>; | |
186 | clocks = <&gateclk 20>; | |
187 | status = "disabled"; | |
188 | }; | |
189 | ||
467f54b2 GC |
190 | xor@60900 { |
191 | compatible = "marvell,orion-xor"; | |
192 | reg = <0x60900 0x100 | |
193 | 0x60b00 0x100>; | |
194 | clocks = <&gateclk 22>; | |
195 | status = "okay"; | |
196 | ||
197 | xor10 { | |
198 | interrupts = <51>; | |
199 | dmacap,memcpy; | |
200 | dmacap,xor; | |
201 | }; | |
202 | xor11 { | |
203 | interrupts = <52>; | |
204 | dmacap,memcpy; | |
205 | dmacap,xor; | |
206 | dmacap,memset; | |
207 | }; | |
a1d53dab | 208 | }; |
467f54b2 GC |
209 | |
210 | xor@f0900 { | |
211 | compatible = "marvell,orion-xor"; | |
212 | reg = <0xF0900 0x100 | |
213 | 0xF0B00 0x100>; | |
214 | clocks = <&gateclk 28>; | |
215 | status = "okay"; | |
216 | ||
217 | xor00 { | |
218 | interrupts = <94>; | |
219 | dmacap,memcpy; | |
220 | dmacap,xor; | |
221 | }; | |
222 | xor01 { | |
223 | interrupts = <95>; | |
224 | dmacap,memcpy; | |
225 | dmacap,xor; | |
226 | dmacap,memset; | |
227 | }; | |
a1d53dab | 228 | }; |
693a56ea | 229 | }; |
9ae6f740 | 230 | }; |
c1bbd430 EG |
231 | |
232 | clocks { | |
233 | /* 25 MHz reference crystal */ | |
234 | refclk: oscillator { | |
235 | compatible = "fixed-clock"; | |
236 | #clock-cells = <0>; | |
237 | clock-frequency = <25000000>; | |
238 | }; | |
239 | }; | |
9ae6f740 | 240 | }; |