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9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada XP family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | * | |
10b683cb | 15 | * Contains definitions specific to the Armada XP SoC that are not |
9ae6f740 TP |
16 | * common to all Armada SoCs. |
17 | */ | |
18 | ||
38149887 | 19 | #include "armada-370-xp.dtsi" |
9ae6f740 TP |
20 | |
21 | / { | |
22 | model = "Marvell Armada XP family SoC"; | |
23 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; | |
24 | ||
be5a9389 WT |
25 | aliases { |
26 | eth2 = ð2; | |
27 | }; | |
28 | ||
b18ea4dc | 29 | soc { |
5e12a613 EG |
30 | compatible = "marvell,armadaxp-mbus", "simple-bus"; |
31 | ||
0cd3754a EG |
32 | bootrom { |
33 | compatible = "marvell,bootrom"; | |
34 | reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; | |
35 | }; | |
36 | ||
467f54b2 GC |
37 | internal-regs { |
38 | L2: l2-cache { | |
39 | compatible = "marvell,aurora-system-cache"; | |
40 | reg = <0x08000 0x1000>; | |
41 | cache-id-part = <0x100>; | |
a9ce1afb | 42 | cache-unified; |
467f54b2 GC |
43 | wt-override; |
44 | }; | |
2f96fbb7 | 45 | |
a095b1c7 JC |
46 | i2c0: i2c@11000 { |
47 | compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; | |
48 | reg = <0x11000 0x100>; | |
467f54b2 | 49 | }; |
9ae6f740 | 50 | |
a095b1c7 JC |
51 | i2c1: i2c@11100 { |
52 | compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; | |
53 | reg = <0x11100 0x100>; | |
467f54b2 | 54 | }; |
9ae6f740 | 55 | |
181d9b28 | 56 | uart2: serial@12200 { |
b24212fb | 57 | compatible = "snps,dw-apb-uart"; |
82a68267 | 58 | reg = <0x12200 0x100>; |
9ae6f740 TP |
59 | reg-shift = <2>; |
60 | interrupts = <43>; | |
e366154f | 61 | reg-io-width = <1>; |
64939dc5 | 62 | clocks = <&coreclk 0>; |
9ae6f740 | 63 | status = "disabled"; |
467f54b2 | 64 | }; |
181d9b28 AE |
65 | |
66 | uart3: serial@12300 { | |
b24212fb | 67 | compatible = "snps,dw-apb-uart"; |
82a68267 | 68 | reg = <0x12300 0x100>; |
9ae6f740 TP |
69 | reg-shift = <2>; |
70 | interrupts = <44>; | |
e366154f | 71 | reg-io-width = <1>; |
64939dc5 | 72 | clocks = <&coreclk 0>; |
9ae6f740 | 73 | status = "disabled"; |
467f54b2 | 74 | }; |
9ae6f740 | 75 | |
a095b1c7 JC |
76 | system-controller@18200 { |
77 | compatible = "marvell,armada-370-xp-system-controller"; | |
78 | reg = <0x18200 0x500>; | |
79 | }; | |
80 | ||
81 | gateclk: clock-gating-control@18220 { | |
82 | compatible = "marvell,armada-xp-gating-clock"; | |
83 | reg = <0x18220 0x4>; | |
84 | clocks = <&coreclk 0>; | |
85 | #clock-cells = <1>; | |
467f54b2 | 86 | }; |
9ae6f740 | 87 | |
467f54b2 GC |
88 | coreclk: mvebu-sar@18230 { |
89 | compatible = "marvell,armada-xp-core-clock"; | |
90 | reg = <0x18230 0x08>; | |
91 | #clock-cells = <1>; | |
92 | }; | |
9d202783 | 93 | |
a095b1c7 JC |
94 | thermal@182b0 { |
95 | compatible = "marvell,armadaxp-thermal"; | |
96 | reg = <0x182b0 0x4 | |
97 | 0x184d0 0x4>; | |
98 | status = "okay"; | |
99 | }; | |
100 | ||
467f54b2 GC |
101 | cpuclk: clock-complex@18700 { |
102 | #clock-cells = <1>; | |
103 | compatible = "marvell,armada-xp-cpu-clock"; | |
38436078 | 104 | reg = <0x18700 0xA0>, <0x1c054 0x10>; |
467f54b2 GC |
105 | clocks = <&coreclk 1>; |
106 | }; | |
9d202783 | 107 | |
a095b1c7 JC |
108 | interrupt-controller@20000 { |
109 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
467f54b2 | 110 | }; |
9d202783 | 111 | |
a095b1c7 JC |
112 | timer@20300 { |
113 | compatible = "marvell,armada-xp-timer"; | |
114 | clocks = <&coreclk 2>, <&refclk>; | |
115 | clock-names = "nbclk", "fixed"; | |
116 | }; | |
117 | ||
05afeeb9 EG |
118 | watchdog@20300 { |
119 | compatible = "marvell,armada-xp-wdt"; | |
120 | clocks = <&coreclk 2>, <&refclk>; | |
121 | clock-names = "nbclk", "fixed"; | |
122 | }; | |
123 | ||
b6249d4b GC |
124 | cpurst@20800 { |
125 | compatible = "marvell,armada-370-cpu-reset"; | |
126 | reg = <0x20800 0x20>; | |
467f54b2 | 127 | }; |
323c1010 | 128 | |
be5a9389 | 129 | eth2: ethernet@30000 { |
323c1010 | 130 | compatible = "marvell,armada-370-neta"; |
cf8088c5 | 131 | reg = <0x30000 0x4000>; |
323c1010 | 132 | interrupts = <12>; |
4aa935a2 | 133 | clocks = <&gateclk 2>; |
323c1010 | 134 | status = "disabled"; |
a1d53dab | 135 | }; |
a1d53dab | 136 | |
a095b1c7 JC |
137 | usb@50000 { |
138 | clocks = <&gateclk 18>; | |
139 | }; | |
140 | ||
141 | usb@51000 { | |
142 | clocks = <&gateclk 19>; | |
143 | }; | |
144 | ||
145 | usb@52000 { | |
146 | compatible = "marvell,orion-ehci"; | |
147 | reg = <0x52000 0x500>; | |
148 | interrupts = <47>; | |
149 | clocks = <&gateclk 20>; | |
150 | status = "disabled"; | |
151 | }; | |
152 | ||
467f54b2 GC |
153 | xor@60900 { |
154 | compatible = "marvell,orion-xor"; | |
155 | reg = <0x60900 0x100 | |
156 | 0x60b00 0x100>; | |
157 | clocks = <&gateclk 22>; | |
158 | status = "okay"; | |
159 | ||
160 | xor10 { | |
161 | interrupts = <51>; | |
162 | dmacap,memcpy; | |
163 | dmacap,xor; | |
164 | }; | |
165 | xor11 { | |
166 | interrupts = <52>; | |
167 | dmacap,memcpy; | |
168 | dmacap,xor; | |
169 | dmacap,memset; | |
170 | }; | |
a1d53dab | 171 | }; |
467f54b2 GC |
172 | |
173 | xor@f0900 { | |
174 | compatible = "marvell,orion-xor"; | |
175 | reg = <0xF0900 0x100 | |
176 | 0xF0B00 0x100>; | |
177 | clocks = <&gateclk 28>; | |
178 | status = "okay"; | |
179 | ||
180 | xor00 { | |
181 | interrupts = <94>; | |
182 | dmacap,memcpy; | |
183 | dmacap,xor; | |
184 | }; | |
185 | xor01 { | |
186 | interrupts = <95>; | |
187 | dmacap,memcpy; | |
188 | dmacap,xor; | |
189 | dmacap,memset; | |
190 | }; | |
a1d53dab | 191 | }; |
693a56ea | 192 | }; |
9ae6f740 | 193 | }; |
c1bbd430 EG |
194 | |
195 | clocks { | |
196 | /* 25 MHz reference crystal */ | |
197 | refclk: oscillator { | |
198 | compatible = "fixed-clock"; | |
199 | #clock-cells = <0>; | |
200 | clock-frequency = <25000000>; | |
201 | }; | |
202 | }; | |
9ae6f740 | 203 | }; |
4904a82a AE |
204 | |
205 | &pinctrl { | |
206 | pmx_ge0_gmii: pmx-ge0-gmii { | |
207 | marvell,pins = | |
208 | "mpp0", "mpp1", "mpp2", "mpp3", | |
209 | "mpp4", "mpp5", "mpp6", "mpp7", | |
210 | "mpp8", "mpp9", "mpp10", "mpp11", | |
211 | "mpp12", "mpp13", "mpp14", "mpp15", | |
212 | "mpp16", "mpp17", "mpp18", "mpp19", | |
213 | "mpp20", "mpp21", "mpp22", "mpp23"; | |
214 | marvell,function = "ge0"; | |
215 | }; | |
216 | ||
217 | pmx_ge0_rgmii: pmx-ge0-rgmii { | |
218 | marvell,pins = | |
219 | "mpp0", "mpp1", "mpp2", "mpp3", | |
220 | "mpp4", "mpp5", "mpp6", "mpp7", | |
221 | "mpp8", "mpp9", "mpp10", "mpp11"; | |
222 | marvell,function = "ge0"; | |
223 | }; | |
224 | ||
225 | pmx_ge1_rgmii: pmx-ge1-rgmii { | |
226 | marvell,pins = | |
227 | "mpp12", "mpp13", "mpp14", "mpp15", | |
228 | "mpp16", "mpp17", "mpp18", "mpp19", | |
229 | "mpp20", "mpp21", "mpp22", "mpp23"; | |
230 | marvell,function = "ge1"; | |
231 | }; | |
232 | ||
233 | sdio_pins: sdio-pins { | |
234 | marvell,pins = "mpp30", "mpp31", "mpp32", | |
235 | "mpp33", "mpp34", "mpp35"; | |
236 | marvell,function = "sd0"; | |
237 | }; | |
238 | }; |