[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / aspeed-bmc-quanta-q71l.dts

// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "aspeed-g4.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>

/ {
	model = "Quanta Q71L BMC";
	compatible = "quanta,q71l-bmc", "aspeed,ast2400";

	aliases {
		i2c14 = &i2c_pcie2;
		i2c15 = &i2c_pcie3;
		i2c16 = &i2c_pcie6;
		i2c17 = &i2c_pcie7;
		i2c18 = &i2c_pcie1;
		i2c19 = &i2c_pcie4;
		i2c20 = &i2c_pcie5;
		i2c21 = &i2c_pcie8;
		i2c22 = &i2c_pcie9;
		i2c23 = &i2c_pcie10;
		i2c24 = &i2c_ssd1;
		i2c25 = &i2c_ssd2;
		i2c26 = &i2c_psu4;
		i2c27 = &i2c_psu1;
		i2c28 = &i2c_psu3;
		i2c29 = &i2c_psu2;
	};

	chosen {
		stdout-path = &uart5;
		bootargs = "console=ttyS4,115200 earlyprintk";
	};

	memory@40000000 {
		reg = <0x40000000 0x8000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		vga_memory: framebuffer@47800000 {
			no-map;
			reg = <0x47800000 0x00800000>; /* 8MB */
		};
	};

	leds {
		compatible = "gpio-leds";

		heartbeat {
			gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
		};

		power {
			gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
		};

		identify {
			gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
		};
	};

	iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
			<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
			<&adc 8>, <&adc 9>, <&adc 10>;
	};

	iio-hwmon-battery {
		compatible = "iio-hwmon";
		io-channels = <&adc 11>;
	};

	i2c1mux: i2cmux {
		compatible = "i2c-mux-gpio";
		#address-cells = <1>;
		#size-cells = <0>;

		/* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
		i2c-parent = <&i2c1>;
	};
};

&fmc {
	status = "okay";
	flash@0 {
		status = "okay";
		label = "bmc";
		m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
	};
};

&spi {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1_default>;

	flash@0 {
		status = "okay";
		m25p,fast-read;
		label = "pnor";
	};
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
			&pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
};

&ibt {
	status = "okay";
};

&lpc_ctrl {
	status = "okay";
};

&lpc_snoop {
	status = "okay";
	snoop-ports = <0x80>;
};

&mac0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rmii1_default>;
	use-ncsi;
};

&mac1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};

&uart5 {
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";

	/* temp2 inlet */
	tmp75@4c {
		compatible = "ti,tmp75";
		reg = <0x4c>;
	};

	/* temp3 */
	tmp75@4e {
		compatible = "ti,tmp75";
		reg = <0x4e>;
	};

	/* temp1 */
	tmp75@4f {
		compatible = "ti,tmp75";
		reg = <0x4f>;
	};

	/* Baseboard FRU */
	eeprom@54 {
		compatible = "atmel,24c64";
		reg = <0x54>;
	};

	/* FP FRU */
	eeprom@57 {
		compatible = "atmel,24c64";
		reg = <0x57>;
	};
};

&i2c2 {
	status = "okay";

	/* 0: PCIe Slot 2,
	 *    Slot 3,
	 *    Slot 6,
	 *    Slot 7
	 */
	i2c-switch@74 {
		compatible = "nxp,pca9546";
		reg = <0x74>;
		#address-cells = <1>;
		#size-cells = <0>;
		i2c-mux-idle-disconnect;  /* may use mux@77 next. */

		i2c_pcie2: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		i2c_pcie3: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		i2c_pcie6: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};

		i2c_pcie7: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};
	};

	/* 0: PCIe Slot 1,
	 *    Slot 4,
	 *    Slot 5,
	 *    Slot 8,
	 *    Slot 9,
	 *    Slot 10,
	 *    SSD 1,
	 *    SSD 2
	 */
	i2c-switch@77 {
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x77>;
		i2c-mux-idle-disconnect;  /* may use mux@74 next. */

		i2c_pcie1: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		i2c_pcie4: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		i2c_pcie5: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};

		i2c_pcie8: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};

		i2c_pcie9: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};

		i2c_pcie10: i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
		};

		i2c_ssd1: i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
		};

		i2c_ssd2: i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;
		};
	};
};

&i2c3 {
	status = "okay";

	/* BIOS FRU */
	eeprom@56 {
		compatible = "atmel,24c64";
		reg = <0x56>;
	};
};

&i2c4 {
	status = "okay";
};

&i2c5 {
	status = "okay";
};

&i2c6 {
	status = "okay";
};

&i2c7 {
	status = "okay";

	/* 0: PSU4
	 *    PSU1
	 *    PSU3
	 *    PSU2
	 */
	i2c-switch@70 {
		compatible = "nxp,pca9546";
		reg = <0x70>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c_psu4: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			psu@59 {
				compatible = "pmbus";
				reg = <0x59>;
			};
		};

		i2c_psu1: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			psu@58 {
				compatible = "pmbus";
				reg = <0x58>;
			};
		};

		i2c_psu3: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;

			psu@58 {
				compatible = "pmbus";
				reg = <0x58>;
			};
		};

		i2c_psu2: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			psu@59 {
				compatible = "pmbus";
				reg = <0x59>;
			};
		};
	};

	/* PDB FRU */
	eeprom@52 {
		compatible = "atmel,24c64";
		reg = <0x52>;
	};
};

&i2c8 {
	status = "okay";

	/* BMC FRU */
	eeprom@50 {
		compatible = "atmel,24c64";
		reg = <0x50>;
	};
};

&vuart {
	status = "okay";
};

&wdt2 {
	status = "okay";
};

&adc {
	status = "okay";
};

&pwm_tacho {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0_default
		&pinctrl_pwm1_default
		&pinctrl_pwm2_default
		&pinctrl_pwm3_default>;

	fan@0 {
		reg = <0x00>;
		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
	};

	fan@1 {
		reg = <0x01>;
		aspeed,fan-tach-ch = /bits/ 8 <0x01>;
	};

	fan@2 {
		reg = <0x02>;
		aspeed,fan-tach-ch = /bits/ 8 <0x02>;
	};

	fan@3 {
		reg = <0x03>;
		aspeed,fan-tach-ch = /bits/ 8 <0x03>;
	};

	fan@4 {
		reg = <0x00>;
		aspeed,fan-tach-ch = /bits/ 8 <0x04>;
	};

	fan@5 {
		reg = <0x01>;
		aspeed,fan-tach-ch = /bits/ 8 <0x05>;
	};

	fan@6 {
		reg = <0x02>;
		aspeed,fan-tach-ch = /bits/ 8 <0x06>;
	};

	fan@7 {
		reg = <0x03>;
		aspeed,fan-tach-ch = /bits/ 8 <0x07>;
	};
};

&i2c1mux {
	i2c@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* Memory Riser 1 FRU */
		eeprom@50 {
			compatible = "atmel,24c02";
			reg = <0x50>;
		};

		/* Memory Riser 2 FRU */
		eeprom@51 {
			compatible = "atmel,24c02";
			reg = <0x51>;
		};

		/* Memory Riser 3 FRU */
		eeprom@52 {
			compatible = "atmel,24c02";
			reg = <0x52>;
		};

		/* Memory Riser 4 FRU */
		eeprom@53 {
			compatible = "atmel,24c02";
			reg = <0x53>;
		};
	};

	i2c@1 {
		reg = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* Memory Riser 5 FRU */
		eeprom@50 {
			compatible = "atmel,24c02";
			reg = <0x50>;
		};

		/* Memory Riser 6 FRU */
		eeprom@51 {
			compatible = "atmel,24c02";
			reg = <0x51>;
		};

		/* Memory Riser 7 FRU */
		eeprom@52 {
			compatible = "atmel,24c02";
			reg = <0x52>;
		};

		/* Memory Riser 8 FRU */
		eeprom@53 {
			compatible = "atmel,24c02";
			reg = <0x53>;
		};
	};
};
Commit	Line	Data
f88bc8e1 RA	1	// SPDX-License-Identifier: GPL-2.0
	2	/dts-v1/;
	3	#include "aspeed-g4.dtsi"
	4	#include <dt-bindings/gpio/aspeed-gpio.h>
	5
	6	/ {
	7	model = "Quanta Q71L BMC";
	8	compatible = "quanta,q71l-bmc", "aspeed,ast2400";
	9
e19ecbca PV	10	aliases {
	11	i2c14 = &i2c_pcie2;
	12	i2c15 = &i2c_pcie3;
	13	i2c16 = &i2c_pcie6;
	14	i2c17 = &i2c_pcie7;
	15	i2c18 = &i2c_pcie1;
	16	i2c19 = &i2c_pcie4;
	17	i2c20 = &i2c_pcie5;
	18	i2c21 = &i2c_pcie8;
	19	i2c22 = &i2c_pcie9;
	20	i2c23 = &i2c_pcie10;
	21	i2c24 = &i2c_ssd1;
	22	i2c25 = &i2c_ssd2;
	23	i2c26 = &i2c_psu4;
	24	i2c27 = &i2c_psu1;
	25	i2c28 = &i2c_psu3;
	26	i2c29 = &i2c_psu2;
	27	};
	28
f88bc8e1 RA	29	chosen {
	30	stdout-path = &uart5;
	31	bootargs = "console=ttyS4,115200 earlyprintk";
	32	};
	33
	34	memory@40000000 {
	35	reg = <0x40000000 0x8000000>;
	36	};
	37
	38	reserved-memory {
	39	#address-cells = <1>;
	40	#size-cells = <1>;
	41	ranges;
	42
	43	vga_memory: framebuffer@47800000 {
	44	no-map;
	45	reg = <0x47800000 0x00800000>; /* 8MB */
	46	};
	47	};
	48
	49	leds {
	50	compatible = "gpio-leds";
	51
	52	heartbeat {
	53	gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
	54	};
	55
	56	power {
	57	gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
	58	};
	59
	60	identify {
	61	gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
	62	};
	63	};
	64
	65	iio-hwmon {
	66	compatible = "iio-hwmon";
	67	io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
	68	<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
	69	<&adc 8>, <&adc 9>, <&adc 10>;
	70	};
	71
	72	iio-hwmon-battery {
	73	compatible = "iio-hwmon";
	74	io-channels = <&adc 11>;
	75	};
	76
	77	i2c1mux: i2cmux {
	78	compatible = "i2c-mux-gpio";
	79	#address-cells = <1>;
	80	#size-cells = <0>;
	81
	82	/* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
	83	i2c-parent = <&i2c1>;
	84	};
	85	};
	86
	87	&fmc {
	88	status = "okay";
	89	flash@0 {
	90	status = "okay";
	91	label = "bmc";
	92	m25p,fast-read;
93	#include "openbmc-flash-layout.dtsi"
94	};
95	};
96
97	&spi {
98	status = "okay";
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_spi1_default>;
101
102	flash@0 {
103	status = "okay";
104	m25p,fast-read;
105	label = "pnor";
106	};
107	};
108
109	&pinctrl {
110	pinctrl-names = "default";
111	pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
112	&pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
113	};
114
fde4f21b PV	115	&ibt {
	116	status = "okay";
	117	};
	118
95779307 PV	119	&lpc_ctrl {
	120	status = "okay";
	121	};
	122
f88bc8e1 RA	123	&lpc_snoop {
	124	status = "okay";
	125	snoop-ports = <0x80>;
	126	};
	127
	128	&mac0 {
	129	status = "okay";
	130	pinctrl-names = "default";
	131	pinctrl-0 = <&pinctrl_rmii1_default>;
	132	use-ncsi;
	133	};
	134
	135	&mac1 {
	136	status = "okay";
	137	pinctrl-names = "default";
	138	pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
	139	};
	140
	141	&uart5 {
	142	status = "okay";
	143	};
	144
	145	&i2c0 {
	146	status = "okay";
	147	};
	148
	149	&i2c1 {
	150	status = "okay";
	151
	152	/* temp2 inlet */
	153	tmp75@4c {
	154	compatible = "ti,tmp75";
	155	reg = <0x4c>;
	156	};
	157
	158	/* temp3 */
	159	tmp75@4e {
	160	compatible = "ti,tmp75";
	161	reg = <0x4e>;
	162	};
	163
	164	/* temp1 */
	165	tmp75@4f {
	166	compatible = "ti,tmp75";
	167	reg = <0x4f>;
	168	};
	169
	170	/* Baseboard FRU */
	171	eeprom@54 {
	172	compatible = "atmel,24c64";
	173	reg = <0x54>;
	174	};
	175
	176	/* FP FRU */
	177	eeprom@57 {
	178	compatible = "atmel,24c64";
	179	reg = <0x57>;
	180	};
	181	};
	182
	183	&i2c2 {
	184	status = "okay";
	185
	186	/* 0: PCIe Slot 2,
187	* Slot 3,
188	* Slot 6,
189	* Slot 7
190	*/
191	i2c-switch@74 {
192	compatible = "nxp,pca9546";
193	reg = <0x74>;
194	#address-cells = <1>;
195	#size-cells = <0>;
196	i2c-mux-idle-disconnect; /* may use mux@77 next. */
197
198	i2c_pcie2: i2c@0 {
199	#address-cells = <1>;
200	#size-cells = <0>;
201	reg = <0>;
202	};
203
204	i2c_pcie3: i2c@1 {
205	#address-cells = <1>;
206	#size-cells = <0>;
207	reg = <1>;
208	};
209
210	i2c_pcie6: i2c@2 {
211	#address-cells = <1>;
212	#size-cells = <0>;
213	reg = <2>;
214	};
215
216	i2c_pcie7: i2c@3 {
217	#address-cells = <1>;
218	#size-cells = <0>;
219	reg = <3>;
220	};
221	};
222
223	/* 0: PCIe Slot 1,
224	* Slot 4,
225	* Slot 5,
226	* Slot 8,
227	* Slot 9,
228	* Slot 10,
229	* SSD 1,
230	* SSD 2
231	*/
232	i2c-switch@77 {
233	compatible = "nxp,pca9548";
234	#address-cells = <1>;
235	#size-cells = <0>;
236	reg = <0x77>;
237	i2c-mux-idle-disconnect; /* may use mux@74 next. */
238
239	i2c_pcie1: i2c@0 {
240	#address-cells = <1>;
241	#size-cells = <0>;
242	reg = <0>;
243	};
244
245	i2c_pcie4: i2c@1 {
246	#address-cells = <1>;
247	#size-cells = <0>;
248	reg = <1>;
249	};
250
251	i2c_pcie5: i2c@2 {
252	#address-cells = <1>;
253	#size-cells = <0>;
254	reg = <2>;
255	};
256
257	i2c_pcie8: i2c@3 {
258	#address-cells = <1>;
259	#size-cells = <0>;
260	reg = <3>;
261	};
262
263	i2c_pcie9: i2c@4 {
264	#address-cells = <1>;
265	#size-cells = <0>;
266	reg = <4>;
267	};
268
269	i2c_pcie10: i2c@5 {
270	#address-cells = <1>;
271	#size-cells = <0>;
272	reg = <5>;
273	};
274
275	i2c_ssd1: i2c@6 {
276	#address-cells = <1>;
277	#size-cells = <0>;
278	reg = <6>;
279	};
280
281	i2c_ssd2: i2c@7 {
282	#address-cells = <1>;
283	#size-cells = <0>;
284	reg = <7>;
285	};
286	};
287	};
288
289	&i2c3 {
290	status = "okay";
291
292	/* BIOS FRU */
293	eeprom@56 {
294	compatible = "atmel,24c64";
295	reg = <0x56>;
296	};
297	};
298
299	&i2c4 {
300	status = "okay";
301	};
302
303	&i2c5 {
304	status = "okay";
305	};
306
307	&i2c6 {
308	status = "okay";
309	};
310
311	&i2c7 {
312	status = "okay";
313
314	/* 0: PSU4
315	* PSU1
316	* PSU3
317	* PSU2
318	*/
319	i2c-switch@70 {
320	compatible = "nxp,pca9546";
321	reg = <0x70>;
322	#address-cells = <1>;
323	#size-cells = <0>;
324
325	i2c_psu4: i2c@0 {
326	#address-cells = <1>;
327	#size-cells = <0>;
328	reg = <0>;
d8a2b2a2 PV	329
	330	psu@59 {
	331	compatible = "pmbus";
	332	reg = <0x59>;
	333	};
f88bc8e1 RA	334	};
	335
	336	i2c_psu1: i2c@1 {
	337	#address-cells = <1>;
	338	#size-cells = <0>;
	339	reg = <1>;
d8a2b2a2 PV	340
	341	psu@58 {
	342	compatible = "pmbus";
	343	reg = <0x58>;
	344	};
f88bc8e1 RA	345	};
	346
	347	i2c_psu3: i2c@2 {
	348	#address-cells = <1>;
	349	#size-cells = <0>;
	350	reg = <2>;
d8a2b2a2 PV	351
	352	psu@58 {
	353	compatible = "pmbus";
	354	reg = <0x58>;
	355	};
f88bc8e1 RA	356	};
	357
	358	i2c_psu2: i2c@3 {
	359	#address-cells = <1>;
	360	#size-cells = <0>;
	361	reg = <3>;
d8a2b2a2 PV	362
	363	psu@59 {
	364	compatible = "pmbus";
	365	reg = <0x59>;
	366	};
f88bc8e1 RA	367	};
	368	};
	369
	370	/* PDB FRU */
	371	eeprom@52 {
	372	compatible = "atmel,24c64";
	373	reg = <0x52>;
	374	};
	375	};
	376
	377	&i2c8 {
	378	status = "okay";
	379
	380	/* BMC FRU */
	381	eeprom@50 {
	382	compatible = "atmel,24c64";
	383	reg = <0x50>;
	384	};
	385	};
	386
	387	&vuart {
	388	status = "okay";
	389	};
	390
	391	&wdt2 {
	392	status = "okay";
	393	};
	394
fde4f21b PV	395	&adc {
	396	status = "okay";
	397	};
	398
f88bc8e1 RA	399	&pwm_tacho {
	400	status = "okay";
	401
	402	pinctrl-names = "default";
	403	pinctrl-0 = <&pinctrl_pwm0_default
	404	&pinctrl_pwm1_default
	405	&pinctrl_pwm2_default
	406	&pinctrl_pwm3_default>;
	407
	408	fan@0 {
	409	reg = <0x00>;
	410	aspeed,fan-tach-ch = /bits/ 8 <0x00>;
	411	};
	412
	413	fan@1 {
	414	reg = <0x01>;
	415	aspeed,fan-tach-ch = /bits/ 8 <0x01>;
	416	};
	417
	418	fan@2 {
	419	reg = <0x02>;
	420	aspeed,fan-tach-ch = /bits/ 8 <0x02>;
	421	};
	422
	423	fan@3 {
	424	reg = <0x03>;
	425	aspeed,fan-tach-ch = /bits/ 8 <0x03>;
	426	};
	427
	428	fan@4 {
	429	reg = <0x00>;
	430	aspeed,fan-tach-ch = /bits/ 8 <0x04>;
	431	};
	432
	433	fan@5 {
	434	reg = <0x01>;
	435	aspeed,fan-tach-ch = /bits/ 8 <0x05>;
	436	};
	437
	438	fan@6 {
	439	reg = <0x02>;
	440	aspeed,fan-tach-ch = /bits/ 8 <0x06>;
	441	};
	442
	443	fan@7 {
	444	reg = <0x03>;
	445	aspeed,fan-tach-ch = /bits/ 8 <0x07>;
	446	};
	447	};
	448
	449	&i2c1mux {
	450	i2c@0 {
	451	reg = <0>;
	452	#address-cells = <1>;
	453	#size-cells = <0>;
	454
	455	/* Memory Riser 1 FRU */
	456	eeprom@50 {
	457	compatible = "atmel,24c02";
	458	reg = <0x50>;
	459	};
	460
	461	/* Memory Riser 2 FRU */
	462	eeprom@51 {
463	compatible = "atmel,24c02";
464	reg = <0x51>;
465	};
466
467	/* Memory Riser 3 FRU */
468	eeprom@52 {
469	compatible = "atmel,24c02";
470	reg = <0x52>;
471	};
472
473	/* Memory Riser 4 FRU */
474	eeprom@53 {
475	compatible = "atmel,24c02";
476	reg = <0x53>;
477	};
478	};
479
480	i2c@1 {
481	reg = <1>;
482	#address-cells = <1>;
483	#size-cells = <0>;
484
485	/* Memory Riser 5 FRU */
486	eeprom@50 {
487	compatible = "atmel,24c02";
488	reg = <0x50>;
489	};
490
491	/* Memory Riser 6 FRU */
492	eeprom@51 {
493	compatible = "atmel,24c02";
494	reg = <0x51>;
495	};
496
497	/* Memory Riser 7 FRU */
498	eeprom@52 {
499	compatible = "atmel,24c02";
500	reg = <0x52>;
501	};
502
503	/* Memory Riser 8 FRU */
504	eeprom@53 {
505	compatible = "atmel,24c02";
506	reg = <0x53>;
507	};
508	};
509	};