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ARM: dts: aspeed: add SPI controller bindings
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / aspeed-g4.dtsi
CommitLineData
d44a1138
JS
1#include "skeleton.dtsi"
2
3/ {
4 model = "Aspeed BMC";
5 compatible = "aspeed,ast2400";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&vic>;
9
10 cpus {
11 #address-cells = <1>;
12 #size-cells = <0>;
13
14 cpu@0 {
15 compatible = "arm,arm926ej-s";
16 device_type = "cpu";
17 reg = <0>;
18 };
19 };
20
21 clocks {
22 clk_clkin: clk_clkin {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <48000000>;
26 };
27
28 };
29
30 ahb {
31 compatible = "simple-bus";
32 #address-cells = <1>;
33 #size-cells = <1>;
34 ranges;
35
74dc3cd3
CLG
36 fmc: flash-controller@1e620000 {
37 reg = < 0x1e620000 0x94
38 0x20000000 0x02000000 >;
39 #address-cells = <1>;
40 #size-cells = <0>;
41 compatible = "aspeed,ast2400-fmc";
42 status = "disabled";
43 interrupts = <19>;
44 flash@0 {
45 reg = < 0 >;
46 compatible = "jedec,spi-nor";
47 status = "disabled";
48 };
49 };
50
51 spi: flash-controller@1e630000 {
52 reg = < 0x1e630000 0x18
53 0x30000000 0x02000000 >;
54 #address-cells = <1>;
55 #size-cells = <0>;
56 compatible = "aspeed,ast2400-spi";
57 status = "disabled";
58 flash@0 {
59 reg = < 0 >;
60 compatible = "jedec,spi-nor";
61 status = "disabled";
62 };
63 };
64
d44a1138
JS
65 vic: interrupt-controller@1e6c0080 {
66 compatible = "aspeed,ast2400-vic";
67 interrupt-controller;
68 #interrupt-cells = <1>;
69 valid-sources = <0xffffffff 0x0007ffff>;
70 reg = <0x1e6c0080 0x80>;
71 };
72
34ea5c9d
JS
73 mac0: ethernet@1e660000 {
74 compatible = "faraday,ftgmac100";
75 reg = <0x1e660000 0x180>;
76 interrupts = <2>;
77 no-hw-checksum;
78 status = "disabled";
79 };
80
81 mac1: ethernet@1e680000 {
82 compatible = "faraday,ftgmac100";
83 reg = <0x1e680000 0x180>;
84 interrupts = <3>;
85 no-hw-checksum;
86 status = "disabled";
87 };
88
d44a1138
JS
89 apb {
90 compatible = "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges;
94
95 clk_hpll: clk_hpll@1e6e2070 {
96 #clock-cells = <0>;
97 compatible = "aspeed,g4-hpll-clock";
98 reg = <0x1e6e2070 0x4>;
99 clocks = <&clk_clkin>;
100 };
101
d9072279
AJ
102 syscon: syscon@1e6e2000 {
103 compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
104 reg = <0x1e6e2000 0x1a8>;
105
106 pinctrl: pinctrl {
107 compatible = "aspeed,g4-pinctrl";
108
109 pinctrl_acpi_default: acpi_default {
110 function = "ACPI";
111 groups = "ACPI";
112 };
113
114 pinctrl_adc0_default: adc0_default {
115 function = "ADC0";
116 groups = "ADC0";
117 };
118
119 pinctrl_adc1_default: adc1_default {
120 function = "ADC1";
121 groups = "ADC1";
122 };
123
124 pinctrl_adc10_default: adc10_default {
125 function = "ADC10";
126 groups = "ADC10";
127 };
128
129 pinctrl_adc11_default: adc11_default {
130 function = "ADC11";
131 groups = "ADC11";
132 };
133
134 pinctrl_adc12_default: adc12_default {
135 function = "ADC12";
136 groups = "ADC12";
137 };
138
139 pinctrl_adc13_default: adc13_default {
140 function = "ADC13";
141 groups = "ADC13";
142 };
143
144 pinctrl_adc14_default: adc14_default {
145 function = "ADC14";
146 groups = "ADC14";
147 };
148
149 pinctrl_adc15_default: adc15_default {
150 function = "ADC15";
151 groups = "ADC15";
152 };
153
154 pinctrl_adc2_default: adc2_default {
155 function = "ADC2";
156 groups = "ADC2";
157 };
158
159 pinctrl_adc3_default: adc3_default {
160 function = "ADC3";
161 groups = "ADC3";
162 };
163
164 pinctrl_adc4_default: adc4_default {
165 function = "ADC4";
166 groups = "ADC4";
167 };
168
169 pinctrl_adc5_default: adc5_default {
170 function = "ADC5";
171 groups = "ADC5";
172 };
173
174 pinctrl_adc6_default: adc6_default {
175 function = "ADC6";
176 groups = "ADC6";
177 };
178
179 pinctrl_adc7_default: adc7_default {
180 function = "ADC7";
181 groups = "ADC7";
182 };
183
184 pinctrl_adc8_default: adc8_default {
185 function = "ADC8";
186 groups = "ADC8";
187 };
188
189 pinctrl_adc9_default: adc9_default {
190 function = "ADC9";
191 groups = "ADC9";
192 };
193
194 pinctrl_bmcint_default: bmcint_default {
195 function = "BMCINT";
196 groups = "BMCINT";
197 };
198
199 pinctrl_ddcclk_default: ddcclk_default {
200 function = "DDCCLK";
201 groups = "DDCCLK";
202 };
203
204 pinctrl_ddcdat_default: ddcdat_default {
205 function = "DDCDAT";
206 groups = "DDCDAT";
207 };
208
209 pinctrl_extrst_default: extrst_default {
210 function = "EXTRST";
211 groups = "EXTRST";
212 };
213
214 pinctrl_flack_default: flack_default {
215 function = "FLACK";
216 groups = "FLACK";
217 };
218
219 pinctrl_flbusy_default: flbusy_default {
220 function = "FLBUSY";
221 groups = "FLBUSY";
222 };
223
224 pinctrl_flwp_default: flwp_default {
225 function = "FLWP";
226 groups = "FLWP";
227 };
228
229 pinctrl_gpid_default: gpid_default {
230 function = "GPID";
231 groups = "GPID";
232 };
233
234 pinctrl_gpid0_default: gpid0_default {
235 function = "GPID0";
236 groups = "GPID0";
237 };
238
239 pinctrl_gpid2_default: gpid2_default {
240 function = "GPID2";
241 groups = "GPID2";
242 };
243
244 pinctrl_gpid4_default: gpid4_default {
245 function = "GPID4";
246 groups = "GPID4";
247 };
248
249 pinctrl_gpid6_default: gpid6_default {
250 function = "GPID6";
251 groups = "GPID6";
252 };
253
254 pinctrl_gpie0_default: gpie0_default {
255 function = "GPIE0";
256 groups = "GPIE0";
257 };
258
259 pinctrl_gpie2_default: gpie2_default {
260 function = "GPIE2";
261 groups = "GPIE2";
262 };
263
264 pinctrl_gpie4_default: gpie4_default {
265 function = "GPIE4";
266 groups = "GPIE4";
267 };
268
269 pinctrl_gpie6_default: gpie6_default {
270 function = "GPIE6";
271 groups = "GPIE6";
272 };
273
274 pinctrl_i2c10_default: i2c10_default {
275 function = "I2C10";
276 groups = "I2C10";
277 };
278
279 pinctrl_i2c11_default: i2c11_default {
280 function = "I2C11";
281 groups = "I2C11";
282 };
283
284 pinctrl_i2c12_default: i2c12_default {
285 function = "I2C12";
286 groups = "I2C12";
287 };
288
289 pinctrl_i2c13_default: i2c13_default {
290 function = "I2C13";
291 groups = "I2C13";
292 };
293
294 pinctrl_i2c14_default: i2c14_default {
295 function = "I2C14";
296 groups = "I2C14";
297 };
298
299 pinctrl_i2c3_default: i2c3_default {
300 function = "I2C3";
301 groups = "I2C3";
302 };
303
304 pinctrl_i2c4_default: i2c4_default {
305 function = "I2C4";
306 groups = "I2C4";
307 };
308
309 pinctrl_i2c5_default: i2c5_default {
310 function = "I2C5";
311 groups = "I2C5";
312 };
313
314 pinctrl_i2c6_default: i2c6_default {
315 function = "I2C6";
316 groups = "I2C6";
317 };
318
319 pinctrl_i2c7_default: i2c7_default {
320 function = "I2C7";
321 groups = "I2C7";
322 };
323
324 pinctrl_i2c8_default: i2c8_default {
325 function = "I2C8";
326 groups = "I2C8";
327 };
328
329 pinctrl_i2c9_default: i2c9_default {
330 function = "I2C9";
331 groups = "I2C9";
332 };
333
334 pinctrl_lpcpd_default: lpcpd_default {
335 function = "LPCPD";
336 groups = "LPCPD";
337 };
338
339 pinctrl_lpcpme_default: lpcpme_default {
340 function = "LPCPME";
341 groups = "LPCPME";
342 };
343
344 pinctrl_lpcrst_default: lpcrst_default {
345 function = "LPCRST";
346 groups = "LPCRST";
347 };
348
349 pinctrl_lpcsmi_default: lpcsmi_default {
350 function = "LPCSMI";
351 groups = "LPCSMI";
352 };
353
354 pinctrl_mac1link_default: mac1link_default {
355 function = "MAC1LINK";
356 groups = "MAC1LINK";
357 };
358
359 pinctrl_mac2link_default: mac2link_default {
360 function = "MAC2LINK";
361 groups = "MAC2LINK";
362 };
363
364 pinctrl_mdio1_default: mdio1_default {
365 function = "MDIO1";
366 groups = "MDIO1";
367 };
368
369 pinctrl_mdio2_default: mdio2_default {
370 function = "MDIO2";
371 groups = "MDIO2";
372 };
373
374 pinctrl_ncts1_default: ncts1_default {
375 function = "NCTS1";
376 groups = "NCTS1";
377 };
378
379 pinctrl_ncts2_default: ncts2_default {
380 function = "NCTS2";
381 groups = "NCTS2";
382 };
383
384 pinctrl_ncts3_default: ncts3_default {
385 function = "NCTS3";
386 groups = "NCTS3";
387 };
388
389 pinctrl_ncts4_default: ncts4_default {
390 function = "NCTS4";
391 groups = "NCTS4";
392 };
393
394 pinctrl_ndcd1_default: ndcd1_default {
395 function = "NDCD1";
396 groups = "NDCD1";
397 };
398
399 pinctrl_ndcd2_default: ndcd2_default {
400 function = "NDCD2";
401 groups = "NDCD2";
402 };
403
404 pinctrl_ndcd3_default: ndcd3_default {
405 function = "NDCD3";
406 groups = "NDCD3";
407 };
408
409 pinctrl_ndcd4_default: ndcd4_default {
410 function = "NDCD4";
411 groups = "NDCD4";
412 };
413
414 pinctrl_ndsr1_default: ndsr1_default {
415 function = "NDSR1";
416 groups = "NDSR1";
417 };
418
419 pinctrl_ndsr2_default: ndsr2_default {
420 function = "NDSR2";
421 groups = "NDSR2";
422 };
423
424 pinctrl_ndsr3_default: ndsr3_default {
425 function = "NDSR3";
426 groups = "NDSR3";
427 };
428
429 pinctrl_ndsr4_default: ndsr4_default {
430 function = "NDSR4";
431 groups = "NDSR4";
432 };
433
434 pinctrl_ndtr1_default: ndtr1_default {
435 function = "NDTR1";
436 groups = "NDTR1";
437 };
438
439 pinctrl_ndtr2_default: ndtr2_default {
440 function = "NDTR2";
441 groups = "NDTR2";
442 };
443
444 pinctrl_ndtr3_default: ndtr3_default {
445 function = "NDTR3";
446 groups = "NDTR3";
447 };
448
449 pinctrl_ndtr4_default: ndtr4_default {
450 function = "NDTR4";
451 groups = "NDTR4";
452 };
453
454 pinctrl_ndts4_default: ndts4_default {
455 function = "NDTS4";
456 groups = "NDTS4";
457 };
458
459 pinctrl_nri1_default: nri1_default {
460 function = "NRI1";
461 groups = "NRI1";
462 };
463
464 pinctrl_nri2_default: nri2_default {
465 function = "NRI2";
466 groups = "NRI2";
467 };
468
469 pinctrl_nri3_default: nri3_default {
470 function = "NRI3";
471 groups = "NRI3";
472 };
473
474 pinctrl_nri4_default: nri4_default {
475 function = "NRI4";
476 groups = "NRI4";
477 };
478
479 pinctrl_nrts1_default: nrts1_default {
480 function = "NRTS1";
481 groups = "NRTS1";
482 };
483
484 pinctrl_nrts2_default: nrts2_default {
485 function = "NRTS2";
486 groups = "NRTS2";
487 };
488
489 pinctrl_nrts3_default: nrts3_default {
490 function = "NRTS3";
491 groups = "NRTS3";
492 };
493
494 pinctrl_oscclk_default: oscclk_default {
495 function = "OSCCLK";
496 groups = "OSCCLK";
497 };
498
499 pinctrl_pwm0_default: pwm0_default {
500 function = "PWM0";
501 groups = "PWM0";
502 };
503
504 pinctrl_pwm1_default: pwm1_default {
505 function = "PWM1";
506 groups = "PWM1";
507 };
508
509 pinctrl_pwm2_default: pwm2_default {
510 function = "PWM2";
511 groups = "PWM2";
512 };
513
514 pinctrl_pwm3_default: pwm3_default {
515 function = "PWM3";
516 groups = "PWM3";
517 };
518
519 pinctrl_pwm4_default: pwm4_default {
520 function = "PWM4";
521 groups = "PWM4";
522 };
523
524 pinctrl_pwm5_default: pwm5_default {
525 function = "PWM5";
526 groups = "PWM5";
527 };
528
529 pinctrl_pwm6_default: pwm6_default {
530 function = "PWM6";
531 groups = "PWM6";
532 };
533
534 pinctrl_pwm7_default: pwm7_default {
535 function = "PWM7";
536 groups = "PWM7";
537 };
538
539 pinctrl_rgmii1_default: rgmii1_default {
540 function = "RGMII1";
541 groups = "RGMII1";
542 };
543
544 pinctrl_rgmii2_default: rgmii2_default {
545 function = "RGMII2";
546 groups = "RGMII2";
547 };
548
549 pinctrl_rmii1_default: rmii1_default {
550 function = "RMII1";
551 groups = "RMII1";
552 };
553
554 pinctrl_rmii2_default: rmii2_default {
555 function = "RMII2";
556 groups = "RMII2";
557 };
558
559 pinctrl_rom16_default: rom16_default {
560 function = "ROM16";
561 groups = "ROM16";
562 };
563
564 pinctrl_rom8_default: rom8_default {
565 function = "ROM8";
566 groups = "ROM8";
567 };
568
569 pinctrl_romcs1_default: romcs1_default {
570 function = "ROMCS1";
571 groups = "ROMCS1";
572 };
573
574 pinctrl_romcs2_default: romcs2_default {
575 function = "ROMCS2";
576 groups = "ROMCS2";
577 };
578
579 pinctrl_romcs3_default: romcs3_default {
580 function = "ROMCS3";
581 groups = "ROMCS3";
582 };
583
584 pinctrl_romcs4_default: romcs4_default {
585 function = "ROMCS4";
586 groups = "ROMCS4";
587 };
588
589 pinctrl_rxd1_default: rxd1_default {
590 function = "RXD1";
591 groups = "RXD1";
592 };
593
594 pinctrl_rxd2_default: rxd2_default {
595 function = "RXD2";
596 groups = "RXD2";
597 };
598
599 pinctrl_rxd3_default: rxd3_default {
600 function = "RXD3";
601 groups = "RXD3";
602 };
603
604 pinctrl_rxd4_default: rxd4_default {
605 function = "RXD4";
606 groups = "RXD4";
607 };
608
609 pinctrl_salt1_default: salt1_default {
610 function = "SALT1";
611 groups = "SALT1";
612 };
613
614 pinctrl_salt2_default: salt2_default {
615 function = "SALT2";
616 groups = "SALT2";
617 };
618
619 pinctrl_salt3_default: salt3_default {
620 function = "SALT3";
621 groups = "SALT3";
622 };
623
624 pinctrl_salt4_default: salt4_default {
625 function = "SALT4";
626 groups = "SALT4";
627 };
628
629 pinctrl_sd1_default: sd1_default {
630 function = "SD1";
631 groups = "SD1";
632 };
633
634 pinctrl_sd2_default: sd2_default {
635 function = "SD2";
636 groups = "SD2";
637 };
638
639 pinctrl_sgpmck_default: sgpmck_default {
640 function = "SGPMCK";
641 groups = "SGPMCK";
642 };
643
644 pinctrl_sgpmi_default: sgpmi_default {
645 function = "SGPMI";
646 groups = "SGPMI";
647 };
648
649 pinctrl_sgpmld_default: sgpmld_default {
650 function = "SGPMLD";
651 groups = "SGPMLD";
652 };
653
654 pinctrl_sgpmo_default: sgpmo_default {
655 function = "SGPMO";
656 groups = "SGPMO";
657 };
658
659 pinctrl_sgpsck_default: sgpsck_default {
660 function = "SGPSCK";
661 groups = "SGPSCK";
662 };
663
664 pinctrl_sgpsi0_default: sgpsi0_default {
665 function = "SGPSI0";
666 groups = "SGPSI0";
667 };
668
669 pinctrl_sgpsi1_default: sgpsi1_default {
670 function = "SGPSI1";
671 groups = "SGPSI1";
672 };
673
674 pinctrl_sgpsld_default: sgpsld_default {
675 function = "SGPSLD";
676 groups = "SGPSLD";
677 };
678
679 pinctrl_sioonctrl_default: sioonctrl_default {
680 function = "SIOONCTRL";
681 groups = "SIOONCTRL";
682 };
683
684 pinctrl_siopbi_default: siopbi_default {
685 function = "SIOPBI";
686 groups = "SIOPBI";
687 };
688
689 pinctrl_siopbo_default: siopbo_default {
690 function = "SIOPBO";
691 groups = "SIOPBO";
692 };
693
694 pinctrl_siopwreq_default: siopwreq_default {
695 function = "SIOPWREQ";
696 groups = "SIOPWREQ";
697 };
698
699 pinctrl_siopwrgd_default: siopwrgd_default {
700 function = "SIOPWRGD";
701 groups = "SIOPWRGD";
702 };
703
704 pinctrl_sios3_default: sios3_default {
705 function = "SIOS3";
706 groups = "SIOS3";
707 };
708
709 pinctrl_sios5_default: sios5_default {
710 function = "SIOS5";
711 groups = "SIOS5";
712 };
713
714 pinctrl_siosci_default: siosci_default {
715 function = "SIOSCI";
716 groups = "SIOSCI";
717 };
718
719 pinctrl_spi1_default: spi1_default {
720 function = "SPI1";
721 groups = "SPI1";
722 };
723
724 pinctrl_spi1debug_default: spi1debug_default {
725 function = "SPI1DEBUG";
726 groups = "SPI1DEBUG";
727 };
728
729 pinctrl_spi1passthru_default: spi1passthru_default {
730 function = "SPI1PASSTHRU";
731 groups = "SPI1PASSTHRU";
732 };
733
734 pinctrl_spics1_default: spics1_default {
735 function = "SPICS1";
736 groups = "SPICS1";
737 };
738
739 pinctrl_timer3_default: timer3_default {
740 function = "TIMER3";
741 groups = "TIMER3";
742 };
743
744 pinctrl_timer4_default: timer4_default {
745 function = "TIMER4";
746 groups = "TIMER4";
747 };
748
749 pinctrl_timer5_default: timer5_default {
750 function = "TIMER5";
751 groups = "TIMER5";
752 };
753
754 pinctrl_timer6_default: timer6_default {
755 function = "TIMER6";
756 groups = "TIMER6";
757 };
758
759 pinctrl_timer7_default: timer7_default {
760 function = "TIMER7";
761 groups = "TIMER7";
762 };
763
764 pinctrl_timer8_default: timer8_default {
765 function = "TIMER8";
766 groups = "TIMER8";
767 };
768
769 pinctrl_txd1_default: txd1_default {
770 function = "TXD1";
771 groups = "TXD1";
772 };
773
774 pinctrl_txd2_default: txd2_default {
775 function = "TXD2";
776 groups = "TXD2";
777 };
778
779 pinctrl_txd3_default: txd3_default {
780 function = "TXD3";
781 groups = "TXD3";
782 };
783
784 pinctrl_txd4_default: txd4_default {
785 function = "TXD4";
786 groups = "TXD4";
787 };
788
789 pinctrl_uart6_default: uart6_default {
790 function = "UART6";
791 groups = "UART6";
792 };
793
794 pinctrl_usbcki_default: usbcki_default {
795 function = "USBCKI";
796 groups = "USBCKI";
797 };
798
799 pinctrl_vgabios_rom_default: vgabios_rom_default {
800 function = "VGABIOS_ROM";
801 groups = "VGABIOS_ROM";
802 };
803
804 pinctrl_vgahs_default: vgahs_default {
805 function = "VGAHS";
806 groups = "VGAHS";
807 };
808
809 pinctrl_vgavs_default: vgavs_default {
810 function = "VGAVS";
811 groups = "VGAVS";
812 };
813
814 pinctrl_vpi18_default: vpi18_default {
815 function = "VPI18";
816 groups = "VPI18";
817 };
818
819 pinctrl_vpi24_default: vpi24_default {
820 function = "VPI24";
821 groups = "VPI24";
822 };
823
824 pinctrl_vpi30_default: vpi30_default {
825 function = "VPI30";
826 groups = "VPI30";
827 };
828
829 pinctrl_vpo12_default: vpo12_default {
830 function = "VPO12";
831 groups = "VPO12";
832 };
833
834 pinctrl_vpo24_default: vpo24_default {
835 function = "VPO24";
836 groups = "VPO24";
837 };
838
839 pinctrl_wdtrst1_default: wdtrst1_default {
840 function = "WDTRST1";
841 groups = "WDTRST1";
842 };
843
844 pinctrl_wdtrst2_default: wdtrst2_default {
845 function = "WDTRST2";
846 groups = "WDTRST2";
847 };
848
849 };
850 };
851
d44a1138
JS
852 clk_apb: clk_apb@1e6e2008 {
853 #clock-cells = <0>;
854 compatible = "aspeed,g4-apb-clock";
855 reg = <0x1e6e2008 0x4>;
856 clocks = <&clk_hpll>;
857 };
858
859 clk_uart: clk_uart@1e6e2008 {
860 #clock-cells = <0>;
861 compatible = "aspeed,uart-clock";
862 reg = <0x1e6e202c 0x4>;
863 };
864
865 sram@1e720000 {
866 compatible = "mmio-sram";
867 reg = <0x1e720000 0x8000>; // 32K
868 };
869
09955007
AJ
870 gpio: gpio@1e780000 {
871 #gpio-cells = <2>;
872 gpio-controller;
873 compatible = "aspeed,ast2400-gpio";
874 reg = <0x1e780000 0x1000>;
875 interrupts = <20>;
876 gpio-ranges = <&pinctrl 0 0 220>;
877 interrupt-controller;
878 };
879
d44a1138
JS
880 timer: timer@1e782000 {
881 compatible = "aspeed,ast2400-timer";
882 reg = <0x1e782000 0x90>;
883 // The moxart_timer driver registers only one
884 // interrupt and assumes it's for timer 1
885 //interrupts = <16 17 18 35 36 37 38 39>;
886 interrupts = <16>;
887 clocks = <&clk_apb>;
888 };
889
890 wdt1: wdt@1e785000 {
891 compatible = "aspeed,wdt";
892 reg = <0x1e785000 0x1c>;
893 interrupts = <27>;
894 };
895
896 wdt2: wdt@1e785020 {
897 compatible = "aspeed,wdt";
898 reg = <0x1e785020 0x1c>;
899 interrupts = <27>;
900 clocks = <&clk_apb>;
901 status = "disabled";
902 };
903
904 uart1: serial@1e783000 {
905 compatible = "ns16550a";
906 reg = <0x1e783000 0x1000>;
907 reg-shift = <2>;
908 interrupts = <9>;
909 clocks = <&clk_uart>;
910 no-loopback-test;
911 status = "disabled";
912 };
913
914 uart2: serial@1e78d000 {
915 compatible = "ns16550a";
916 reg = <0x1e78d000 0x1000>;
917 reg-shift = <2>;
918 interrupts = <32>;
919 clocks = <&clk_uart>;
920 no-loopback-test;
921 status = "disabled";
922 };
923
924 uart3: serial@1e78e000 {
925 compatible = "ns16550a";
926 reg = <0x1e78e000 0x1000>;
927 reg-shift = <2>;
928 interrupts = <33>;
929 clocks = <&clk_uart>;
930 no-loopback-test;
931 status = "disabled";
932 };
933
934 uart4: serial@1e78f000 {
935 compatible = "ns16550a";
936 reg = <0x1e78f000 0x1000>;
937 reg-shift = <2>;
938 interrupts = <34>;
939 clocks = <&clk_uart>;
940 no-loopback-test;
941 status = "disabled";
942 };
943
944 uart5: serial@1e784000 {
945 compatible = "ns16550a";
946 reg = <0x1e784000 0x1000>;
947 reg-shift = <2>;
948 interrupts = <10>;
949 clocks = <&clk_uart>;
950 current-speed = <38400>;
951 no-loopback-test;
952 status = "disabled";
953 };
954
955 uart6: serial@1e787000 {
956 compatible = "ns16550a";
957 reg = <0x1e787000 0x1000>;
958 reg-shift = <2>;
959 interrupts = <10>;
960 clocks = <&clk_uart>;
961 no-loopback-test;
962 status = "disabled";
963 };
964 };
965 };
966};