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Commit | Line | Data |
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fe975cf6 JE |
1 | /* |
2 | * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC | |
3 | * | |
4 | * Copyright (C) 2011 Atmel, | |
5 | * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>, | |
6 | * 2012 Joachim Eastwood <manabian@gmail.com> | |
7 | * | |
8 | * Based on at91sam9260.dtsi | |
9 | * | |
10 | * Licensed under GPLv2 or later. | |
11 | */ | |
12 | ||
6db64d29 | 13 | #include "skeleton.dtsi" |
c9d0f317 | 14 | #include <dt-bindings/pinctrl/at91.h> |
5e8b3bc3 | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
92f8629b | 16 | #include <dt-bindings/gpio/gpio.h> |
68580013 | 17 | #include <dt-bindings/clock/at91.h> |
fe975cf6 JE |
18 | |
19 | / { | |
20 | model = "Atmel AT91RM9200 family SoC"; | |
21 | compatible = "atmel,at91rm9200"; | |
22 | interrupt-parent = <&aic>; | |
23 | ||
24 | aliases { | |
25 | serial0 = &dbgu; | |
26 | serial1 = &usart0; | |
27 | serial2 = &usart1; | |
28 | serial3 = &usart2; | |
29 | serial4 = &usart3; | |
30 | gpio0 = &pioA; | |
31 | gpio1 = &pioB; | |
32 | gpio2 = &pioC; | |
33 | gpio3 = &pioD; | |
34 | tcb0 = &tcb0; | |
35 | tcb1 = &tcb1; | |
2d25210d | 36 | i2c0 = &i2c0; |
883a07f6 JE |
37 | ssc0 = &ssc0; |
38 | ssc1 = &ssc1; | |
39 | ssc2 = &ssc2; | |
fe975cf6 JE |
40 | }; |
41 | cpus { | |
e757a6ee LP |
42 | #address-cells = <0>; |
43 | #size-cells = <0>; | |
44 | ||
45 | cpu { | |
fe975cf6 | 46 | compatible = "arm,arm920t"; |
e757a6ee | 47 | device_type = "cpu"; |
fe975cf6 JE |
48 | }; |
49 | }; | |
50 | ||
51 | memory { | |
52 | reg = <0x20000000 0x04000000>; | |
53 | }; | |
54 | ||
68580013 AB |
55 | clocks { |
56 | slow_xtal: slow_xtal { | |
57 | compatible = "fixed-clock"; | |
58 | #clock-cells = <0>; | |
59 | clock-frequency = <0>; | |
60 | }; | |
61 | ||
62 | main_xtal: main_xtal { | |
63 | compatible = "fixed-clock"; | |
64 | #clock-cells = <0>; | |
65 | clock-frequency = <0>; | |
66 | }; | |
67 | }; | |
68 | ||
fe975cf6 JE |
69 | ahb { |
70 | compatible = "simple-bus"; | |
71 | #address-cells = <1>; | |
72 | #size-cells = <1>; | |
73 | ranges; | |
74 | ||
75 | apb { | |
76 | compatible = "simple-bus"; | |
77 | #address-cells = <1>; | |
78 | #size-cells = <1>; | |
79 | ranges; | |
80 | ||
81 | aic: interrupt-controller@fffff000 { | |
82 | #interrupt-cells = <3>; | |
83 | compatible = "atmel,at91rm9200-aic"; | |
84 | interrupt-controller; | |
85 | reg = <0xfffff000 0x200>; | |
86 | atmel,external-irqs = <25 26 27 28 29 30 31>; | |
87 | }; | |
88 | ||
89 | ramc0: ramc@ffffff00 { | |
90 | compatible = "atmel,at91rm9200-sdramc"; | |
91 | reg = <0xffffff00 0x100>; | |
92 | }; | |
93 | ||
94 | pmc: pmc@fffffc00 { | |
95 | compatible = "atmel,at91rm9200-pmc"; | |
96 | reg = <0xfffffc00 0x100>; | |
68580013 AB |
97 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
98 | interrupt-controller; | |
99 | #address-cells = <1>; | |
100 | #size-cells = <0>; | |
101 | #interrupt-cells = <1>; | |
102 | ||
103 | main_osc: main_osc { | |
104 | compatible = "atmel,at91rm9200-clk-main-osc"; | |
105 | #clock-cells = <0>; | |
106 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; | |
107 | clocks = <&main_xtal>; | |
108 | }; | |
109 | ||
110 | main: mainck { | |
111 | compatible = "atmel,at91rm9200-clk-main"; | |
112 | #clock-cells = <0>; | |
113 | clocks = <&main_osc>; | |
114 | }; | |
115 | ||
116 | plla: pllack { | |
117 | compatible = "atmel,at91rm9200-clk-pll"; | |
118 | #clock-cells = <0>; | |
119 | interrupts-extended = <&pmc AT91_PMC_LOCKA>; | |
120 | clocks = <&main>; | |
121 | reg = <0>; | |
122 | atmel,clk-input-range = <1000000 32000000>; | |
123 | #atmel,pll-clk-output-range-cells = <3>; | |
124 | atmel,pll-clk-output-ranges = <80000000 160000000 0>, | |
125 | <150000000 180000000 2>; | |
126 | }; | |
127 | ||
128 | pllb: pllbck { | |
129 | compatible = "atmel,at91rm9200-clk-pll"; | |
130 | #clock-cells = <0>; | |
131 | interrupts-extended = <&pmc AT91_PMC_LOCKB>; | |
132 | clocks = <&main>; | |
133 | reg = <1>; | |
134 | atmel,clk-input-range = <1000000 32000000>; | |
135 | #atmel,pll-clk-output-range-cells = <3>; | |
136 | atmel,pll-clk-output-ranges = <80000000 160000000 0>, | |
137 | <150000000 180000000 2>; | |
138 | }; | |
139 | ||
140 | mck: masterck { | |
141 | compatible = "atmel,at91rm9200-clk-master"; | |
142 | #clock-cells = <0>; | |
143 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | |
144 | clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; | |
145 | atmel,clk-output-range = <0 80000000>; | |
146 | atmel,clk-divisors = <1 2 3 4>; | |
147 | }; | |
148 | ||
149 | usb: usbck { | |
150 | compatible = "atmel,at91rm9200-clk-usb"; | |
151 | #clock-cells = <0>; | |
ea4fc621 | 152 | atmel,clk-divisors = <1 2 0 0>; |
68580013 AB |
153 | clocks = <&pllb>; |
154 | }; | |
155 | ||
156 | prog: progck { | |
157 | compatible = "atmel,at91rm9200-clk-programmable"; | |
158 | #address-cells = <1>; | |
159 | #size-cells = <0>; | |
160 | interrupt-parent = <&pmc>; | |
161 | clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; | |
162 | ||
163 | prog0: prog0 { | |
164 | #clock-cells = <0>; | |
165 | reg = <0>; | |
166 | interrupts = <AT91_PMC_PCKRDY(0)>; | |
167 | }; | |
168 | ||
169 | prog1: prog1 { | |
170 | #clock-cells = <0>; | |
171 | reg = <1>; | |
172 | interrupts = <AT91_PMC_PCKRDY(1)>; | |
173 | }; | |
174 | ||
175 | prog2: prog2 { | |
176 | #clock-cells = <0>; | |
177 | reg = <2>; | |
178 | interrupts = <AT91_PMC_PCKRDY(2)>; | |
179 | }; | |
180 | ||
181 | prog3: prog3 { | |
182 | #clock-cells = <0>; | |
183 | reg = <3>; | |
184 | interrupts = <AT91_PMC_PCKRDY(3)>; | |
185 | }; | |
186 | }; | |
187 | ||
188 | systemck { | |
189 | compatible = "atmel,at91rm9200-clk-system"; | |
190 | #address-cells = <1>; | |
191 | #size-cells = <0>; | |
192 | ||
193 | udpck: udpck { | |
194 | #clock-cells = <0>; | |
195 | reg = <2>; | |
196 | clocks = <&usb>; | |
197 | }; | |
198 | ||
199 | uhpck: uhpck { | |
200 | #clock-cells = <0>; | |
201 | reg = <4>; | |
202 | clocks = <&usb>; | |
203 | }; | |
204 | ||
205 | pck0: pck0 { | |
206 | #clock-cells = <0>; | |
207 | reg = <8>; | |
208 | clocks = <&prog0>; | |
209 | }; | |
210 | ||
211 | pck1: pck1 { | |
212 | #clock-cells = <0>; | |
213 | reg = <9>; | |
214 | clocks = <&prog1>; | |
215 | }; | |
216 | ||
217 | pck2: pck2 { | |
218 | #clock-cells = <0>; | |
219 | reg = <10>; | |
220 | clocks = <&prog2>; | |
221 | }; | |
222 | ||
223 | pck3: pck3 { | |
224 | #clock-cells = <0>; | |
225 | reg = <11>; | |
226 | clocks = <&prog3>; | |
227 | }; | |
228 | }; | |
229 | ||
230 | periphck { | |
231 | compatible = "atmel,at91rm9200-clk-peripheral"; | |
232 | #address-cells = <1>; | |
233 | #size-cells = <0>; | |
234 | clocks = <&mck>; | |
235 | ||
236 | pioA_clk: pioA_clk { | |
237 | #clock-cells = <0>; | |
238 | reg = <2>; | |
239 | }; | |
240 | ||
241 | pioB_clk: pioB_clk { | |
242 | #clock-cells = <0>; | |
243 | reg = <3>; | |
244 | }; | |
245 | ||
246 | pioC_clk: pioC_clk { | |
247 | #clock-cells = <0>; | |
248 | reg = <4>; | |
249 | }; | |
250 | ||
251 | pioD_clk: pioD_clk { | |
252 | #clock-cells = <0>; | |
253 | reg = <5>; | |
254 | }; | |
255 | ||
256 | usart0_clk: usart0_clk { | |
257 | #clock-cells = <0>; | |
258 | reg = <6>; | |
259 | }; | |
260 | ||
261 | usart1_clk: usart1_clk { | |
262 | #clock-cells = <0>; | |
263 | reg = <7>; | |
264 | }; | |
265 | ||
266 | usart2_clk: usart2_clk { | |
267 | #clock-cells = <0>; | |
268 | reg = <8>; | |
269 | }; | |
270 | ||
271 | usart3_clk: usart3_clk { | |
272 | #clock-cells = <0>; | |
273 | reg = <9>; | |
274 | }; | |
275 | ||
276 | mci0_clk: mci0_clk { | |
277 | #clock-cells = <0>; | |
278 | reg = <10>; | |
279 | }; | |
280 | ||
281 | udc_clk: udc_clk { | |
282 | #clock-cells = <0>; | |
283 | reg = <11>; | |
284 | }; | |
285 | ||
286 | twi0_clk: twi0_clk { | |
287 | reg = <12>; | |
288 | #clock-cells = <0>; | |
289 | }; | |
290 | ||
291 | spi0_clk: spi0_clk { | |
292 | #clock-cells = <0>; | |
293 | reg = <13>; | |
294 | }; | |
295 | ||
296 | ssc0_clk: ssc0_clk { | |
297 | #clock-cells = <0>; | |
298 | reg = <14>; | |
299 | }; | |
300 | ||
301 | ssc1_clk: ssc1_clk { | |
302 | #clock-cells = <0>; | |
303 | reg = <15>; | |
304 | }; | |
305 | ||
306 | ssc2_clk: ssc2_clk { | |
307 | #clock-cells = <0>; | |
308 | reg = <16>; | |
309 | }; | |
310 | ||
311 | tc0_clk: tc0_clk { | |
312 | #clock-cells = <0>; | |
313 | reg = <17>; | |
314 | }; | |
315 | ||
316 | tc1_clk: tc1_clk { | |
317 | #clock-cells = <0>; | |
318 | reg = <18>; | |
319 | }; | |
320 | ||
321 | tc2_clk: tc2_clk { | |
322 | #clock-cells = <0>; | |
323 | reg = <19>; | |
324 | }; | |
325 | ||
326 | tc3_clk: tc3_clk { | |
327 | #clock-cells = <0>; | |
328 | reg = <20>; | |
329 | }; | |
330 | ||
331 | tc4_clk: tc4_clk { | |
332 | #clock-cells = <0>; | |
333 | reg = <21>; | |
334 | }; | |
335 | ||
336 | tc5_clk: tc5_clk { | |
337 | #clock-cells = <0>; | |
338 | reg = <22>; | |
339 | }; | |
340 | ||
341 | ohci_clk: ohci_clk { | |
342 | #clock-cells = <0>; | |
343 | reg = <23>; | |
344 | }; | |
345 | ||
346 | macb0_clk: macb0_clk { | |
347 | #clock-cells = <0>; | |
348 | reg = <24>; | |
349 | }; | |
350 | }; | |
fe975cf6 JE |
351 | }; |
352 | ||
353 | st: timer@fffffd00 { | |
354 | compatible = "atmel,at91rm9200-st"; | |
355 | reg = <0xfffffd00 0x100>; | |
5e8b3bc3 | 356 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
fe975cf6 JE |
357 | }; |
358 | ||
359 | tcb0: timer@fffa0000 { | |
360 | compatible = "atmel,at91rm9200-tcb"; | |
361 | reg = <0xfffa0000 0x100>; | |
5e8b3bc3 JCPV |
362 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 |
363 | 18 IRQ_TYPE_LEVEL_HIGH 0 | |
364 | 19 IRQ_TYPE_LEVEL_HIGH 0>; | |
68580013 AB |
365 | clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; |
366 | clock-names = "t0_clk", "t1_clk", "t2_clk"; | |
fe975cf6 JE |
367 | }; |
368 | ||
369 | tcb1: timer@fffa4000 { | |
370 | compatible = "atmel,at91rm9200-tcb"; | |
371 | reg = <0xfffa4000 0x100>; | |
5e8b3bc3 JCPV |
372 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 |
373 | 21 IRQ_TYPE_LEVEL_HIGH 0 | |
374 | 22 IRQ_TYPE_LEVEL_HIGH 0>; | |
68580013 AB |
375 | clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; |
376 | clock-names = "t0_clk", "t1_clk", "t2_clk"; | |
fe975cf6 JE |
377 | }; |
378 | ||
2d25210d JE |
379 | i2c0: i2c@fffb8000 { |
380 | compatible = "atmel,at91rm9200-i2c"; | |
381 | reg = <0xfffb8000 0x4000>; | |
5e8b3bc3 | 382 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; |
2d25210d JE |
383 | pinctrl-names = "default"; |
384 | pinctrl-0 = <&pinctrl_twi>; | |
68580013 | 385 | clocks = <&twi0_clk>; |
2d25210d JE |
386 | #address-cells = <1>; |
387 | #size-cells = <0>; | |
388 | status = "disabled"; | |
389 | }; | |
390 | ||
4e4c963e JE |
391 | mmc0: mmc@fffb4000 { |
392 | compatible = "atmel,hsmci"; | |
393 | reg = <0xfffb4000 0x4000>; | |
5e8b3bc3 | 394 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; |
68580013 AB |
395 | clocks = <&mci0_clk>; |
396 | clock-names = "mci_clk"; | |
4e4c963e JE |
397 | #address-cells = <1>; |
398 | #size-cells = <0>; | |
90a69f13 | 399 | pinctrl-names = "default"; |
4e4c963e JE |
400 | status = "disabled"; |
401 | }; | |
402 | ||
883a07f6 JE |
403 | ssc0: ssc@fffd0000 { |
404 | compatible = "atmel,at91rm9200-ssc"; | |
405 | reg = <0xfffd0000 0x4000>; | |
5e8b3bc3 | 406 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
883a07f6 JE |
407 | pinctrl-names = "default"; |
408 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
68580013 AB |
409 | clocks = <&ssc0_clk>; |
410 | clock-names = "pclk"; | |
883a07f6 JE |
411 | status = "disable"; |
412 | }; | |
413 | ||
414 | ssc1: ssc@fffd4000 { | |
415 | compatible = "atmel,at91rm9200-ssc"; | |
416 | reg = <0xfffd4000 0x4000>; | |
5e8b3bc3 | 417 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
883a07f6 JE |
418 | pinctrl-names = "default"; |
419 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | |
68580013 AB |
420 | clocks = <&ssc1_clk>; |
421 | clock-names = "pclk"; | |
883a07f6 JE |
422 | status = "disable"; |
423 | }; | |
424 | ||
425 | ssc2: ssc@fffd8000 { | |
426 | compatible = "atmel,at91rm9200-ssc"; | |
427 | reg = <0xfffd8000 0x4000>; | |
5e8b3bc3 | 428 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
883a07f6 JE |
429 | pinctrl-names = "default"; |
430 | pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; | |
68580013 AB |
431 | clocks = <&ssc2_clk>; |
432 | clock-names = "pclk"; | |
883a07f6 JE |
433 | status = "disable"; |
434 | }; | |
435 | ||
ce3b2630 JE |
436 | macb0: ethernet@fffbc000 { |
437 | compatible = "cdns,at91rm9200-emac", "cdns,emac"; | |
438 | reg = <0xfffbc000 0x4000>; | |
5e8b3bc3 | 439 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; |
ce3b2630 JE |
440 | phy-mode = "rmii"; |
441 | pinctrl-names = "default"; | |
442 | pinctrl-0 = <&pinctrl_macb_rmii>; | |
68580013 AB |
443 | clocks = <&macb0_clk>; |
444 | clock-names = "ether_clk"; | |
ce3b2630 JE |
445 | status = "disabled"; |
446 | }; | |
447 | ||
fe975cf6 JE |
448 | pinctrl@fffff400 { |
449 | #address-cells = <1>; | |
450 | #size-cells = <1>; | |
451 | compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; | |
452 | ranges = <0xfffff400 0xfffff400 0x800>; | |
453 | ||
454 | atmel,mux-mask = < | |
455 | /* A B */ | |
456 | 0xffffffff 0xffffffff /* pioA */ | |
457 | 0xffffffff 0x083fffff /* pioB */ | |
458 | 0xffff3fff 0x00000000 /* pioC */ | |
459 | 0x03ff87ff 0x0fffff80 /* pioD */ | |
460 | >; | |
461 | ||
462 | /* shared pinctrl settings */ | |
463 | dbgu { | |
464 | pinctrl_dbgu: dbgu-0 { | |
465 | atmel,pins = | |
c9d0f317 JCPV |
466 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */ |
467 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */ | |
fe975cf6 JE |
468 | }; |
469 | }; | |
470 | ||
471 | uart0 { | |
472 | pinctrl_uart0: uart0-0 { | |
473 | atmel,pins = | |
c9d0f317 JCPV |
474 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
475 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ | |
fe975cf6 JE |
476 | }; |
477 | ||
5cffba20 | 478 | pinctrl_uart0_cts: uart0_cts-0 { |
fe975cf6 | 479 | atmel,pins = |
c9d0f317 | 480 | <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ |
fe975cf6 JE |
481 | }; |
482 | ||
5cffba20 | 483 | pinctrl_uart0_rts: uart0_rts-0 { |
fe975cf6 | 484 | atmel,pins = |
c9d0f317 | 485 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ |
fe975cf6 JE |
486 | }; |
487 | }; | |
488 | ||
489 | uart1 { | |
490 | pinctrl_uart1: uart1-0 { | |
491 | atmel,pins = | |
c9d0f317 JCPV |
492 | <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */ |
493 | AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ | |
fe975cf6 JE |
494 | }; |
495 | ||
496 | pinctrl_uart1_rts: uart1_rts-0 { | |
497 | atmel,pins = | |
c9d0f317 | 498 | <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */ |
fe975cf6 JE |
499 | }; |
500 | ||
501 | pinctrl_uart1_cts: uart1_cts-0 { | |
502 | atmel,pins = | |
c9d0f317 | 503 | <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ |
fe975cf6 JE |
504 | }; |
505 | ||
506 | pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { | |
507 | atmel,pins = | |
c9d0f317 JCPV |
508 | <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ |
509 | AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ | |
fe975cf6 JE |
510 | }; |
511 | ||
512 | pinctrl_uart1_dcd: uart1_dcd-0 { | |
513 | atmel,pins = | |
c9d0f317 | 514 | <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ |
fe975cf6 JE |
515 | }; |
516 | ||
517 | pinctrl_uart1_ri: uart1_ri-0 { | |
518 | atmel,pins = | |
c9d0f317 | 519 | <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ |
fe975cf6 JE |
520 | }; |
521 | }; | |
522 | ||
523 | uart2 { | |
524 | pinctrl_uart2: uart2-0 { | |
525 | atmel,pins = | |
c9d0f317 JCPV |
526 | <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */ |
527 | AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ | |
fe975cf6 JE |
528 | }; |
529 | ||
530 | pinctrl_uart2_rts: uart2_rts-0 { | |
531 | atmel,pins = | |
c9d0f317 | 532 | <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ |
fe975cf6 JE |
533 | }; |
534 | ||
535 | pinctrl_uart2_cts: uart2_cts-0 { | |
536 | atmel,pins = | |
c9d0f317 | 537 | <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */ |
fe975cf6 JE |
538 | }; |
539 | }; | |
540 | ||
541 | uart3 { | |
542 | pinctrl_uart3: uart3-0 { | |
543 | atmel,pins = | |
c9d0f317 JCPV |
544 | <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ |
545 | AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */ | |
fe975cf6 JE |
546 | }; |
547 | ||
548 | pinctrl_uart3_rts: uart3_rts-0 { | |
549 | atmel,pins = | |
c9d0f317 | 550 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ |
fe975cf6 JE |
551 | }; |
552 | ||
553 | pinctrl_uart3_cts: uart3_cts-0 { | |
554 | atmel,pins = | |
c9d0f317 | 555 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ |
fe975cf6 JE |
556 | }; |
557 | }; | |
558 | ||
559 | nand { | |
560 | pinctrl_nand: nand-0 { | |
561 | atmel,pins = | |
c9d0f317 JCPV |
562 | <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */ |
563 | AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */ | |
fe975cf6 JE |
564 | }; |
565 | }; | |
566 | ||
ce3b2630 JE |
567 | macb { |
568 | pinctrl_macb_rmii: macb_rmii-0 { | |
569 | atmel,pins = | |
c9d0f317 JCPV |
570 | <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */ |
571 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */ | |
572 | AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ | |
573 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ | |
574 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ | |
575 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ | |
576 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ | |
577 | AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ | |
578 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ | |
579 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */ | |
ce3b2630 JE |
580 | }; |
581 | ||
582 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { | |
583 | atmel,pins = | |
c9d0f317 JCPV |
584 | <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */ |
585 | AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */ | |
586 | AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */ | |
587 | AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */ | |
588 | AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */ | |
589 | AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */ | |
590 | AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */ | |
591 | AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */ | |
ce3b2630 JE |
592 | }; |
593 | }; | |
594 | ||
4e4c963e JE |
595 | mmc0 { |
596 | pinctrl_mmc0_clk: mmc0_clk-0 { | |
597 | atmel,pins = | |
c9d0f317 | 598 | <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ |
4e4c963e JE |
599 | }; |
600 | ||
601 | pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { | |
602 | atmel,pins = | |
c9d0f317 JCPV |
603 | <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ |
604 | AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */ | |
4e4c963e JE |
605 | }; |
606 | ||
607 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | |
608 | atmel,pins = | |
c9d0f317 JCPV |
609 | <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */ |
610 | AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */ | |
611 | AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */ | |
4e4c963e JE |
612 | }; |
613 | ||
614 | pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { | |
615 | atmel,pins = | |
c9d0f317 JCPV |
616 | <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */ |
617 | AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */ | |
4e4c963e JE |
618 | }; |
619 | ||
620 | pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { | |
621 | atmel,pins = | |
c9d0f317 JCPV |
622 | <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */ |
623 | AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ | |
624 | AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */ | |
4e4c963e JE |
625 | }; |
626 | }; | |
627 | ||
883a07f6 JE |
628 | ssc0 { |
629 | pinctrl_ssc0_tx: ssc0_tx-0 { | |
630 | atmel,pins = | |
c9d0f317 JCPV |
631 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ |
632 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ | |
633 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */ | |
883a07f6 JE |
634 | }; |
635 | ||
636 | pinctrl_ssc0_rx: ssc0_rx-0 { | |
637 | atmel,pins = | |
c9d0f317 JCPV |
638 | <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ |
639 | AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ | |
640 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ | |
883a07f6 JE |
641 | }; |
642 | }; | |
643 | ||
644 | ssc1 { | |
645 | pinctrl_ssc1_tx: ssc1_tx-0 { | |
646 | atmel,pins = | |
c9d0f317 JCPV |
647 | <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ |
648 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ | |
649 | AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ | |
883a07f6 JE |
650 | }; |
651 | ||
652 | pinctrl_ssc1_rx: ssc1_rx-0 { | |
653 | atmel,pins = | |
c9d0f317 JCPV |
654 | <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ |
655 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ | |
656 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ | |
883a07f6 JE |
657 | }; |
658 | }; | |
659 | ||
660 | ssc2 { | |
661 | pinctrl_ssc2_tx: ssc2_tx-0 { | |
662 | atmel,pins = | |
c9d0f317 JCPV |
663 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ |
664 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ | |
665 | AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */ | |
883a07f6 JE |
666 | }; |
667 | ||
668 | pinctrl_ssc2_rx: ssc2_rx-0 { | |
669 | atmel,pins = | |
c9d0f317 JCPV |
670 | <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ |
671 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ | |
672 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ | |
883a07f6 JE |
673 | }; |
674 | }; | |
675 | ||
2d25210d JE |
676 | twi { |
677 | pinctrl_twi: twi-0 { | |
678 | atmel,pins = | |
c9d0f317 JCPV |
679 | <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */ |
680 | AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */ | |
2d25210d | 681 | }; |
83960c82 JE |
682 | |
683 | pinctrl_twi_gpio: twi_gpio-0 { | |
684 | atmel,pins = | |
c9d0f317 JCPV |
685 | <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */ |
686 | AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */ | |
83960c82 | 687 | }; |
2d25210d JE |
688 | }; |
689 | ||
028633c2 BB |
690 | tcb0 { |
691 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | |
692 | atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
693 | }; | |
694 | ||
695 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { | |
696 | atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
697 | }; | |
698 | ||
699 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { | |
700 | atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
701 | }; | |
702 | ||
703 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { | |
704 | atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
705 | }; | |
706 | ||
707 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { | |
708 | atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
709 | }; | |
710 | ||
711 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { | |
712 | atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
713 | }; | |
714 | ||
715 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { | |
716 | atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
717 | }; | |
718 | ||
719 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { | |
720 | atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
721 | }; | |
722 | ||
723 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { | |
724 | atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
725 | }; | |
726 | }; | |
727 | ||
728 | tcb1 { | |
729 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { | |
730 | atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
731 | }; | |
732 | ||
733 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { | |
734 | atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
735 | }; | |
736 | ||
737 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { | |
738 | atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
739 | }; | |
740 | ||
741 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { | |
742 | atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
743 | }; | |
744 | ||
745 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { | |
746 | atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
747 | }; | |
748 | ||
749 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { | |
750 | atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
751 | }; | |
752 | ||
753 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { | |
754 | atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
755 | }; | |
756 | ||
757 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { | |
758 | atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
759 | }; | |
760 | ||
761 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { | |
762 | atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
763 | }; | |
764 | }; | |
765 | ||
32a86877 JCPV |
766 | spi0 { |
767 | pinctrl_spi0: spi0-0 { | |
768 | atmel,pins = | |
769 | <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ | |
770 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ | |
771 | AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ | |
772 | }; | |
773 | }; | |
774 | ||
fe975cf6 JE |
775 | pioA: gpio@fffff400 { |
776 | compatible = "atmel,at91rm9200-gpio"; | |
777 | reg = <0xfffff400 0x200>; | |
5e8b3bc3 | 778 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
fe975cf6 JE |
779 | #gpio-cells = <2>; |
780 | gpio-controller; | |
781 | interrupt-controller; | |
782 | #interrupt-cells = <2>; | |
68580013 | 783 | clocks = <&pioA_clk>; |
fe975cf6 JE |
784 | }; |
785 | ||
786 | pioB: gpio@fffff600 { | |
787 | compatible = "atmel,at91rm9200-gpio"; | |
788 | reg = <0xfffff600 0x200>; | |
5e8b3bc3 | 789 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
fe975cf6 JE |
790 | #gpio-cells = <2>; |
791 | gpio-controller; | |
792 | interrupt-controller; | |
793 | #interrupt-cells = <2>; | |
68580013 | 794 | clocks = <&pioB_clk>; |
fe975cf6 JE |
795 | }; |
796 | ||
797 | pioC: gpio@fffff800 { | |
798 | compatible = "atmel,at91rm9200-gpio"; | |
799 | reg = <0xfffff800 0x200>; | |
5e8b3bc3 | 800 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
fe975cf6 JE |
801 | #gpio-cells = <2>; |
802 | gpio-controller; | |
803 | interrupt-controller; | |
804 | #interrupt-cells = <2>; | |
68580013 | 805 | clocks = <&pioC_clk>; |
fe975cf6 JE |
806 | }; |
807 | ||
808 | pioD: gpio@fffffa00 { | |
809 | compatible = "atmel,at91rm9200-gpio"; | |
810 | reg = <0xfffffa00 0x200>; | |
5e8b3bc3 | 811 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; |
fe975cf6 JE |
812 | #gpio-cells = <2>; |
813 | gpio-controller; | |
814 | interrupt-controller; | |
815 | #interrupt-cells = <2>; | |
68580013 | 816 | clocks = <&pioD_clk>; |
fe975cf6 JE |
817 | }; |
818 | }; | |
819 | ||
820 | dbgu: serial@fffff200 { | |
821 | compatible = "atmel,at91rm9200-usart"; | |
822 | reg = <0xfffff200 0x200>; | |
5e8b3bc3 | 823 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
fe975cf6 JE |
824 | pinctrl-names = "default"; |
825 | pinctrl-0 = <&pinctrl_dbgu>; | |
68580013 AB |
826 | clocks = <&mck>; |
827 | clock-names = "usart"; | |
fe975cf6 JE |
828 | status = "disabled"; |
829 | }; | |
830 | ||
831 | usart0: serial@fffc0000 { | |
832 | compatible = "atmel,at91rm9200-usart"; | |
833 | reg = <0xfffc0000 0x200>; | |
5e8b3bc3 | 834 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
fe975cf6 JE |
835 | atmel,use-dma-rx; |
836 | atmel,use-dma-tx; | |
837 | pinctrl-names = "default"; | |
838 | pinctrl-0 = <&pinctrl_uart0>; | |
68580013 AB |
839 | clocks = <&usart0_clk>; |
840 | clock-names = "usart"; | |
fe975cf6 JE |
841 | status = "disabled"; |
842 | }; | |
843 | ||
844 | usart1: serial@fffc4000 { | |
845 | compatible = "atmel,at91rm9200-usart"; | |
846 | reg = <0xfffc4000 0x200>; | |
5e8b3bc3 | 847 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
fe975cf6 JE |
848 | atmel,use-dma-rx; |
849 | atmel,use-dma-tx; | |
850 | pinctrl-names = "default"; | |
851 | pinctrl-0 = <&pinctrl_uart1>; | |
68580013 AB |
852 | clocks = <&usart1_clk>; |
853 | clock-names = "usart"; | |
fe975cf6 JE |
854 | status = "disabled"; |
855 | }; | |
856 | ||
857 | usart2: serial@fffc8000 { | |
858 | compatible = "atmel,at91rm9200-usart"; | |
859 | reg = <0xfffc8000 0x200>; | |
5e8b3bc3 | 860 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
fe975cf6 JE |
861 | atmel,use-dma-rx; |
862 | atmel,use-dma-tx; | |
863 | pinctrl-names = "default"; | |
864 | pinctrl-0 = <&pinctrl_uart2>; | |
68580013 AB |
865 | clocks = <&usart2_clk>; |
866 | clock-names = "usart"; | |
fe975cf6 JE |
867 | status = "disabled"; |
868 | }; | |
869 | ||
870 | usart3: serial@fffcc000 { | |
871 | compatible = "atmel,at91rm9200-usart"; | |
872 | reg = <0xfffcc000 0x200>; | |
5e8b3bc3 | 873 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; |
fe975cf6 JE |
874 | atmel,use-dma-rx; |
875 | atmel,use-dma-tx; | |
876 | pinctrl-names = "default"; | |
877 | pinctrl-0 = <&pinctrl_uart3>; | |
68580013 AB |
878 | clocks = <&usart3_clk>; |
879 | clock-names = "usart"; | |
fe975cf6 JE |
880 | status = "disabled"; |
881 | }; | |
882 | ||
883 | usb1: gadget@fffb0000 { | |
884 | compatible = "atmel,at91rm9200-udc"; | |
885 | reg = <0xfffb0000 0x4000>; | |
5e8b3bc3 | 886 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; |
68580013 AB |
887 | clocks = <&udc_clk>, <&udpck>; |
888 | clock-names = "pclk", "hclk"; | |
fe975cf6 JE |
889 | status = "disabled"; |
890 | }; | |
32a86877 JCPV |
891 | |
892 | spi0: spi@fffe0000 { | |
893 | #address-cells = <1>; | |
894 | #size-cells = <0>; | |
895 | compatible = "atmel,at91rm9200-spi"; | |
896 | reg = <0xfffe0000 0x200>; | |
897 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; | |
898 | pinctrl-names = "default"; | |
899 | pinctrl-0 = <&pinctrl_spi0>; | |
68580013 AB |
900 | clocks = <&spi0_clk>; |
901 | clock-names = "spi_clk"; | |
32a86877 JCPV |
902 | status = "disabled"; |
903 | }; | |
fe975cf6 JE |
904 | }; |
905 | ||
906 | nand0: nand@40000000 { | |
907 | compatible = "atmel,at91rm9200-nand"; | |
908 | #address-cells = <1>; | |
909 | #size-cells = <1>; | |
910 | reg = <0x40000000 0x10000000>; | |
911 | atmel,nand-addr-offset = <21>; | |
912 | atmel,nand-cmd-offset = <22>; | |
913 | pinctrl-names = "default"; | |
914 | pinctrl-0 = <&pinctrl_nand>; | |
915 | nand-ecc-mode = "soft"; | |
92f8629b | 916 | gpios = <&pioC 2 GPIO_ACTIVE_HIGH |
fe975cf6 | 917 | 0 |
92f8629b | 918 | &pioB 1 GPIO_ACTIVE_HIGH |
fe975cf6 JE |
919 | >; |
920 | status = "disabled"; | |
921 | }; | |
922 | ||
923 | usb0: ohci@00300000 { | |
924 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
925 | reg = <0x00300000 0x100000>; | |
5e8b3bc3 | 926 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; |
68580013 AB |
927 | clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; |
928 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | |
fe975cf6 JE |
929 | status = "disabled"; |
930 | }; | |
931 | }; | |
932 | ||
933 | i2c@0 { | |
934 | compatible = "i2c-gpio"; | |
92f8629b JCPV |
935 | gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ |
936 | &pioA 26 GPIO_ACTIVE_HIGH /* scl */ | |
fe975cf6 JE |
937 | >; |
938 | i2c-gpio,sda-open-drain; | |
939 | i2c-gpio,scl-open-drain; | |
940 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
83960c82 JE |
941 | pinctrl-names = "default"; |
942 | pinctrl-0 = <&pinctrl_twi_gpio>; | |
fe975cf6 JE |
943 | #address-cells = <1>; |
944 | #size-cells = <0>; | |
945 | status = "disabled"; | |
946 | }; | |
947 | }; |