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Commit | Line | Data |
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4abb3677 JCPV |
1 | /* |
2 | * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
5 | * | |
6 | * Licensed under GPLv2 only. | |
7 | */ | |
8 | ||
6db64d29 | 9 | #include "skeleton.dtsi" |
c9d0f317 | 10 | #include <dt-bindings/pinctrl/at91.h> |
5e8b3bc3 | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
92f8629b | 12 | #include <dt-bindings/gpio/gpio.h> |
c2375821 | 13 | #include <dt-bindings/clock/at91.h> |
4abb3677 JCPV |
14 | |
15 | / { | |
16 | model = "Atmel AT91SAM9263 family SoC"; | |
17 | compatible = "atmel,at91sam9263"; | |
18 | interrupt-parent = <&aic>; | |
19 | ||
20 | aliases { | |
21 | serial0 = &dbgu; | |
22 | serial1 = &usart0; | |
23 | serial2 = &usart1; | |
24 | serial3 = &usart2; | |
25 | gpio0 = &pioA; | |
26 | gpio1 = &pioB; | |
27 | gpio2 = &pioC; | |
28 | gpio3 = &pioD; | |
29 | gpio4 = &pioE; | |
30 | tcb0 = &tcb0; | |
05dcd361 | 31 | i2c0 = &i2c0; |
099343c6 BS |
32 | ssc0 = &ssc0; |
33 | ssc1 = &ssc1; | |
f3ab0527 | 34 | pwm0 = &pwm0; |
4abb3677 | 35 | }; |
c2375821 | 36 | |
4abb3677 | 37 | cpus { |
e757a6ee LP |
38 | #address-cells = <0>; |
39 | #size-cells = <0>; | |
40 | ||
41 | cpu { | |
42 | compatible = "arm,arm926ej-s"; | |
43 | device_type = "cpu"; | |
4abb3677 JCPV |
44 | }; |
45 | }; | |
46 | ||
47 | memory { | |
48 | reg = <0x20000000 0x08000000>; | |
49 | }; | |
50 | ||
c2375821 AB |
51 | clocks { |
52 | main_xtal: main_xtal { | |
53 | compatible = "fixed-clock"; | |
54 | #clock-cells = <0>; | |
55 | clock-frequency = <0>; | |
56 | }; | |
57 | ||
58 | slow_xtal: slow_xtal { | |
59 | compatible = "fixed-clock"; | |
60 | #clock-cells = <0>; | |
61 | clock-frequency = <0>; | |
62 | }; | |
63 | }; | |
64 | ||
8dccafaa | 65 | sram0: sram@300000 { |
f04660e4 AB |
66 | compatible = "mmio-sram"; |
67 | reg = <0x00300000 0x14000>; | |
68 | }; | |
69 | ||
8dccafaa | 70 | sram1: sram@500000 { |
f04660e4 | 71 | compatible = "mmio-sram"; |
940e766a | 72 | reg = <0x00500000 0x4000>; |
f04660e4 AB |
73 | }; |
74 | ||
4abb3677 JCPV |
75 | ahb { |
76 | compatible = "simple-bus"; | |
77 | #address-cells = <1>; | |
78 | #size-cells = <1>; | |
79 | ranges; | |
80 | ||
81 | apb { | |
82 | compatible = "simple-bus"; | |
83 | #address-cells = <1>; | |
84 | #size-cells = <1>; | |
85 | ranges; | |
86 | ||
87 | aic: interrupt-controller@fffff000 { | |
f8a073ee | 88 | #interrupt-cells = <3>; |
4abb3677 JCPV |
89 | compatible = "atmel,at91rm9200-aic"; |
90 | interrupt-controller; | |
91 | reg = <0xfffff000 0x200>; | |
c6573943 | 92 | atmel,external-irqs = <30 31>; |
4abb3677 JCPV |
93 | }; |
94 | ||
95 | pmc: pmc@fffffc00 { | |
620f5033 | 96 | compatible = "atmel,at91rm9200-pmc", "syscon"; |
4abb3677 | 97 | reg = <0xfffffc00 0x100>; |
c2375821 AB |
98 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
99 | interrupt-controller; | |
100 | #address-cells = <1>; | |
101 | #size-cells = <0>; | |
102 | #interrupt-cells = <1>; | |
103 | ||
104 | main_osc: main_osc { | |
105 | compatible = "atmel,at91rm9200-clk-main-osc"; | |
106 | #clock-cells = <0>; | |
107 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; | |
108 | clocks = <&main_xtal>; | |
109 | }; | |
110 | ||
111 | main: mainck { | |
112 | compatible = "atmel,at91rm9200-clk-main"; | |
113 | #clock-cells = <0>; | |
114 | clocks = <&main_osc>; | |
115 | }; | |
116 | ||
117 | plla: pllack { | |
118 | compatible = "atmel,at91rm9200-clk-pll"; | |
119 | #clock-cells = <0>; | |
120 | interrupts-extended = <&pmc AT91_PMC_LOCKA>; | |
121 | clocks = <&main>; | |
122 | reg = <0>; | |
123 | atmel,clk-input-range = <1000000 32000000>; | |
124 | #atmel,pll-clk-output-range-cells = <4>; | |
125 | atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, | |
126 | <190000000 240000000 2 1>; | |
127 | }; | |
128 | ||
129 | pllb: pllbck { | |
130 | compatible = "atmel,at91rm9200-clk-pll"; | |
131 | #clock-cells = <0>; | |
132 | interrupts-extended = <&pmc AT91_PMC_LOCKB>; | |
133 | clocks = <&main>; | |
134 | reg = <1>; | |
106c67af | 135 | atmel,clk-input-range = <1000000 32000000>; |
c2375821 | 136 | #atmel,pll-clk-output-range-cells = <4>; |
106c67af BB |
137 | atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, |
138 | <190000000 240000000 2 1>; | |
c2375821 AB |
139 | }; |
140 | ||
141 | mck: masterck { | |
142 | compatible = "atmel,at91rm9200-clk-master"; | |
143 | #clock-cells = <0>; | |
144 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | |
145 | clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; | |
146 | atmel,clk-output-range = <0 120000000>; | |
147 | atmel,clk-divisors = <1 2 4 0>; | |
148 | }; | |
149 | ||
150 | usb: usbck { | |
151 | compatible = "atmel,at91rm9200-clk-usb"; | |
152 | #clock-cells = <0>; | |
153 | atmel,clk-divisors = <1 2 4 0>; | |
154 | clocks = <&pllb>; | |
155 | }; | |
156 | ||
157 | prog: progck { | |
158 | compatible = "atmel,at91rm9200-clk-programmable"; | |
159 | #address-cells = <1>; | |
160 | #size-cells = <0>; | |
161 | interrupt-parent = <&pmc>; | |
162 | clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; | |
163 | ||
164 | prog0: prog0 { | |
165 | #clock-cells = <0>; | |
166 | reg = <0>; | |
167 | interrupts = <AT91_PMC_PCKRDY(0)>; | |
168 | }; | |
169 | ||
170 | prog1: prog1 { | |
171 | #clock-cells = <0>; | |
172 | reg = <1>; | |
173 | interrupts = <AT91_PMC_PCKRDY(1)>; | |
174 | }; | |
175 | ||
176 | prog2: prog2 { | |
177 | #clock-cells = <0>; | |
178 | reg = <2>; | |
179 | interrupts = <AT91_PMC_PCKRDY(2)>; | |
180 | }; | |
181 | ||
182 | prog3: prog3 { | |
183 | #clock-cells = <0>; | |
184 | reg = <3>; | |
185 | interrupts = <AT91_PMC_PCKRDY(3)>; | |
186 | }; | |
187 | }; | |
188 | ||
189 | systemck { | |
190 | compatible = "atmel,at91rm9200-clk-system"; | |
191 | #address-cells = <1>; | |
192 | #size-cells = <0>; | |
193 | ||
194 | uhpck: uhpck { | |
195 | #clock-cells = <0>; | |
196 | reg = <6>; | |
197 | clocks = <&usb>; | |
198 | }; | |
199 | ||
200 | udpck: udpck { | |
201 | #clock-cells = <0>; | |
202 | reg = <7>; | |
203 | clocks = <&usb>; | |
204 | }; | |
205 | ||
206 | pck0: pck0 { | |
207 | #clock-cells = <0>; | |
208 | reg = <8>; | |
209 | clocks = <&prog0>; | |
210 | }; | |
211 | ||
212 | pck1: pck1 { | |
213 | #clock-cells = <0>; | |
214 | reg = <9>; | |
215 | clocks = <&prog1>; | |
216 | }; | |
217 | ||
218 | pck2: pck2 { | |
219 | #clock-cells = <0>; | |
220 | reg = <10>; | |
221 | clocks = <&prog2>; | |
222 | }; | |
223 | ||
224 | pck3: pck3 { | |
225 | #clock-cells = <0>; | |
226 | reg = <11>; | |
227 | clocks = <&prog3>; | |
228 | }; | |
229 | }; | |
230 | ||
231 | periphck { | |
232 | compatible = "atmel,at91rm9200-clk-peripheral"; | |
233 | #address-cells = <1>; | |
234 | #size-cells = <0>; | |
235 | clocks = <&mck>; | |
236 | ||
237 | pioA_clk: pioA_clk { | |
238 | #clock-cells = <0>; | |
239 | reg = <2>; | |
240 | }; | |
241 | ||
242 | pioB_clk: pioB_clk { | |
243 | #clock-cells = <0>; | |
244 | reg = <3>; | |
245 | }; | |
246 | ||
247 | pioCDE_clk: pioCDE_clk { | |
248 | #clock-cells = <0>; | |
249 | reg = <4>; | |
250 | }; | |
251 | ||
252 | usart0_clk: usart0_clk { | |
253 | #clock-cells = <0>; | |
254 | reg = <7>; | |
255 | }; | |
256 | ||
257 | usart1_clk: usart1_clk { | |
258 | #clock-cells = <0>; | |
259 | reg = <8>; | |
260 | }; | |
261 | ||
262 | usart2_clk: usart2_clk { | |
263 | #clock-cells = <0>; | |
264 | reg = <9>; | |
265 | }; | |
266 | ||
267 | mci0_clk: mci0_clk { | |
268 | #clock-cells = <0>; | |
269 | reg = <10>; | |
270 | }; | |
271 | ||
272 | mci1_clk: mci1_clk { | |
273 | #clock-cells = <0>; | |
274 | reg = <11>; | |
275 | }; | |
276 | ||
277 | can_clk: can_clk { | |
278 | #clock-cells = <0>; | |
279 | reg = <12>; | |
280 | }; | |
281 | ||
282 | twi0_clk: twi0_clk { | |
283 | #clock-cells = <0>; | |
284 | reg = <13>; | |
285 | }; | |
286 | ||
287 | spi0_clk: spi0_clk { | |
288 | #clock-cells = <0>; | |
289 | reg = <14>; | |
290 | }; | |
291 | ||
292 | spi1_clk: spi1_clk { | |
293 | #clock-cells = <0>; | |
294 | reg = <15>; | |
295 | }; | |
296 | ||
297 | ssc0_clk: ssc0_clk { | |
298 | #clock-cells = <0>; | |
299 | reg = <16>; | |
300 | }; | |
301 | ||
302 | ssc1_clk: ssc1_clk { | |
303 | #clock-cells = <0>; | |
304 | reg = <17>; | |
305 | }; | |
306 | ||
226b7b61 | 307 | ac97_clk: ac97_clk { |
c2375821 AB |
308 | #clock-cells = <0>; |
309 | reg = <18>; | |
310 | }; | |
311 | ||
312 | tcb_clk: tcb_clk { | |
313 | #clock-cells = <0>; | |
314 | reg = <19>; | |
315 | }; | |
316 | ||
317 | pwm_clk: pwm_clk { | |
318 | #clock-cells = <0>; | |
319 | reg = <20>; | |
320 | }; | |
321 | ||
322 | macb0_clk: macb0_clk { | |
323 | #clock-cells = <0>; | |
324 | reg = <21>; | |
325 | }; | |
326 | ||
327 | g2de_clk: g2de_clk { | |
328 | #clock-cells = <0>; | |
329 | reg = <23>; | |
330 | }; | |
331 | ||
332 | udc_clk: udc_clk { | |
333 | #clock-cells = <0>; | |
334 | reg = <24>; | |
335 | }; | |
336 | ||
337 | isi_clk: isi_clk { | |
338 | #clock-cells = <0>; | |
339 | reg = <25>; | |
340 | }; | |
341 | ||
342 | lcd_clk: lcd_clk { | |
343 | #clock-cells = <0>; | |
344 | reg = <26>; | |
345 | }; | |
346 | ||
347 | dma_clk: dma_clk { | |
348 | #clock-cells = <0>; | |
349 | reg = <27>; | |
350 | }; | |
351 | ||
352 | ohci_clk: ohci_clk { | |
353 | #clock-cells = <0>; | |
354 | reg = <29>; | |
355 | }; | |
356 | }; | |
4abb3677 JCPV |
357 | }; |
358 | ||
1e165a7d | 359 | ramc0: ramc@ffffe200 { |
4abb3677 | 360 | compatible = "atmel,at91sam9260-sdramc"; |
1e165a7d MR |
361 | reg = <0xffffe200 0x200>; |
362 | }; | |
363 | ||
d9c41bf3 BB |
364 | smc0: smc@ffffe400 { |
365 | compatible = "atmel,at91sam9260-smc", "syscon"; | |
366 | reg = <0xffffe400 0x200>; | |
367 | }; | |
368 | ||
1e165a7d MR |
369 | ramc1: ramc@ffffe800 { |
370 | compatible = "atmel,at91sam9260-sdramc"; | |
371 | reg = <0xffffe800 0x200>; | |
4abb3677 JCPV |
372 | }; |
373 | ||
d9c41bf3 BB |
374 | smc1: smc@ffffea00 { |
375 | compatible = "atmel,at91sam9260-smc", "syscon"; | |
376 | reg = <0xffffea00 0x200>; | |
377 | }; | |
378 | ||
379 | matrix: matrix@ffffec00 { | |
380 | compatible = "atmel,at91sam9263-matrix", "syscon"; | |
381 | reg = <0xffffec00 0x200>; | |
382 | }; | |
383 | ||
4abb3677 JCPV |
384 | pit: timer@fffffd30 { |
385 | compatible = "atmel,at91sam9260-pit"; | |
386 | reg = <0xfffffd30 0xf>; | |
5e8b3bc3 | 387 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
c2375821 | 388 | clocks = <&mck>; |
4abb3677 JCPV |
389 | }; |
390 | ||
391 | tcb0: timer@fff7c000 { | |
d89b16f3 AB |
392 | compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; |
393 | #address-cells = <1>; | |
394 | #size-cells = <0>; | |
4abb3677 | 395 | reg = <0xfff7c000 0x100>; |
5e8b3bc3 | 396 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; |
53b0b378 AB |
397 | clocks = <&tcb_clk>, <&slow_xtal>; |
398 | clock-names = "t0_clk", "slow_clk"; | |
4abb3677 JCPV |
399 | }; |
400 | ||
401 | rstc@fffffd00 { | |
402 | compatible = "atmel,at91sam9260-rstc"; | |
403 | reg = <0xfffffd00 0x10>; | |
53b0b378 | 404 | clocks = <&slow_xtal>; |
4abb3677 JCPV |
405 | }; |
406 | ||
407 | shdwc@fffffd10 { | |
408 | compatible = "atmel,at91sam9260-shdwc"; | |
409 | reg = <0xfffffd10 0x10>; | |
53b0b378 | 410 | clocks = <&slow_xtal>; |
4abb3677 JCPV |
411 | }; |
412 | ||
e4541ff2 JCPV |
413 | pinctrl@fffff200 { |
414 | #address-cells = <1>; | |
415 | #size-cells = <1>; | |
416 | compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; | |
417 | ranges = <0xfffff200 0xfffff200 0xa00>; | |
418 | ||
5314ec8e JCPV |
419 | atmel,mux-mask = < |
420 | /* A B */ | |
421 | 0xfffffffb 0xffffe07f /* pioA */ | |
422 | 0x0007ffff 0x39072fff /* pioB */ | |
423 | 0xffffffff 0x3ffffff8 /* pioC */ | |
424 | 0xfffffbff 0xffffffff /* pioD */ | |
425 | 0xffe00fff 0xfbfcff00 /* pioE */ | |
426 | >; | |
427 | ||
428 | /* shared pinctrl settings */ | |
ec6754a7 JCPV |
429 | dbgu { |
430 | pinctrl_dbgu: dbgu-0 { | |
431 | atmel,pins = | |
138c2b2f SR |
432 | <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP |
433 | AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
ec6754a7 JCPV |
434 | }; |
435 | }; | |
436 | ||
9e3129e9 JCPV |
437 | usart0 { |
438 | pinctrl_usart0: usart0-0 { | |
ec6754a7 | 439 | atmel,pins = |
5e04822f PR |
440 | <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE |
441 | AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; | |
ec6754a7 JCPV |
442 | }; |
443 | ||
c58c0c5a | 444 | pinctrl_usart0_rts: usart0_rts-0 { |
ec6754a7 | 445 | atmel,pins = |
c9d0f317 | 446 | <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */ |
c58c0c5a JCPV |
447 | }; |
448 | ||
449 | pinctrl_usart0_cts: usart0_cts-0 { | |
450 | atmel,pins = | |
c9d0f317 | 451 | <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */ |
ec6754a7 JCPV |
452 | }; |
453 | }; | |
454 | ||
9e3129e9 JCPV |
455 | usart1 { |
456 | pinctrl_usart1: usart1-0 { | |
ec6754a7 | 457 | atmel,pins = |
5e04822f PR |
458 | <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE |
459 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; | |
ec6754a7 JCPV |
460 | }; |
461 | ||
c58c0c5a | 462 | pinctrl_usart1_rts: usart1_rts-0 { |
ec6754a7 | 463 | atmel,pins = |
c9d0f317 | 464 | <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */ |
c58c0c5a JCPV |
465 | }; |
466 | ||
467 | pinctrl_usart1_cts: usart1_cts-0 { | |
468 | atmel,pins = | |
c9d0f317 | 469 | <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */ |
ec6754a7 JCPV |
470 | }; |
471 | }; | |
472 | ||
9e3129e9 JCPV |
473 | usart2 { |
474 | pinctrl_usart2: usart2-0 { | |
ec6754a7 | 475 | atmel,pins = |
5e04822f PR |
476 | <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE |
477 | AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; | |
ec6754a7 JCPV |
478 | }; |
479 | ||
c58c0c5a JCPV |
480 | pinctrl_usart2_rts: usart2_rts-0 { |
481 | atmel,pins = | |
c9d0f317 | 482 | <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */ |
c58c0c5a JCPV |
483 | }; |
484 | ||
485 | pinctrl_usart2_cts: usart2_cts-0 { | |
ec6754a7 | 486 | atmel,pins = |
c9d0f317 | 487 | <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */ |
ec6754a7 JCPV |
488 | }; |
489 | }; | |
5314ec8e | 490 | |
7a38d450 | 491 | nand { |
1004a297 | 492 | pinctrl_nand_rb: nand-rb-0 { |
7a38d450 | 493 | atmel,pins = |
1004a297 BB |
494 | <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; |
495 | }; | |
496 | ||
497 | pinctrl_nand_cs: nand-cs-0 { | |
498 | atmel,pins = | |
499 | <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; | |
7a38d450 JCPV |
500 | }; |
501 | }; | |
502 | ||
d9b4fe83 JCPV |
503 | macb { |
504 | pinctrl_macb_rmii: macb_rmii-0 { | |
505 | atmel,pins = | |
c9d0f317 JCPV |
506 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ |
507 | AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ | |
508 | AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ | |
509 | AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ | |
510 | AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ | |
511 | AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ | |
512 | AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ | |
513 | AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ | |
514 | AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ | |
515 | AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ | |
d9b4fe83 JCPV |
516 | }; |
517 | ||
518 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { | |
519 | atmel,pins = | |
c9d0f317 JCPV |
520 | <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ |
521 | AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ | |
522 | AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */ | |
523 | AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */ | |
524 | AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */ | |
525 | AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ | |
526 | AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ | |
527 | AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */ | |
d9b4fe83 JCPV |
528 | }; |
529 | }; | |
530 | ||
d4fe9ac7 JCPV |
531 | mmc0 { |
532 | pinctrl_mmc0_clk: mmc0_clk-0 { | |
533 | atmel,pins = | |
c9d0f317 | 534 | <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */ |
d4fe9ac7 JCPV |
535 | }; |
536 | ||
537 | pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { | |
538 | atmel,pins = | |
c9d0f317 JCPV |
539 | <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ |
540 | AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */ | |
d4fe9ac7 JCPV |
541 | }; |
542 | ||
543 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | |
544 | atmel,pins = | |
c9d0f317 JCPV |
545 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ |
546 | AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ | |
547 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ | |
d4fe9ac7 JCPV |
548 | }; |
549 | ||
550 | pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { | |
551 | atmel,pins = | |
c9d0f317 JCPV |
552 | <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ |
553 | AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */ | |
d4fe9ac7 JCPV |
554 | }; |
555 | ||
556 | pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { | |
557 | atmel,pins = | |
c9d0f317 JCPV |
558 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ |
559 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ | |
560 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ | |
d4fe9ac7 JCPV |
561 | }; |
562 | }; | |
563 | ||
564 | mmc1 { | |
565 | pinctrl_mmc1_clk: mmc1_clk-0 { | |
566 | atmel,pins = | |
c9d0f317 | 567 | <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ |
d4fe9ac7 JCPV |
568 | }; |
569 | ||
570 | pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { | |
571 | atmel,pins = | |
c9d0f317 JCPV |
572 | <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ |
573 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */ | |
d4fe9ac7 JCPV |
574 | }; |
575 | ||
576 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { | |
577 | atmel,pins = | |
c9d0f317 JCPV |
578 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ |
579 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ | |
580 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ | |
d4fe9ac7 JCPV |
581 | }; |
582 | ||
583 | pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { | |
584 | atmel,pins = | |
c9d0f317 JCPV |
585 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */ |
586 | AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */ | |
d4fe9ac7 JCPV |
587 | }; |
588 | ||
589 | pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { | |
590 | atmel,pins = | |
c9d0f317 JCPV |
591 | <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */ |
592 | AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ | |
593 | AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */ | |
d4fe9ac7 JCPV |
594 | }; |
595 | }; | |
596 | ||
544ae6b2 BS |
597 | ssc0 { |
598 | pinctrl_ssc0_tx: ssc0_tx-0 { | |
599 | atmel,pins = | |
c9d0f317 JCPV |
600 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */ |
601 | AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */ | |
602 | AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ | |
544ae6b2 BS |
603 | }; |
604 | ||
605 | pinctrl_ssc0_rx: ssc0_rx-0 { | |
606 | atmel,pins = | |
c9d0f317 JCPV |
607 | <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */ |
608 | AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */ | |
609 | AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */ | |
544ae6b2 BS |
610 | }; |
611 | }; | |
612 | ||
613 | ssc1 { | |
614 | pinctrl_ssc1_tx: ssc1_tx-0 { | |
615 | atmel,pins = | |
c9d0f317 JCPV |
616 | <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ |
617 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ | |
618 | AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ | |
544ae6b2 BS |
619 | }; |
620 | ||
621 | pinctrl_ssc1_rx: ssc1_rx-0 { | |
622 | atmel,pins = | |
c9d0f317 JCPV |
623 | <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ |
624 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ | |
625 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ | |
544ae6b2 BS |
626 | }; |
627 | }; | |
628 | ||
a68b728f WY |
629 | spi0 { |
630 | pinctrl_spi0: spi0-0 { | |
631 | atmel,pins = | |
c9d0f317 JCPV |
632 | <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */ |
633 | AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */ | |
634 | AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */ | |
a68b728f WY |
635 | }; |
636 | }; | |
637 | ||
638 | spi1 { | |
639 | pinctrl_spi1: spi1-0 { | |
640 | atmel,pins = | |
c9d0f317 JCPV |
641 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */ |
642 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */ | |
643 | AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */ | |
a68b728f WY |
644 | }; |
645 | }; | |
646 | ||
028633c2 BB |
647 | tcb0 { |
648 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | |
649 | atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
650 | }; | |
651 | ||
652 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { | |
653 | atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
654 | }; | |
655 | ||
656 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { | |
657 | atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
658 | }; | |
659 | ||
660 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { | |
661 | atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
662 | }; | |
663 | ||
664 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { | |
665 | atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
666 | }; | |
667 | ||
668 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { | |
669 | atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
670 | }; | |
671 | ||
672 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { | |
673 | atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
674 | }; | |
675 | ||
676 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { | |
677 | atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
678 | }; | |
679 | ||
680 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { | |
681 | atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; | |
682 | }; | |
683 | }; | |
684 | ||
f8a0d793 JCPV |
685 | fb { |
686 | pinctrl_fb: fb-0 { | |
687 | atmel,pins = | |
688 | <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */ | |
689 | AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */ | |
690 | AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */ | |
691 | AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */ | |
692 | AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */ | |
693 | AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */ | |
694 | AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */ | |
695 | AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */ | |
696 | AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */ | |
697 | AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */ | |
698 | AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */ | |
699 | AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */ | |
700 | AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */ | |
701 | AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */ | |
702 | AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */ | |
703 | AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */ | |
704 | AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */ | |
705 | AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */ | |
706 | AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */ | |
707 | AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */ | |
708 | AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */ | |
709 | AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */ | |
710 | }; | |
711 | }; | |
712 | ||
2667c6ad AS |
713 | can { |
714 | pinctrl_can_rx_tx: can_rx_tx { | |
715 | atmel,pins = | |
716 | <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */ | |
717 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */ | |
718 | }; | |
719 | }; | |
720 | ||
c7f85be1 AS |
721 | ac97 { |
722 | pinctrl_ac97: ac97-0 { | |
723 | atmel,pins = | |
724 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */ | |
725 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A AC97CK pin */ | |
726 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A AC97TX pin */ | |
727 | AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A AC97RX pin */ | |
728 | }; | |
729 | }; | |
730 | ||
e4541ff2 JCPV |
731 | pioA: gpio@fffff200 { |
732 | compatible = "atmel,at91rm9200-gpio"; | |
733 | reg = <0xfffff200 0x200>; | |
5e8b3bc3 | 734 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
e4541ff2 JCPV |
735 | #gpio-cells = <2>; |
736 | gpio-controller; | |
737 | interrupt-controller; | |
738 | #interrupt-cells = <2>; | |
c2375821 | 739 | clocks = <&pioA_clk>; |
e4541ff2 JCPV |
740 | }; |
741 | ||
742 | pioB: gpio@fffff400 { | |
743 | compatible = "atmel,at91rm9200-gpio"; | |
744 | reg = <0xfffff400 0x200>; | |
5e8b3bc3 | 745 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
e4541ff2 JCPV |
746 | #gpio-cells = <2>; |
747 | gpio-controller; | |
748 | interrupt-controller; | |
749 | #interrupt-cells = <2>; | |
c2375821 | 750 | clocks = <&pioB_clk>; |
e4541ff2 JCPV |
751 | }; |
752 | ||
753 | pioC: gpio@fffff600 { | |
754 | compatible = "atmel,at91rm9200-gpio"; | |
755 | reg = <0xfffff600 0x200>; | |
5e8b3bc3 | 756 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
e4541ff2 JCPV |
757 | #gpio-cells = <2>; |
758 | gpio-controller; | |
759 | interrupt-controller; | |
760 | #interrupt-cells = <2>; | |
c2375821 | 761 | clocks = <&pioCDE_clk>; |
e4541ff2 JCPV |
762 | }; |
763 | ||
764 | pioD: gpio@fffff800 { | |
765 | compatible = "atmel,at91rm9200-gpio"; | |
766 | reg = <0xfffff800 0x200>; | |
5e8b3bc3 | 767 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
e4541ff2 JCPV |
768 | #gpio-cells = <2>; |
769 | gpio-controller; | |
770 | interrupt-controller; | |
771 | #interrupt-cells = <2>; | |
c2375821 | 772 | clocks = <&pioCDE_clk>; |
e4541ff2 JCPV |
773 | }; |
774 | ||
775 | pioE: gpio@fffffa00 { | |
776 | compatible = "atmel,at91rm9200-gpio"; | |
777 | reg = <0xfffffa00 0x200>; | |
5e8b3bc3 | 778 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
e4541ff2 JCPV |
779 | #gpio-cells = <2>; |
780 | gpio-controller; | |
781 | interrupt-controller; | |
782 | #interrupt-cells = <2>; | |
c2375821 | 783 | clocks = <&pioCDE_clk>; |
5314ec8e | 784 | }; |
4abb3677 JCPV |
785 | }; |
786 | ||
787 | dbgu: serial@ffffee00 { | |
8c07f664 | 788 | compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; |
4abb3677 | 789 | reg = <0xffffee00 0x200>; |
5e8b3bc3 | 790 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
ec6754a7 JCPV |
791 | pinctrl-names = "default"; |
792 | pinctrl-0 = <&pinctrl_dbgu>; | |
c2375821 AB |
793 | clocks = <&mck>; |
794 | clock-names = "usart"; | |
4abb3677 JCPV |
795 | status = "disabled"; |
796 | }; | |
797 | ||
798 | usart0: serial@fff8c000 { | |
799 | compatible = "atmel,at91sam9260-usart"; | |
800 | reg = <0xfff8c000 0x200>; | |
5e8b3bc3 | 801 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
4abb3677 JCPV |
802 | atmel,use-dma-rx; |
803 | atmel,use-dma-tx; | |
ec6754a7 | 804 | pinctrl-names = "default"; |
9e3129e9 | 805 | pinctrl-0 = <&pinctrl_usart0>; |
c2375821 AB |
806 | clocks = <&usart0_clk>; |
807 | clock-names = "usart"; | |
4abb3677 JCPV |
808 | status = "disabled"; |
809 | }; | |
810 | ||
811 | usart1: serial@fff90000 { | |
812 | compatible = "atmel,at91sam9260-usart"; | |
813 | reg = <0xfff90000 0x200>; | |
5e8b3bc3 | 814 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
4abb3677 JCPV |
815 | atmel,use-dma-rx; |
816 | atmel,use-dma-tx; | |
ec6754a7 | 817 | pinctrl-names = "default"; |
9e3129e9 | 818 | pinctrl-0 = <&pinctrl_usart1>; |
c2375821 AB |
819 | clocks = <&usart1_clk>; |
820 | clock-names = "usart"; | |
4abb3677 JCPV |
821 | status = "disabled"; |
822 | }; | |
823 | ||
824 | usart2: serial@fff94000 { | |
825 | compatible = "atmel,at91sam9260-usart"; | |
826 | reg = <0xfff94000 0x200>; | |
5e8b3bc3 | 827 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; |
4abb3677 JCPV |
828 | atmel,use-dma-rx; |
829 | atmel,use-dma-tx; | |
ec6754a7 | 830 | pinctrl-names = "default"; |
9e3129e9 | 831 | pinctrl-0 = <&pinctrl_usart2>; |
c2375821 AB |
832 | clocks = <&usart2_clk>; |
833 | clock-names = "usart"; | |
4abb3677 JCPV |
834 | status = "disabled"; |
835 | }; | |
836 | ||
099343c6 BS |
837 | ssc0: ssc@fff98000 { |
838 | compatible = "atmel,at91rm9200-ssc"; | |
839 | reg = <0xfff98000 0x4000>; | |
5e8b3bc3 | 840 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
544ae6b2 BS |
841 | pinctrl-names = "default"; |
842 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
c2375821 AB |
843 | clocks = <&ssc0_clk>; |
844 | clock-names = "pclk"; | |
315656bc | 845 | status = "disabled"; |
099343c6 BS |
846 | }; |
847 | ||
848 | ssc1: ssc@fff9c000 { | |
849 | compatible = "atmel,at91rm9200-ssc"; | |
850 | reg = <0xfff9c000 0x4000>; | |
5e8b3bc3 | 851 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; |
544ae6b2 BS |
852 | pinctrl-names = "default"; |
853 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | |
c2375821 AB |
854 | clocks = <&ssc1_clk>; |
855 | clock-names = "pclk"; | |
315656bc | 856 | status = "disabled"; |
099343c6 BS |
857 | }; |
858 | ||
c7f85be1 AS |
859 | ac97: sound@fffa0000 { |
860 | compatible = "atmel,at91sam9263-ac97c"; | |
861 | reg = <0xfffa0000 0x4000>; | |
862 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; | |
863 | pinctrl-names = "default"; | |
864 | pinctrl-0 = <&pinctrl_ac97>; | |
865 | clocks = <&ac97_clk>; | |
866 | clock-names = "ac97_clk"; | |
867 | status = "disabled"; | |
868 | }; | |
869 | ||
4abb3677 | 870 | macb0: ethernet@fffbc000 { |
9c348d45 | 871 | compatible = "cdns,at91sam9260-macb", "cdns,macb"; |
4abb3677 | 872 | reg = <0xfffbc000 0x100>; |
5e8b3bc3 | 873 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; |
d9b4fe83 JCPV |
874 | pinctrl-names = "default"; |
875 | pinctrl-0 = <&pinctrl_macb_rmii>; | |
c2375821 AB |
876 | clocks = <&macb0_clk>, <&macb0_clk>; |
877 | clock-names = "hclk", "pclk"; | |
4abb3677 JCPV |
878 | status = "disabled"; |
879 | }; | |
880 | ||
881 | usb1: gadget@fff78000 { | |
70a9beaa | 882 | compatible = "atmel,at91sam9263-udc"; |
4abb3677 | 883 | reg = <0xfff78000 0x4000>; |
5e8b3bc3 | 884 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; |
c2375821 AB |
885 | clocks = <&udc_clk>, <&udpck>; |
886 | clock-names = "pclk", "hclk"; | |
4abb3677 JCPV |
887 | status = "disabled"; |
888 | }; | |
05dcd361 LD |
889 | |
890 | i2c0: i2c@fff88000 { | |
821003ba | 891 | compatible = "atmel,at91sam9260-i2c"; |
05dcd361 | 892 | reg = <0xfff88000 0x100>; |
5e8b3bc3 | 893 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; |
05dcd361 LD |
894 | #address-cells = <1>; |
895 | #size-cells = <0>; | |
c2375821 | 896 | clocks = <&twi0_clk>; |
05dcd361 LD |
897 | status = "disabled"; |
898 | }; | |
9873137a LD |
899 | |
900 | mmc0: mmc@fff80000 { | |
901 | compatible = "atmel,hsmci"; | |
902 | reg = <0xfff80000 0x600>; | |
5e8b3bc3 | 903 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; |
b65e0fb3 | 904 | pinctrl-names = "default"; |
9873137a LD |
905 | #address-cells = <1>; |
906 | #size-cells = <0>; | |
c2375821 AB |
907 | clocks = <&mci0_clk>; |
908 | clock-names = "mci_clk"; | |
9873137a LD |
909 | status = "disabled"; |
910 | }; | |
911 | ||
912 | mmc1: mmc@fff84000 { | |
913 | compatible = "atmel,hsmci"; | |
914 | reg = <0xfff84000 0x600>; | |
5e8b3bc3 | 915 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; |
b65e0fb3 | 916 | pinctrl-names = "default"; |
9873137a LD |
917 | #address-cells = <1>; |
918 | #size-cells = <0>; | |
c2375821 AB |
919 | clocks = <&mci1_clk>; |
920 | clock-names = "mci_clk"; | |
9873137a LD |
921 | status = "disabled"; |
922 | }; | |
db5b0ae0 | 923 | |
7492e7ca FP |
924 | watchdog@fffffd40 { |
925 | compatible = "atmel,at91sam9260-wdt"; | |
926 | reg = <0xfffffd40 0x10>; | |
fe46aa67 | 927 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
53b0b378 | 928 | clocks = <&slow_xtal>; |
fe46aa67 BB |
929 | atmel,watchdog-type = "hardware"; |
930 | atmel,reset-type = "all"; | |
931 | atmel,dbg-halt; | |
7492e7ca FP |
932 | status = "disabled"; |
933 | }; | |
d50f88a0 RG |
934 | |
935 | spi0: spi@fffa4000 { | |
936 | #address-cells = <1>; | |
937 | #size-cells = <0>; | |
938 | compatible = "atmel,at91rm9200-spi"; | |
939 | reg = <0xfffa4000 0x200>; | |
5e8b3bc3 | 940 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
a68b728f WY |
941 | pinctrl-names = "default"; |
942 | pinctrl-0 = <&pinctrl_spi0>; | |
c2375821 AB |
943 | clocks = <&spi0_clk>; |
944 | clock-names = "spi_clk"; | |
d50f88a0 RG |
945 | status = "disabled"; |
946 | }; | |
947 | ||
948 | spi1: spi@fffa8000 { | |
949 | #address-cells = <1>; | |
950 | #size-cells = <0>; | |
951 | compatible = "atmel,at91rm9200-spi"; | |
952 | reg = <0xfffa8000 0x200>; | |
5e8b3bc3 | 953 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; |
a68b728f WY |
954 | pinctrl-names = "default"; |
955 | pinctrl-0 = <&pinctrl_spi1>; | |
c2375821 AB |
956 | clocks = <&spi1_clk>; |
957 | clock-names = "spi_clk"; | |
d50f88a0 RG |
958 | status = "disabled"; |
959 | }; | |
f3ab0527 BS |
960 | |
961 | pwm0: pwm@fffb8000 { | |
962 | compatible = "atmel,at91sam9rl-pwm"; | |
963 | reg = <0xfffb8000 0x300>; | |
964 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; | |
965 | #pwm-cells = <3>; | |
c2375821 AB |
966 | clocks = <&pwm_clk>; |
967 | clock-names = "pwm_clk"; | |
f3ab0527 BS |
968 | status = "disabled"; |
969 | }; | |
2667c6ad AS |
970 | |
971 | can: can@fffac000 { | |
972 | compatible = "atmel,at91sam9263-can"; | |
973 | reg = <0xfffac000 0x300>; | |
974 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; | |
975 | pinctrl-names = "default"; | |
976 | pinctrl-0 = <&pinctrl_can_rx_tx>; | |
977 | clocks = <&can_clk>; | |
978 | clock-names = "can_clk"; | |
9b5a0675 BB |
979 | }; |
980 | ||
981 | rtc@fffffd20 { | |
982 | compatible = "atmel,at91sam9260-rtt"; | |
983 | reg = <0xfffffd20 0x10>; | |
984 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
985 | clocks = <&slow_xtal>; | |
986 | status = "disabled"; | |
987 | }; | |
988 | ||
989 | rtc@fffffd50 { | |
990 | compatible = "atmel,at91sam9260-rtt"; | |
991 | reg = <0xfffffd50 0x10>; | |
992 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
993 | clocks = <&slow_xtal>; | |
2667c6ad AS |
994 | status = "disabled"; |
995 | }; | |
1ff3beca BB |
996 | |
997 | gpbr: syscon@fffffd60 { | |
998 | compatible = "atmel,at91sam9260-gpbr", "syscon"; | |
999 | reg = <0xfffffd60 0x50>; | |
1000 | status = "disabled"; | |
1001 | }; | |
4abb3677 JCPV |
1002 | }; |
1003 | ||
ed4ced0c | 1004 | fb0: fb@700000 { |
f8a0d793 JCPV |
1005 | compatible = "atmel,at91sam9263-lcdc"; |
1006 | reg = <0x00700000 0x1000>; | |
1007 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; | |
1008 | pinctrl-names = "default"; | |
1009 | pinctrl-0 = <&pinctrl_fb>; | |
55eb9c34 AS |
1010 | clocks = <&lcd_clk>, <&lcd_clk>; |
1011 | clock-names = "lcdc_clk", "hclk"; | |
f8a0d793 JCPV |
1012 | status = "disabled"; |
1013 | }; | |
1014 | ||
8dccafaa | 1015 | usb0: ohci@a00000 { |
4abb3677 JCPV |
1016 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
1017 | reg = <0x00a00000 0x100000>; | |
5e8b3bc3 | 1018 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; |
f8073708 BB |
1019 | clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; |
1020 | clock-names = "ohci_clk", "hclk", "uhpck"; | |
4abb3677 JCPV |
1021 | status = "disabled"; |
1022 | }; | |
d9c41bf3 BB |
1023 | |
1024 | ebi0: ebi@10000000 { | |
1025 | compatible = "atmel,at91sam9263-ebi0"; | |
1026 | #address-cells = <2>; | |
1027 | #size-cells = <1>; | |
1028 | atmel,smc = <&smc0>; | |
1029 | atmel,matrix = <&matrix>; | |
1030 | reg = <0x10000000 0x80000000>; | |
1031 | ranges = <0x0 0x0 0x10000000 0x10000000 | |
1032 | 0x1 0x0 0x20000000 0x10000000 | |
1033 | 0x2 0x0 0x30000000 0x10000000 | |
1034 | 0x3 0x0 0x40000000 0x10000000 | |
1035 | 0x4 0x0 0x50000000 0x10000000 | |
1036 | 0x5 0x0 0x60000000 0x10000000>; | |
1037 | clocks = <&mck>; | |
1038 | status = "disabled"; | |
1039 | ||
1040 | nand_controller0: nand-controller { | |
1041 | compatible = "atmel,at91sam9260-nand-controller"; | |
1042 | #address-cells = <2>; | |
1043 | #size-cells = <1>; | |
1044 | ranges; | |
1045 | status = "disabled"; | |
1046 | }; | |
1047 | }; | |
1048 | ||
1049 | ebi1: ebi@70000000 { | |
1050 | compatible = "atmel,at91sam9263-ebi1"; | |
1051 | #address-cells = <2>; | |
1052 | #size-cells = <1>; | |
1053 | atmel,smc = <&smc1>; | |
1054 | atmel,matrix = <&matrix>; | |
1055 | reg = <0x80000000 0x20000000>; | |
1056 | ranges = <0x0 0x0 0x80000000 0x10000000 | |
1057 | 0x1 0x0 0x90000000 0x10000000>; | |
1058 | clocks = <&mck>; | |
1059 | status = "disabled"; | |
1060 | ||
1061 | nand_controller1: nand-controller { | |
1062 | compatible = "atmel,at91sam9260-nand-controller"; | |
1063 | #address-cells = <2>; | |
1064 | #size-cells = <1>; | |
1065 | ranges; | |
1066 | status = "disabled"; | |
1067 | }; | |
1068 | }; | |
4abb3677 JCPV |
1069 | }; |
1070 | ||
e152e3f7 | 1071 | i2c-gpio-0 { |
4abb3677 | 1072 | compatible = "i2c-gpio"; |
92f8629b JCPV |
1073 | gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ |
1074 | &pioB 5 GPIO_ACTIVE_HIGH /* scl */ | |
4abb3677 JCPV |
1075 | >; |
1076 | i2c-gpio,sda-open-drain; | |
1077 | i2c-gpio,scl-open-drain; | |
1078 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
1079 | #address-cells = <1>; | |
1080 | #size-cells = <0>; | |
1081 | status = "disabled"; | |
1082 | }; | |
1083 | }; |