[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / at91sam9g45.dtsi

/*
 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
 *                    applies to AT91SAM9G45, AT91SAM9M10,
 *                    AT91SAM9G46, AT91SAM9M11 SoC
 *
 *  Copyright (C) 2011 Atmel,
 *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
 *
 * Licensed under GPLv2 or later.
 */

/include/ "skeleton.dtsi"

/ {
	model = "Atmel AT91SAM9G45 family SoC";
	compatible = "atmel,at91sam9g45";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &dbgu;
		serial1 = &usart0;
		serial2 = &usart1;
		serial3 = &usart2;
		serial4 = &usart3;
		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		gpio4 = &pioE;
		tcb0 = &tcb0;
		tcb1 = &tcb1;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		ssc0 = &ssc0;
		ssc1 = &ssc1;
	};
	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
		};
	};

	memory {
		reg = <0x70000000 0x10000000>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			aic: interrupt-controller@fffff000 {
				#interrupt-cells = <3>;
				compatible = "atmel,at91rm9200-aic";
				interrupt-controller;
				reg = <0xfffff000 0x200>;
				atmel,external-irqs = <31>;
			};

			ramc0: ramc@ffffe400 {
				compatible = "atmel,at91sam9g45-ddramc";
				reg = <0xffffe400 0x200
				       0xffffe600 0x200>;
			};

			pmc: pmc@fffffc00 {
				compatible = "atmel,at91rm9200-pmc";
				reg = <0xfffffc00 0x100>;
			};

			rstc@fffffd00 {
				compatible = "atmel,at91sam9g45-rstc";
				reg = <0xfffffd00 0x10>;
			};

			pit: timer@fffffd30 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfffffd30 0xf>;
				interrupts = <1 4 7>;
			};


			shdwc@fffffd10 {
				compatible = "atmel,at91sam9rl-shdwc";
				reg = <0xfffffd10 0x10>;
			};

			tcb0: timer@fff7c000 {
				compatible = "atmel,at91rm9200-tcb";
				reg = <0xfff7c000 0x100>;
				interrupts = <18 4 0>;
			};

			tcb1: timer@fffd4000 {
				compatible = "atmel,at91rm9200-tcb";
				reg = <0xfffd4000 0x100>;
				interrupts = <18 4 0>;
			};

			dma: dma-controller@ffffec00 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffec00 0x200>;
				interrupts = <21 4 0>;
				#dma-cells = <2>;
			};

			pinctrl@fffff200 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
				ranges = <0xfffff200 0xfffff200 0xa00>;

				atmel,mux-mask = <
				      /*    A         B     */
				       0xffffffff 0xffc003ff  /* pioA */
				       0xffffffff 0x800f8f00  /* pioB */
				       0xffffffff 0x00000e00  /* pioC */
				       0xffffffff 0xff0c1381  /* pioD */
				       0xffffffff 0x81ffff81  /* pioE */
				      >;

				/* shared pinctrl settings */
				dbgu {
					pinctrl_dbgu: dbgu-0 {
						atmel,pins =
							<1 12 0x1 0x0	/* PB12 periph A */
							 1 13 0x1 0x0>;	/* PB13 periph A */
					};
				};

				usart0 {
					pinctrl_usart0: usart0-0 {
						atmel,pins =
							<1 19 0x1 0x1	/* PB19 periph A with pullup */
							 1 18 0x1 0x0>;	/* PB18 periph A */
					};

					pinctrl_usart0_rts: usart0_rts-0 {
						atmel,pins =
							<1 17 0x2 0x0>;	/* PB17 periph B */
					};

					pinctrl_usart0_cts: usart0_cts-0 {
						atmel,pins =
							<1 15 0x2 0x0>;	/* PB15 periph B */
					};
				};

				uart1 {
					pinctrl_usart1: usart1-0 {
						atmel,pins =
							<1 4 0x1 0x1	/* PB4 periph A with pullup */
							 1 5 0x1 0x0>;	/* PB5 periph A */
					};

					pinctrl_usart1_rts: usart1_rts-0 {
						atmel,pins =
							<3 16 0x1 0x0>;	/* PD16 periph A */
					};

					pinctrl_usart1_cts: usart1_cts-0 {
						atmel,pins =
							<3 17 0x1 0x0>;	/* PD17 periph A */
					};
				};

				usart2 {
					pinctrl_usart2: usart2-0 {
						atmel,pins =
							<1 6 0x1 0x1	/* PB6 periph A with pullup */
							 1 7 0x1 0x0>;	/* PB7 periph A */
					};

					pinctrl_usart2_rts: usart2_rts-0 {
						atmel,pins =
							<2 9 0x2 0x0>;	/* PC9 periph B */
					};

					pinctrl_usart2_cts: usart2_cts-0 {
						atmel,pins =
							<2 11 0x2 0x0>;	/* PC11 periph B */
					};
				};

				usart3 {
					pinctrl_usart3: usart3-0 {
						atmel,pins =
							<1 8 0x1 0x1	/* PB9 periph A with pullup */
							 1 9 0x1 0x0>;	/* PB8 periph A */
					};

					pinctrl_usart3_rts: usart3_rts-0 {
						atmel,pins =
							<0 23 0x2 0x0>;	/* PA23 periph B */
					};

					pinctrl_usart3_cts: usart3_cts-0 {
						atmel,pins =
							<0 24 0x2 0x0>;	/* PA24 periph B */
					};
				};

				nand {
					pinctrl_nand: nand-0 {
						atmel,pins =
							<2 8 0x0 0x1	/* PC8 gpio RDY pin pull_up*/
							 2 14 0x0 0x1>;	/* PC14 gpio enable pin pull_up */
					};
				};

				macb {
					pinctrl_macb_rmii: macb_rmii-0 {
						atmel,pins =
							<0 10 0x1 0x0	/* PA10 periph A */
							 0 11 0x1 0x0	/* PA11 periph A */
							 0 12 0x1 0x0	/* PA12 periph A */
							 0 13 0x1 0x0	/* PA13 periph A */
							 0 14 0x1 0x0	/* PA14 periph A */
							 0 15 0x1 0x0	/* PA15 periph A */
							 0 16 0x1 0x0	/* PA16 periph A */
							 0 17 0x1 0x0	/* PA17 periph A */
							 0 18 0x1 0x0	/* PA18 periph A */
							 0 19 0x1 0x0>;	/* PA19 periph A */
					};

					pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
						atmel,pins =
							<0 6 0x2 0x0	/* PA6 periph B */
							 0 7 0x2 0x0	/* PA7 periph B */
							 0 8 0x2 0x0	/* PA8 periph B */
							 0 9 0x2 0x0	/* PA9 periph B */
							 0 27 0x2 0x0	/* PA27 periph B */
							 0 28 0x2 0x0	/* PA28 periph B */
							 0 29 0x2 0x0	/* PA29 periph B */
							 0 30 0x2 0x0>;	/* PA30 periph B */
					};
				};

				mmc0 {
					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
						atmel,pins =
							<0 0 0x1 0x0	/* PA0 periph A */
							 0 1 0x1 0x1	/* PA1 periph A with pullup */
							 0 2 0x1 0x1>;	/* PA2 periph A with pullup */
					};

					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
						atmel,pins =
							<0 3 0x1 0x1	/* PA3 periph A with pullup */
							 0 4 0x1 0x1	/* PA4 periph A with pullup */
							 0 5 0x1 0x1>;	/* PA5 periph A with pullup */
					};

					pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
						atmel,pins =
							<0 6 0x1 0x1	/* PA6 periph A with pullup */
							 0 7 0x1 0x1	/* PA7 periph A with pullup */
							 0 8 0x1 0x1	/* PA8 periph A with pullup */
							 0 9 0x1 0x1>;	/* PA9 periph A with pullup */
					};
				};

				mmc1 {
					pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
						atmel,pins =
							<0 31 0x1 0x0	/* PA31 periph A */
							 0 22 0x1 0x1	/* PA22 periph A with pullup */
							 0 23 0x1 0x1>;	/* PA23 periph A with pullup */
					};

					pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
						atmel,pins =
							<0 24 0x1 0x1	/* PA24 periph A with pullup */
							 0 25 0x1 0x1	/* PA25 periph A with pullup */
							 0 26 0x1 0x1>;	/* PA26 periph A with pullup */
					};

					pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
						atmel,pins =
							<0 27 0x1 0x1	/* PA27 periph A with pullup */
							 0 28 0x1 0x1	/* PA28 periph A with pullup */
							 0 29 0x1 0x1	/* PA29 periph A with pullup */
							 0 20 0x1 0x1>;	/* PA30 periph A with pullup */
					};
				};

				ssc0 {
					pinctrl_ssc0_tx: ssc0_tx-0 {
						atmel,pins =
							<3 0 0x1 0x0	/* PD0 periph A */
							 3 1 0x1 0x0	/* PD1 periph A */
							 3 2 0x1 0x0>;	/* PD2 periph A */
					};

					pinctrl_ssc0_rx: ssc0_rx-0 {
						atmel,pins =
							<3 3 0x1 0x0	/* PD3 periph A */
							 3 4 0x1 0x0	/* PD4 periph A */
							 3 5 0x1 0x0>;	/* PD5 periph A */
					};
				};

				ssc1 {
					pinctrl_ssc1_tx: ssc1_tx-0 {
						atmel,pins =
							<3 10 0x1 0x0	/* PD10 periph A */
							 3 11 0x1 0x0	/* PD11 periph A */
							 3 12 0x1 0x0>;	/* PD12 periph A */
					};

					pinctrl_ssc1_rx: ssc1_rx-0 {
						atmel,pins =
							<3 13 0x1 0x0	/* PD13 periph A */
							 3 14 0x1 0x0	/* PD14 periph A */
							 3 15 0x1 0x0>;	/* PD15 periph A */
					};
				};

				spi0 {
					pinctrl_spi0: spi0-0 {
						atmel,pins =
							<1 0 0x1 0x0	/* PB0 periph A SPI0_MISO pin */
							 1 1 0x1 0x0	/* PB1 periph A SPI0_MOSI pin */
							 1 2 0x1 0x0>;	/* PB2 periph A SPI0_SPCK pin */
					};
				};

				spi1 {
					pinctrl_spi1: spi1-0 {
						atmel,pins =
							<1 14 0x1 0x0	/* PB14 periph A SPI1_MISO pin */
							 1 15 0x1 0x0	/* PB15 periph A SPI1_MOSI pin */
							 1 16 0x1 0x0>;	/* PB16 periph A SPI1_SPCK pin */
					};
				};

				pioA: gpio@fffff200 {
					compatible = "atmel,at91rm9200-gpio";
					reg = <0xfffff200 0x200>;
					interrupts = <2 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioB: gpio@fffff400 {
					compatible = "atmel,at91rm9200-gpio";
					reg = <0xfffff400 0x200>;
					interrupts = <3 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioC: gpio@fffff600 {
					compatible = "atmel,at91rm9200-gpio";
					reg = <0xfffff600 0x200>;
					interrupts = <4 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioD: gpio@fffff800 {
					compatible = "atmel,at91rm9200-gpio";
					reg = <0xfffff800 0x200>;
					interrupts = <5 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioE: gpio@fffffa00 {
					compatible = "atmel,at91rm9200-gpio";
					reg = <0xfffffa00 0x200>;
					interrupts = <5 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};
			};

			dbgu: serial@ffffee00 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xffffee00 0x200>;
				interrupts = <1 4 7>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_dbgu>;
				status = "disabled";
			};

			usart0: serial@fff8c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfff8c000 0x200>;
				interrupts = <7 4 5>;
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart0>;
				status = "disabled";
			};

			usart1: serial@fff90000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfff90000 0x200>;
				interrupts = <8 4 5>;
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart1>;
				status = "disabled";
			};

			usart2: serial@fff94000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfff94000 0x200>;
				interrupts = <9 4 5>;
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart2>;
				status = "disabled";
			};

			usart3: serial@fff98000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfff98000 0x200>;
				interrupts = <10 4 5>;
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart3>;
				status = "disabled";
			};

			macb0: ethernet@fffbc000 {
				compatible = "cdns,at32ap7000-macb", "cdns,macb";
				reg = <0xfffbc000 0x100>;
				interrupts = <25 4 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb_rmii>;
				status = "disabled";
			};

			i2c0: i2c@fff84000 {
				compatible = "atmel,at91sam9g10-i2c";
				reg = <0xfff84000 0x100>;
				interrupts = <12 4 6>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c1: i2c@fff88000 {
				compatible = "atmel,at91sam9g10-i2c";
				reg = <0xfff88000 0x100>;
				interrupts = <13 4 6>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			ssc0: ssc@fff9c000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xfff9c000 0x4000>;
				interrupts = <16 4 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
				status = "disabled";
			};

			ssc1: ssc@fffa0000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xfffa0000 0x4000>;
				interrupts = <17 4 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
				status = "disabled";
			};

			adc0: adc@fffb0000 {
				compatible = "atmel,at91sam9260-adc";
				reg = <0xfffb0000 0x100>;
				interrupts = <20 4 0>;
				atmel,adc-use-external-triggers;
				atmel,adc-channels-used = <0xff>;
				atmel,adc-vref = <3300>;
				atmel,adc-num-channels = <8>;
				atmel,adc-startup-time = <40>;
				atmel,adc-channel-base = <0x30>;
				atmel,adc-drdy-mask = <0x10000>;
				atmel,adc-status-register = <0x1c>;
				atmel,adc-trigger-register = <0x08>;
				atmel,adc-res = <8 10>;
				atmel,adc-res-names = "lowres", "highres";
				atmel,adc-use-res = "highres";

				trigger@0 {
					trigger-name = "external-rising";
					trigger-value = <0x1>;
					trigger-external;
				};
				trigger@1 {
					trigger-name = "external-falling";
					trigger-value = <0x2>;
					trigger-external;
				};

				trigger@2 {
					trigger-name = "external-any";
					trigger-value = <0x3>;
					trigger-external;
				};

				trigger@3 {
					trigger-name = "continuous";
					trigger-value = <0x6>;
				};
			};

			mmc0: mmc@fff80000 {
				compatible = "atmel,hsmci";
				reg = <0xfff80000 0x600>;
				interrupts = <11 4 0>;
				dmas = <&dma 1 0>;
				dma-names = "rxtx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			mmc1: mmc@fffd0000 {
				compatible = "atmel,hsmci";
				reg = <0xfffd0000 0x600>;
				interrupts = <29 4 0>;
				dmas = <&dma 1 13>;
				dma-names = "rxtx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			watchdog@fffffd40 {
				compatible = "atmel,at91sam9260-wdt";
				reg = <0xfffffd40 0x10>;
				status = "disabled";
			};

			spi0: spi@fffa4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfffa4000 0x200>;
				interrupts = <14 4 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi0>;
				status = "disabled";
			};

			spi1: spi@fffa8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfffa8000 0x200>;
				interrupts = <15 4 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi1>;
				status = "disabled";
			};
		};

		nand0: nand@40000000 {
			compatible = "atmel,at91rm9200-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40000000 0x10000000
			       0xffffe200 0x200
			      >;
			atmel,nand-addr-offset = <21>;
			atmel,nand-cmd-offset = <22>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			gpios = <&pioC 8 0
				 &pioC 14 0
				 0
				>;
			status = "disabled";
		};

		usb0: ohci@00700000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00700000 0x100000>;
			interrupts = <22 4 2>;
			status = "disabled";
		};

		usb1: ehci@00800000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00800000 0x100000>;
			interrupts = <22 4 2>;
			status = "disabled";
		};
	};

	i2c@0 {
		compatible = "i2c-gpio";
		gpios = <&pioA 20 0 /* sda */
			 &pioA 21 0 /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <5>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};
};
Commit	Line	Data
49fe2ba3 NF	1	/*
	2	* at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
	3	* applies to AT91SAM9G45, AT91SAM9M10,
	4	* AT91SAM9G46, AT91SAM9M11 SoC
	5	*
	6	* Copyright (C) 2011 Atmel,
	7	* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
	8	*
	9	* Licensed under GPLv2 or later.
	10	*/
	11
	12	/include/ "skeleton.dtsi"
	13
	14	/ {
	15	model = "Atmel AT91SAM9G45 family SoC";
	16	compatible = "atmel,at91sam9g45";
	17	interrupt-parent = <&aic>;
	18
	19	aliases {
	20	serial0 = &dbgu;
	21	serial1 = &usart0;
	22	serial2 = &usart1;
	23	serial3 = &usart2;
	24	serial4 = &usart3;
21f81872 NF	25	gpio0 = &pioA;
	26	gpio1 = &pioB;
	27	gpio2 = &pioC;
	28	gpio3 = &pioD;
	29	gpio4 = &pioE;
3a61a5da NF	30	tcb0 = &tcb0;
3a61a5da NF	31	tcb1 = &tcb1;
05dcd361 LD	32	i2c0 = &i2c0;
05dcd361 LD	33	i2c1 = &i2c1;
099343c6 BS	34	ssc0 = &ssc0;
099343c6 BS	35	ssc1 = &ssc1;
49fe2ba3 NF	36	};
49fe2ba3 NF	37	cpus {
e757a6ee LP	38	#address-cells = <0>;
	39	#size-cells = <0>;
	40
	41	cpu {
	42	compatible = "arm,arm926ej-s";
	43	device_type = "cpu";
49fe2ba3 NF	44	};
	45	};
	46
dcce6ce8	47	memory {
49fe2ba3 NF	48	reg = <0x70000000 0x10000000>;
	49	};
	50
	51	ahb {
	52	compatible = "simple-bus";
	53	#address-cells = <1>;
	54	#size-cells = <1>;
	55	ranges;
	56
	57	apb {
	58	compatible = "simple-bus";
	59	#address-cells = <1>;
	60	#size-cells = <1>;
	61	ranges;
	62
	63	aic: interrupt-controller@fffff000 {
f8a073ee	64	#interrupt-cells = <3>;
49fe2ba3 NF	65	compatible = "atmel,at91rm9200-aic";
49fe2ba3 NF	66	interrupt-controller;
49fe2ba3	67	reg = <0xfffff000 0x200>;
c6573943	68	atmel,external-irqs = <31>;
49fe2ba3 NF	69	};
49fe2ba3 NF	70
a7776ec6 JCPV	71	ramc0: ramc@ffffe400 {
	72	compatible = "atmel,at91sam9g45-ddramc";
	73	reg = <0xffffe400 0x200
	74	0xffffe600 0x200>;
	75	};
	76
eb5e76ff JCPV	77	pmc: pmc@fffffc00 {
	78	compatible = "atmel,at91rm9200-pmc";
	79	reg = <0xfffffc00 0x100>;
	80	};
	81
c8082d34 JCPV	82	rstc@fffffd00 {
	83	compatible = "atmel,at91sam9g45-rstc";
	84	reg = <0xfffffd00 0x10>;
	85	};
	86
23fa648f JCPV	87	pit: timer@fffffd30 {
	88	compatible = "atmel,at91sam9260-pit";
	89	reg = <0xfffffd30 0xf>;
f8a073ee	90	interrupts = <1 4 7>;
23fa648f JCPV	91	};
23fa648f JCPV	92
3a61a5da	93
82015c4e JCPV	94	shdwc@fffffd10 {
	95	compatible = "atmel,at91sam9rl-shdwc";
	96	reg = <0xfffffd10 0x10>;
	97	};
	98
3a61a5da NF	99	tcb0: timer@fff7c000 {
	100	compatible = "atmel,at91rm9200-tcb";
	101	reg = <0xfff7c000 0x100>;
f8a073ee	102	interrupts = <18 4 0>;
3a61a5da NF	103	};
	104
	105	tcb1: timer@fffd4000 {
	106	compatible = "atmel,at91rm9200-tcb";
	107	reg = <0xfffd4000 0x100>;
f8a073ee	108	interrupts = <18 4 0>;
3a61a5da NF	109	};
3a61a5da NF	110
49fe2ba3 NF	111	dma: dma-controller@ffffec00 {
	112	compatible = "atmel,at91sam9g45-dma";
	113	reg = <0xffffec00 0x200>;
f8a073ee	114	interrupts = <21 4 0>;
980ce7d9	115	#dma-cells = <2>;
49fe2ba3 NF	116	};
49fe2ba3 NF	117
e4541ff2 JCPV	118	pinctrl@fffff200 {
	119	#address-cells = <1>;
	120	#size-cells = <1>;
	121	compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
	122	ranges = <0xfffff200 0xfffff200 0xa00>;
	123
5314ec8e JCPV	124	atmel,mux-mask = <
	125	/* A B */
	126	0xffffffff 0xffc003ff /* pioA */
	127	0xffffffff 0x800f8f00 /* pioB */
	128	0xffffffff 0x00000e00 /* pioC */
	129	0xffffffff 0xff0c1381 /* pioD */
	130	0xffffffff 0x81ffff81 /* pioE */
	131	>;
	132
	133	/* shared pinctrl settings */
ec6754a7 JCPV	134	dbgu {
	135	pinctrl_dbgu: dbgu-0 {
	136	atmel,pins =
	137	<1 12 0x1 0x0 /* PB12 periph A */
	138	1 13 0x1 0x0>; /* PB13 periph A */
	139	};
	140	};
	141
9e3129e9 JCPV	142	usart0 {
9e3129e9 JCPV	143	pinctrl_usart0: usart0-0 {
ec6754a7 JCPV	144	atmel,pins =
	145	<1 19 0x1 0x1 /* PB19 periph A with pullup */
	146	1 18 0x1 0x0>; /* PB18 periph A */
	147	};
	148
c58c0c5a	149	pinctrl_usart0_rts: usart0_rts-0 {
ec6754a7	150	atmel,pins =
c58c0c5a JCPV	151	<1 17 0x2 0x0>; /* PB17 periph B */
	152	};
	153
	154	pinctrl_usart0_cts: usart0_cts-0 {
	155	atmel,pins =
	156	<1 15 0x2 0x0>; /* PB15 periph B */
ec6754a7 JCPV	157	};
	158	};
	159
	160	uart1 {
9e3129e9	161	pinctrl_usart1: usart1-0 {
ec6754a7 JCPV	162	atmel,pins =
	163	<1 4 0x1 0x1 /* PB4 periph A with pullup */
	164	1 5 0x1 0x0>; /* PB5 periph A */
	165	};
	166
c58c0c5a JCPV	167	pinctrl_usart1_rts: usart1_rts-0 {
	168	atmel,pins =
	169	<3 16 0x1 0x0>; /* PD16 periph A */
	170	};
	171
	172	pinctrl_usart1_cts: usart1_cts-0 {
ec6754a7	173	atmel,pins =
c58c0c5a	174	<3 17 0x1 0x0>; /* PD17 periph A */
ec6754a7 JCPV	175	};
	176	};
	177
9e3129e9 JCPV	178	usart2 {
9e3129e9 JCPV	179	pinctrl_usart2: usart2-0 {
ec6754a7 JCPV	180	atmel,pins =
	181	<1 6 0x1 0x1 /* PB6 periph A with pullup */
	182	1 7 0x1 0x0>; /* PB7 periph A */
	183	};
	184
c58c0c5a	185	pinctrl_usart2_rts: usart2_rts-0 {
ec6754a7	186	atmel,pins =
c58c0c5a JCPV	187	<2 9 0x2 0x0>; /* PC9 periph B */
	188	};
	189
	190	pinctrl_usart2_cts: usart2_cts-0 {
	191	atmel,pins =
	192	<2 11 0x2 0x0>; /* PC11 periph B */
ec6754a7 JCPV	193	};
	194	};
	195
9e3129e9 JCPV	196	usart3 {
9e3129e9 JCPV	197	pinctrl_usart3: usart3-0 {
ec6754a7 JCPV	198	atmel,pins =
	199	<1 8 0x1 0x1 /* PB9 periph A with pullup */
	200	1 9 0x1 0x0>; /* PB8 periph A */
	201	};
	202
c58c0c5a JCPV	203	pinctrl_usart3_rts: usart3_rts-0 {
	204	atmel,pins =
	205	<0 23 0x2 0x0>; /* PA23 periph B */
	206	};
	207
	208	pinctrl_usart3_cts: usart3_cts-0 {
ec6754a7	209	atmel,pins =
c58c0c5a	210	<0 24 0x2 0x0>; /* PA24 periph B */
ec6754a7 JCPV	211	};
ec6754a7 JCPV	212	};
5314ec8e	213
7a38d450 JCPV	214	nand {
	215	pinctrl_nand: nand-0 {
	216	atmel,pins =
	217	<2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
	218	2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
	219	};
	220	};
	221
d9b4fe83 JCPV	222	macb {
	223	pinctrl_macb_rmii: macb_rmii-0 {
	224	atmel,pins =
	225	<0 10 0x1 0x0 /* PA10 periph A */
	226	0 11 0x1 0x0 /* PA11 periph A */
	227	0 12 0x1 0x0 /* PA12 periph A */
	228	0 13 0x1 0x0 /* PA13 periph A */
	229	0 14 0x1 0x0 /* PA14 periph A */
	230	0 15 0x1 0x0 /* PA15 periph A */
	231	0 16 0x1 0x0 /* PA16 periph A */
	232	0 17 0x1 0x0 /* PA17 periph A */
	233	0 18 0x1 0x0 /* PA18 periph A */
	234	0 19 0x1 0x0>; /* PA19 periph A */
	235	};
	236
	237	pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
	238	atmel,pins =
	239	<0 6 0x2 0x0 /* PA6 periph B */
	240	0 7 0x2 0x0 /* PA7 periph B */
	241	0 8 0x2 0x0 /* PA8 periph B */
	242	0 9 0x2 0x0 /* PA9 periph B */
	243	0 27 0x2 0x0 /* PA27 periph B */
	244	0 28 0x2 0x0 /* PA28 periph B */
	245	0 29 0x2 0x0 /* PA29 periph B */
	246	0 30 0x2 0x0>; /* PA30 periph B */
	247	};
	248	};
	249
d4fe9ac7 JCPV	250	mmc0 {
	251	pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
	252	atmel,pins =
	253	<0 0 0x1 0x0 /* PA0 periph A */
	254	0 1 0x1 0x1 /* PA1 periph A with pullup */
	255	0 2 0x1 0x1>; /* PA2 periph A with pullup */
	256	};
	257
	258	pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
	259	atmel,pins =
	260	<0 3 0x1 0x1 /* PA3 periph A with pullup */
	261	0 4 0x1 0x1 /* PA4 periph A with pullup */
	262	0 5 0x1 0x1>; /* PA5 periph A with pullup */
	263	};
	264
	265	pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
	266	atmel,pins =
	267	<0 6 0x1 0x1 /* PA6 periph A with pullup */
	268	0 7 0x1 0x1 /* PA7 periph A with pullup */
	269	0 8 0x1 0x1 /* PA8 periph A with pullup */
	270	0 9 0x1 0x1>; /* PA9 periph A with pullup */
	271	};
	272	};
	273
	274	mmc1 {
	275	pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
	276	atmel,pins =
	277	<0 31 0x1 0x0 /* PA31 periph A */
	278	0 22 0x1 0x1 /* PA22 periph A with pullup */
	279	0 23 0x1 0x1>; /* PA23 periph A with pullup */
	280	};
	281
	282	pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
	283	atmel,pins =
	284	<0 24 0x1 0x1 /* PA24 periph A with pullup */
	285	0 25 0x1 0x1 /* PA25 periph A with pullup */
	286	0 26 0x1 0x1>; /* PA26 periph A with pullup */
	287	};
	288
	289	pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
	290	atmel,pins =
	291	<0 27 0x1 0x1 /* PA27 periph A with pullup */
	292	0 28 0x1 0x1 /* PA28 periph A with pullup */
	293	0 29 0x1 0x1 /* PA29 periph A with pullup */
	294	0 20 0x1 0x1>; /* PA30 periph A with pullup */
	295	};
	296	};
	297
544ae6b2 BS	298	ssc0 {
	299	pinctrl_ssc0_tx: ssc0_tx-0 {
	300	atmel,pins =
	301	<3 0 0x1 0x0 /* PD0 periph A */
	302	3 1 0x1 0x0 /* PD1 periph A */
	303	3 2 0x1 0x0>; /* PD2 periph A */
	304	};
	305
	306	pinctrl_ssc0_rx: ssc0_rx-0 {
	307	atmel,pins =
	308	<3 3 0x1 0x0 /* PD3 periph A */
	309	3 4 0x1 0x0 /* PD4 periph A */
	310	3 5 0x1 0x0>; /* PD5 periph A */
	311	};
	312	};
	313
	314	ssc1 {
	315	pinctrl_ssc1_tx: ssc1_tx-0 {
	316	atmel,pins =
	317	<3 10 0x1 0x0 /* PD10 periph A */
	318	3 11 0x1 0x0 /* PD11 periph A */
	319	3 12 0x1 0x0>; /* PD12 periph A */
	320	};
	321
	322	pinctrl_ssc1_rx: ssc1_rx-0 {
	323	atmel,pins =
	324	<3 13 0x1 0x0 /* PD13 periph A */
	325	3 14 0x1 0x0 /* PD14 periph A */
	326	3 15 0x1 0x0>; /* PD15 periph A */
	327	};
	328	};
	329
a68b728f WY	330	spi0 {
	331	pinctrl_spi0: spi0-0 {
	332	atmel,pins =
	333	<1 0 0x1 0x0 /* PB0 periph A SPI0_MISO pin */
	334	1 1 0x1 0x0 /* PB1 periph A SPI0_MOSI pin */
	335	1 2 0x1 0x0>; /* PB2 periph A SPI0_SPCK pin */
	336	};
	337	};
	338
	339	spi1 {
	340	pinctrl_spi1: spi1-0 {
	341	atmel,pins =
	342	<1 14 0x1 0x0 /* PB14 periph A SPI1_MISO pin */
	343	1 15 0x1 0x0 /* PB15 periph A SPI1_MOSI pin */
	344	1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */
	345	};
	346	};
	347
e4541ff2 JCPV	348	pioA: gpio@fffff200 {
	349	compatible = "atmel,at91rm9200-gpio";
	350	reg = <0xfffff200 0x200>;
	351	interrupts = <2 4 1>;
	352	#gpio-cells = <2>;
	353	gpio-controller;
	354	interrupt-controller;
	355	#interrupt-cells = <2>;
	356	};
	357
	358	pioB: gpio@fffff400 {
	359	compatible = "atmel,at91rm9200-gpio";
	360	reg = <0xfffff400 0x200>;
	361	interrupts = <3 4 1>;
	362	#gpio-cells = <2>;
	363	gpio-controller;
	364	interrupt-controller;
	365	#interrupt-cells = <2>;
	366	};
	367
	368	pioC: gpio@fffff600 {
	369	compatible = "atmel,at91rm9200-gpio";
	370	reg = <0xfffff600 0x200>;
	371	interrupts = <4 4 1>;
	372	#gpio-cells = <2>;
	373	gpio-controller;
	374	interrupt-controller;
	375	#interrupt-cells = <2>;
	376	};
	377
	378	pioD: gpio@fffff800 {
	379	compatible = "atmel,at91rm9200-gpio";
	380	reg = <0xfffff800 0x200>;
	381	interrupts = <5 4 1>;
	382	#gpio-cells = <2>;
	383	gpio-controller;
	384	interrupt-controller;
	385	#interrupt-cells = <2>;
	386	};
	387
	388	pioE: gpio@fffffa00 {
	389	compatible = "atmel,at91rm9200-gpio";
	390	reg = <0xfffffa00 0x200>;
	391	interrupts = <5 4 1>;
	392	#gpio-cells = <2>;
	393	gpio-controller;
	394	interrupt-controller;
	395	#interrupt-cells = <2>;
	396	};
21f81872 NF	397	};
21f81872 NF	398
49fe2ba3 NF	399	dbgu: serial@ffffee00 {
	400	compatible = "atmel,at91sam9260-usart";
	401	reg = <0xffffee00 0x200>;
f8a073ee	402	interrupts = <1 4 7>;
ec6754a7 JCPV	403	pinctrl-names = "default";
ec6754a7 JCPV	404	pinctrl-0 = <&pinctrl_dbgu>;
49fe2ba3 NF	405	status = "disabled";
	406	};
	407
	408	usart0: serial@fff8c000 {
	409	compatible = "atmel,at91sam9260-usart";
	410	reg = <0xfff8c000 0x200>;
f8a073ee	411	interrupts = <7 4 5>;
49fe2ba3 NF	412	atmel,use-dma-rx;
49fe2ba3 NF	413	atmel,use-dma-tx;
ec6754a7	414	pinctrl-names = "default";
9e3129e9	415	pinctrl-0 = <&pinctrl_usart0>;
49fe2ba3 NF	416	status = "disabled";
	417	};
	418
	419	usart1: serial@fff90000 {
	420	compatible = "atmel,at91sam9260-usart";
	421	reg = <0xfff90000 0x200>;
f8a073ee	422	interrupts = <8 4 5>;
49fe2ba3 NF	423	atmel,use-dma-rx;
49fe2ba3 NF	424	atmel,use-dma-tx;
ec6754a7	425	pinctrl-names = "default";
9e3129e9	426	pinctrl-0 = <&pinctrl_usart1>;
49fe2ba3 NF	427	status = "disabled";
	428	};
	429
	430	usart2: serial@fff94000 {
	431	compatible = "atmel,at91sam9260-usart";
	432	reg = <0xfff94000 0x200>;
f8a073ee	433	interrupts = <9 4 5>;
49fe2ba3 NF	434	atmel,use-dma-rx;
49fe2ba3 NF	435	atmel,use-dma-tx;
ec6754a7	436	pinctrl-names = "default";
9e3129e9	437	pinctrl-0 = <&pinctrl_usart2>;
49fe2ba3 NF	438	status = "disabled";
	439	};
	440
	441	usart3: serial@fff98000 {
	442	compatible = "atmel,at91sam9260-usart";
	443	reg = <0xfff98000 0x200>;
f8a073ee	444	interrupts = <10 4 5>;
49fe2ba3 NF	445	atmel,use-dma-rx;
49fe2ba3 NF	446	atmel,use-dma-tx;
ec6754a7	447	pinctrl-names = "default";
9e3129e9	448	pinctrl-0 = <&pinctrl_usart3>;
49fe2ba3 NF	449	status = "disabled";
49fe2ba3 NF	450	};
0d4f99d8 NF	451
	452	macb0: ethernet@fffbc000 {
	453	compatible = "cdns,at32ap7000-macb", "cdns,macb";
	454	reg = <0xfffbc000 0x100>;
f8a073ee	455	interrupts = <25 4 3>;
d9b4fe83 JCPV	456	pinctrl-names = "default";
d9b4fe83 JCPV	457	pinctrl-0 = <&pinctrl_macb_rmii>;
0d4f99d8 NF	458	status = "disabled";
0d4f99d8 NF	459	};
93b298ba	460
05dcd361 LD	461	i2c0: i2c@fff84000 {
	462	compatible = "atmel,at91sam9g10-i2c";
	463	reg = <0xfff84000 0x100>;
	464	interrupts = <12 4 6>;
	465	#address-cells = <1>;
	466	#size-cells = <0>;
	467	status = "disabled";
	468	};
	469
	470	i2c1: i2c@fff88000 {
	471	compatible = "atmel,at91sam9g10-i2c";
	472	reg = <0xfff88000 0x100>;
	473	interrupts = <13 4 6>;
	474	#address-cells = <1>;
	475	#size-cells = <0>;
	476	status = "disabled";
	477	};
	478
099343c6 BS	479	ssc0: ssc@fff9c000 {
	480	compatible = "atmel,at91sam9g45-ssc";
	481	reg = <0xfff9c000 0x4000>;
	482	interrupts = <16 4 5>;
544ae6b2 BS	483	pinctrl-names = "default";
544ae6b2 BS	484	pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
315656bc	485	status = "disabled";
099343c6 BS	486	};
	487
	488	ssc1: ssc@fffa0000 {
	489	compatible = "atmel,at91sam9g45-ssc";
	490	reg = <0xfffa0000 0x4000>;
	491	interrupts = <17 4 5>;
544ae6b2 BS	492	pinctrl-names = "default";
544ae6b2 BS	493	pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
315656bc	494	status = "disabled";
099343c6 BS	495	};
099343c6 BS	496
93b298ba MR	497	adc0: adc@fffb0000 {
	498	compatible = "atmel,at91sam9260-adc";
	499	reg = <0xfffb0000 0x100>;
f8a073ee	500	interrupts = <20 4 0>;
93b298ba MR	501	atmel,adc-use-external-triggers;
	502	atmel,adc-channels-used = <0xff>;
	503	atmel,adc-vref = <3300>;
	504	atmel,adc-num-channels = <8>;
	505	atmel,adc-startup-time = <40>;
	506	atmel,adc-channel-base = <0x30>;
	507	atmel,adc-drdy-mask = <0x10000>;
	508	atmel,adc-status-register = <0x1c>;
	509	atmel,adc-trigger-register = <0x08>;
4b50da65 LD	510	atmel,adc-res = <8 10>;
	511	atmel,adc-res-names = "lowres", "highres";
	512	atmel,adc-use-res = "highres";
93b298ba MR	513
	514	trigger@0 {
	515	trigger-name = "external-rising";
	516	trigger-value = <0x1>;
	517	trigger-external;
	518	};
	519	trigger@1 {
	520	trigger-name = "external-falling";
	521	trigger-value = <0x2>;
	522	trigger-external;
	523	};
	524
	525	trigger@2 {
	526	trigger-name = "external-any";
	527	trigger-value = <0x3>;
	528	trigger-external;
	529	};
	530
	531	trigger@3 {
	532	trigger-name = "continuous";
	533	trigger-value = <0x6>;
	534	};
	535	};
9873137a LD	536
	537	mmc0: mmc@fff80000 {
	538	compatible = "atmel,hsmci";
	539	reg = <0xfff80000 0x600>;
	540	interrupts = <11 4 0>;
05c1bc97 LD	541	dmas = <&dma 1 0>;
05c1bc97 LD	542	dma-names = "rxtx";
9873137a LD	543	#address-cells = <1>;
	544	#size-cells = <0>;
	545	status = "disabled";
	546	};
	547
	548	mmc1: mmc@fffd0000 {
	549	compatible = "atmel,hsmci";
	550	reg = <0xfffd0000 0x600>;
	551	interrupts = <29 4 0>;
05c1bc97 LD	552	dmas = <&dma 1 13>;
05c1bc97 LD	553	dma-names = "rxtx";
9873137a LD	554	#address-cells = <1>;
	555	#size-cells = <0>;
	556	status = "disabled";
db5b0ae0 LT	557	};
db5b0ae0 LT	558
7492e7ca FP	559	watchdog@fffffd40 {
	560	compatible = "atmel,at91sam9260-wdt";
	561	reg = <0xfffffd40 0x10>;
	562	status = "disabled";
d50f88a0 RG	563	};
	564
	565	spi0: spi@fffa4000 {
	566	#address-cells = <1>;
	567	#size-cells = <0>;
	568	compatible = "atmel,at91rm9200-spi";
	569	reg = <0xfffa4000 0x200>;
	570	interrupts = <14 4 3>;
a68b728f WY	571	pinctrl-names = "default";
a68b728f WY	572	pinctrl-0 = <&pinctrl_spi0>;
d50f88a0 RG	573	status = "disabled";
	574	};
	575
	576	spi1: spi@fffa8000 {
	577	#address-cells = <1>;
	578	#size-cells = <0>;
	579	compatible = "atmel,at91rm9200-spi";
	580	reg = <0xfffa8000 0x200>;
	581	interrupts = <15 4 3>;
a68b728f WY	582	pinctrl-names = "default";
a68b728f WY	583	pinctrl-0 = <&pinctrl_spi1>;
d50f88a0	584	status = "disabled";
9873137a	585	};
49fe2ba3	586	};
d6a01661 JCPV	587
	588	nand0: nand@40000000 {
	589	compatible = "atmel,at91rm9200-nand";
	590	#address-cells = <1>;
	591	#size-cells = <1>;
	592	reg = <0x40000000 0x10000000
	593	0xffffe200 0x200
	594	>;
	595	atmel,nand-addr-offset = <21>;
	596	atmel,nand-cmd-offset = <22>;
7a38d450 JCPV	597	pinctrl-names = "default";
7a38d450 JCPV	598	pinctrl-0 = <&pinctrl_nand>;
d6a01661 JCPV	599	gpios = <&pioC 8 0
	600	&pioC 14 0
	601	0
	602	>;
	603	status = "disabled";
	604	};
6a062459 JCPV	605
	606	usb0: ohci@00700000 {
	607	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	608	reg = <0x00700000 0x100000>;
f8a073ee	609	interrupts = <22 4 2>;
6a062459 JCPV	610	status = "disabled";
6a062459 JCPV	611	};
62c5553a JCPV	612
	613	usb1: ehci@00800000 {
	614	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
	615	reg = <0x00800000 0x100000>;
f8a073ee	616	interrupts = <22 4 2>;
62c5553a JCPV	617	status = "disabled";
62c5553a JCPV	618	};
49fe2ba3	619	};
8f24bdaa JCPV	620
	621	i2c@0 {
	622	compatible = "i2c-gpio";
	623	gpios = <&pioA 20 0 /* sda */
	624	&pioA 21 0 /* scl */
	625	>;
	626	i2c-gpio,sda-open-drain;
	627	i2c-gpio,scl-open-drain;
	628	i2c-gpio,delay-us = <5>; /* ~100 kHz */
	629	#address-cells = <1>;
	630	#size-cells = <0>;
	631	status = "disabled";
	632	};
49fe2ba3	633	};