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[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / at91sam9n12.dtsi
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cce783c6
HX		 1/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
6db64d29 10#include "skeleton.dtsi"
d4ae89c8 11#include <dt-bindings/dma/at91.h>
c9d0f317 12#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 13#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 14#include <dt-bindings/gpio/gpio.h>
68f1938e 15#include <dt-bindings/clock/at91.h>
cce783c6
HX		 16
17/ {
18 model = "Atmel AT91SAM9N12 SoC";
19 compatible = "atmel,at91sam9n12";
20 interrupt-parent = <&aic>;
21
22 aliases {
23 serial0 = &dbgu;
24 serial1 = &usart0;
25 serial2 = &usart1;
26 serial3 = &usart2;
27 serial4 = &usart3;
28 gpio0 = &pioA;
29 gpio1 = &pioB;
30 gpio2 = &pioC;
31 gpio3 = &pioD;
32 tcb0 = &tcb0;
33 tcb1 = &tcb1;
05dcd361
LD		 34 i2c0 = &i2c0;
35 i2c1 = &i2c1;
544ae6b2 36 ssc0 = &ssc0;
f3ab0527 37 pwm0 = &pwm0;
cce783c6
HX		 38 };
39 cpus {
e757a6ee
LP		 40 #address-cells = <0>;
41 #size-cells = <0>;
42
43 cpu {
44 compatible = "arm,arm926ej-s";
45 device_type = "cpu";
cce783c6
HX		 46 };
47 };
48
49 memory {
50 reg = <0x20000000 0x10000000>;
51 };
52
6503ab5f
AB		 53 clocks {
54 slow_xtal: slow_xtal {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <0>;
58 };
68f1938e 59
6503ab5f
AB		 60 main_xtal: main_xtal {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <0>;
64 };
68f1938e
BB		 65 };
66
f04660e4
AB		 67 sram: sram@00300000 {
68 compatible = "mmio-sram";
69 reg = <0x00300000 0x8000>;
70 };
71
cce783c6
HX		 72 ahb {
73 compatible = "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges;
77
78 apb {
79 compatible = "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 ranges;
83
84 aic: interrupt-controller@fffff000 {
f8a073ee 85 #interrupt-cells = <3>;
cce783c6
HX		 86 compatible = "atmel,at91rm9200-aic";
87 interrupt-controller;
88 reg = <0xfffff000 0x200>;
029efdda 89 atmel,external-irqs = <31>;
cce783c6
HX		 90 };
91
d9c41bf3
BB		 92 matrix: matrix@ffffde00 {
93 compatible = "atmel,at91sam9n12-matrix", "syscon";
94 reg = <0xffffde00 0x100>;
95 };
96
97 pmecc: ecc-engine@ffffe000 {
98 compatible = "atmel,at91sam9g45-pmecc";
99 reg = <0xffffe000 0x600>,
100 <0xffffe600 0x200>;
101 };
102
cce783c6
HX		 103 ramc0: ramc@ffffe800 {
104 compatible = "atmel,at91sam9g45-ddramc";
105 reg = <0xffffe800 0x200>;
7e948346
AB		 106 clocks = <&ddrck>;
107 clock-names = "ddrck";
cce783c6
HX		 108 };
109
d9c41bf3
BB		 110 smc: smc@ffffea00 {
111 compatible = "atmel,at91sam9260-smc", "syscon";
112 reg = <0xffffea00 0x200>;
113 };
114
cce783c6 115 pmc: pmc@fffffc00 {
620f5033 116 compatible = "atmel,at91sam9n12-pmc", "syscon";
68f1938e
BB		 117 reg = <0xfffffc00 0x200>;
118 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
119 interrupt-controller;
120 #address-cells = <1>;
121 #size-cells = <0>;
122 #interrupt-cells = <1>;
123
124 main_rc_osc: main_rc_osc {
125 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
126 #clock-cells = <0>;
127 interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
128 clock-frequency = <12000000>;
129 clock-accuracy = <50000000>;
130 };
131
132 main_osc: main_osc {
133 compatible = "atmel,at91rm9200-clk-main-osc";
134 #clock-cells = <0>;
135 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
136 clocks = <&main_xtal>;
137 };
138
139 main: mainck {
140 compatible = "atmel,at91sam9x5-clk-main";
141 #clock-cells = <0>;
142 interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
143 clocks = <&main_rc_osc>, <&main_osc>;
144 };
145
146 plla: pllack {
147 compatible = "atmel,at91rm9200-clk-pll";
148 #clock-cells = <0>;
149 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
150 clocks = <&main>;
151 reg = <0>;
152 atmel,clk-input-range = <2000000 32000000>;
153 #atmel,pll-clk-output-range-cells = <4>;
154 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
155 <695000000 750000000 1 0>,
156 <645000000 700000000 2 0>,
157 <595000000 650000000 3 0>,
158 <545000000 600000000 0 1>,
159 <495000000 555000000 1 1>,
8cbff69c
AB		 160 <445000000 500000000 2 1>,
161 <400000000 450000000 3 1>;
68f1938e
BB		 162 };
163
164 plladiv: plladivck {
165 compatible = "atmel,at91sam9x5-clk-plldiv";
166 #clock-cells = <0>;
167 clocks = <&plla>;
168 };
169
170 pllb: pllbck {
171 compatible = "atmel,at91rm9200-clk-pll";
172 #clock-cells = <0>;
173 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
174 clocks = <&main>;
175 reg = <1>;
176 atmel,clk-input-range = <2000000 32000000>;
177 #atmel,pll-clk-output-range-cells = <3>;
178 atmel,pll-clk-output-ranges = <30000000 100000000 0>;
179 };
180
181 mck: masterck {
182 compatible = "atmel,at91sam9x5-clk-master";
183 #clock-cells = <0>;
184 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
185 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
186 atmel,clk-output-range = <0 133333333>;
187 atmel,clk-divisors = <1 2 4 3>;
188 atmel,master-clk-have-div3-pres;
189 };
190
191 usb: usbck {
192 compatible = "atmel,at91sam9n12-clk-usb";
193 #clock-cells = <0>;
194 clocks = <&pllb>;
195 };
196
197 prog: progck {
198 compatible = "atmel,at91sam9x5-clk-programmable";
199 #address-cells = <1>;
200 #size-cells = <0>;
201 interrupt-parent = <&pmc>;
202 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
203
204 prog0: prog0 {
205 #clock-cells = <0>;
206 reg = <0>;
207 interrupts = <AT91_PMC_PCKRDY(0)>;
208 };
209
210 prog1: prog1 {
211 #clock-cells = <0>;
212 reg = <1>;
213 interrupts = <AT91_PMC_PCKRDY(1)>;
214 };
215 };
216
217 systemck {
218 compatible = "atmel,at91rm9200-clk-system";
219 #address-cells = <1>;
220 #size-cells = <0>;
221
222 ddrck: ddrck {
223 #clock-cells = <0>;
224 reg = <2>;
225 clocks = <&mck>;
226 };
227
228 lcdck: lcdck {
229 #clock-cells = <0>;
230 reg = <3>;
231 clocks = <&mck>;
232 };
233
234 uhpck: uhpck {
235 #clock-cells = <0>;
236 reg = <6>;
237 clocks = <&usb>;
238 };
239
240 udpck: udpck {
241 #clock-cells = <0>;
242 reg = <7>;
243 clocks = <&usb>;
244 };
245
246 pck0: pck0 {
247 #clock-cells = <0>;
248 reg = <8>;
249 clocks = <&prog0>;
250 };
251
252 pck1: pck1 {
253 #clock-cells = <0>;
254 reg = <9>;
255 clocks = <&prog1>;
256 };
257 };
258
259 periphck {
260 compatible = "atmel,at91sam9x5-clk-peripheral";
261 #address-cells = <1>;
262 #size-cells = <0>;
263 clocks = <&mck>;
264
265 pioAB_clk: pioAB_clk {
266 #clock-cells = <0>;
267 reg = <2>;
268 };
269
270 pioCD_clk: pioCD_clk {
271 #clock-cells = <0>;
272 reg = <3>;
273 };
274
275 fuse_clk: fuse_clk {
276 #clock-cells = <0>;
277 reg = <4>;
278 };
279
280 usart0_clk: usart0_clk {
281 #clock-cells = <0>;
282 reg = <5>;
283 };
284
285 usart1_clk: usart1_clk {
286 #clock-cells = <0>;
287 reg = <6>;
288 };
289
290 usart2_clk: usart2_clk {
291 #clock-cells = <0>;
292 reg = <7>;
293 };
294
295 usart3_clk: usart3_clk {
296 #clock-cells = <0>;
297 reg = <8>;
298 };
299
300 twi0_clk: twi0_clk {
301 reg = <9>;
302 #clock-cells = <0>;
303 };
304
305 twi1_clk: twi1_clk {
306 #clock-cells = <0>;
307 reg = <10>;
308 };
309
310 mci0_clk: mci0_clk {
311 #clock-cells = <0>;
312 reg = <12>;
313 };
314
315 spi0_clk: spi0_clk {
316 #clock-cells = <0>;
317 reg = <13>;
318 };
319
320 spi1_clk: spi1_clk {
321 #clock-cells = <0>;
322 reg = <14>;
323 };
324
325 uart0_clk: uart0_clk {
326 #clock-cells = <0>;
327 reg = <15>;
328 };
329
330 uart1_clk: uart1_clk {
331 #clock-cells = <0>;
332 reg = <16>;
333 };
334
335 tcb_clk: tcb_clk {
336 #clock-cells = <0>;
337 reg = <17>;
338 };
339
340 pwm_clk: pwm_clk {
341 #clock-cells = <0>;
342 reg = <18>;
343 };
344
345 adc_clk: adc_clk {
346 #clock-cells = <0>;
347 reg = <19>;
348 };
349
350 dma0_clk: dma0_clk {
351 #clock-cells = <0>;
352 reg = <20>;
353 };
354
355 uhphs_clk: uhphs_clk {
356 #clock-cells = <0>;
357 reg = <22>;
358 };
359
360 udphs_clk: udphs_clk {
361 #clock-cells = <0>;
362 reg = <23>;
363 };
364
365 lcdc_clk: lcdc_clk {
366 #clock-cells = <0>;
367 reg = <25>;
368 };
369
370 sha_clk: sha_clk {
371 #clock-cells = <0>;
372 reg = <27>;
373 };
374
375 ssc0_clk: ssc0_clk {
376 #clock-cells = <0>;
377 reg = <28>;
378 };
379
380 aes_clk: aes_clk {
381 #clock-cells = <0>;
382 reg = <29>;
383 };
384
385 trng_clk: trng_clk {
386 #clock-cells = <0>;
387 reg = <30>;
388 };
389 };
cce783c6
HX		 390 };
391
392 rstc@fffffe00 {
393 compatible = "atmel,at91sam9g45-rstc";
394 reg = <0xfffffe00 0x10>;
67451069 395 clocks = <&clk32k>;
cce783c6
HX		 396 };
397
398 pit: timer@fffffe30 {
399 compatible = "atmel,at91sam9260-pit";
400 reg = <0xfffffe30 0xf>;
5e8b3bc3 401 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
68f1938e 402 clocks = <&mck>;
cce783c6
HX		 403 };
404
405 shdwc@fffffe10 {
406 compatible = "atmel,at91sam9x5-shdwc";
407 reg = <0xfffffe10 0x10>;
67451069 408 clocks = <&clk32k>;
cce783c6
HX		 409 };
410
68f1938e
BB		 411 sckc@fffffe50 {
412 compatible = "atmel,at91sam9x5-sckc";
413 reg = <0xfffffe50 0x4>;
414
415 slow_osc: slow_osc {
416 compatible = "atmel,at91sam9x5-clk-slow-osc";
417 #clock-cells = <0>;
418 clocks = <&slow_xtal>;
419 };
420
421 slow_rc_osc: slow_rc_osc {
422 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
423 #clock-cells = <0>;
424 clock-frequency = <32768>;
425 clock-accuracy = <50000000>;
426 };
427
428 clk32k: slck {
429 compatible = "atmel,at91sam9x5-clk-slow";
430 #clock-cells = <0>;
431 clocks = <&slow_rc_osc>, <&slow_osc>;
432 };
433 };
434
9873137a
LD		 435 mmc0: mmc@f0008000 {
436 compatible = "atmel,hsmci";
437 reg = <0xf0008000 0x600>;
5e8b3bc3 438 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 439 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 440 dma-names = "rxtx";
68f1938e
BB		 441 clocks = <&mci0_clk>;
442 clock-names = "mci_clk";
9873137a
LD		 443 #address-cells = <1>;
444 #size-cells = <0>;
445 status = "disabled";
446 };
447
cce783c6
HX		 448 tcb0: timer@f8008000 {
449 compatible = "atmel,at91sam9x5-tcb";
450 reg = <0xf8008000 0x100>;
5e8b3bc3 451 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
67451069
AB		 452 clocks = <&tcb_clk>, <&clk32k>;
453 clock-names = "t0_clk", "slow_clk";
cce783c6
HX		 454 };
455
456 tcb1: timer@f800c000 {
457 compatible = "atmel,at91sam9x5-tcb";
458 reg = <0xf800c000 0x100>;
5e8b3bc3 459 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
67451069
AB		 460 clocks = <&tcb_clk>, <&clk32k>;
461 clock-names = "t0_clk", "slow_clk";
cce783c6
HX		 462 };
463
a437fc59
BS		 464 hlcdc: hlcdc@f8038000 {
465 compatible = "atmel,at91sam9n12-hlcdc";
466 reg = <0xf8038000 0x2000>;
467 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
468 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
469 clock-names = "periph_clk", "sys_clk", "slow_clk";
470 status = "disabled";
471
472 hlcdc-display-controller {
473 compatible = "atmel,hlcdc-display-controller";
474 #address-cells = <1>;
475 #size-cells = <0>;
476
477 port@0 {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 reg = <0>;
481 };
482 };
483
484 hlcdc_pwm: hlcdc-pwm {
485 compatible = "atmel,hlcdc-pwm";
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_lcd_pwm>;
488 #pwm-cells = <3>;
489 };
490 };
491
cce783c6
HX		 492 dma: dma-controller@ffffec00 {
493 compatible = "atmel,at91sam9g45-dma";
494 reg = <0xffffec00 0x200>;
5e8b3bc3 495 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 496 #dma-cells = <2>;
68f1938e
BB		 497 clocks = <&dma0_clk>;
498 clock-names = "dma_clk";
cce783c6
HX		 499 };
500
e4541ff2
JCPV		 501 pinctrl@fffff400 {
502 #address-cells = <1>;
503 #size-cells = <1>;
5314ec8e 504 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
e4541ff2
JCPV		 505 ranges = <0xfffff400 0xfffff400 0x800>;
506
5314ec8e
JCPV		 507 atmel,mux-mask = <
508 /* A B C */
509 0xffffffff 0xffe07983 0x00000000 /* pioA */
510 0x00040000 0x00047e0f 0x00000000 /* pioB */
511 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
512 0x003fffff 0x003f8000 0x00000000 /* pioD */
513 >;
514
515 /* shared pinctrl settings */
ec6754a7
JCPV		 516 dbgu {
517 pinctrl_dbgu: dbgu-0 {
518 atmel,pins =
138c2b2f
SR		 519 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
520 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
ec6754a7
JCPV		 521 };
522 };
523
a437fc59
BS		 524 lcd {
525 pinctrl_lcd_base: lcd-base-0 {
526 atmel,pins =
527 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
528 AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
529 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
530 AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
531 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
532 };
533
534 pinctrl_lcd_pwm: lcd-pwm-0 {
535 atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
536 };
537
538 pinctrl_lcd_rgb888: lcd-rgb-3 {
539 atmel,pins =
540 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
541 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
542 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
543 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
544 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
545 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
546 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
547 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
548 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
549 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
550 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
551 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
552 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
553 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
554 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
555 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
556 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
557 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
558 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
559 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
560 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
561 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
562 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
563 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
564 };
565 };
566
9e3129e9
JCPV		 567 usart0 {
568 pinctrl_usart0: usart0-0 {
ec6754a7 569 atmel,pins =
c9d0f317
JCPV		 570 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
571 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
ec6754a7
JCPV		 572 };
573
c58c0c5a 574 pinctrl_usart0_rts: usart0_rts-0 {
ec6754a7 575 atmel,pins =
c9d0f317 576 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
c58c0c5a
JCPV		 577 };
578
579 pinctrl_usart0_cts: usart0_cts-0 {
580 atmel,pins =
c9d0f317 581 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
ec6754a7
JCPV		 582 };
583 };
584
9e3129e9
JCPV		 585 usart1 {
586 pinctrl_usart1: usart1-0 {
ec6754a7 587 atmel,pins =
c9d0f317
JCPV		 588 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
589 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
ec6754a7
JCPV		 590 };
591 };
592
9e3129e9
JCPV		 593 usart2 {
594 pinctrl_usart2: usart2-0 {
ec6754a7 595 atmel,pins =
c9d0f317
JCPV		 596 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
597 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
ec6754a7
JCPV		 598 };
599
c58c0c5a 600 pinctrl_usart2_rts: usart2_rts-0 {
ec6754a7 601 atmel,pins =
c9d0f317 602 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
c58c0c5a
JCPV		 603 };
604
605 pinctrl_usart2_cts: usart2_cts-0 {
606 atmel,pins =
c9d0f317 607 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
ec6754a7
JCPV		 608 };
609 };
610
9e3129e9
JCPV		 611 usart3 {
612 pinctrl_usart3: usart3-0 {
ec6754a7 613 atmel,pins =
c9d0f317
JCPV		 614 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
615 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
ec6754a7
JCPV		 616 };
617
c58c0c5a
JCPV		 618 pinctrl_usart3_rts: usart3_rts-0 {
619 atmel,pins =
c9d0f317 620 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
c58c0c5a
JCPV		 621 };
622
623 pinctrl_usart3_cts: usart3_cts-0 {
ec6754a7 624 atmel,pins =
c9d0f317 625 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
ec6754a7
JCPV		 626 };
627 };
628
9e3129e9
JCPV		 629 uart0 {
630 pinctrl_uart0: uart0-0 {
ec6754a7 631 atmel,pins =
c9d0f317
JCPV		 632 <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
633 AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
ec6754a7
JCPV		 634 };
635 };
636
9e3129e9
JCPV		 637 uart1 {
638 pinctrl_uart1: uart1-0 {
ec6754a7 639 atmel,pins =
c9d0f317
JCPV		 640 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
641 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
ec6754a7
JCPV		 642 };
643 };
5314ec8e 644
7a38d450 645 nand {
1004a297 646 pinctrl_nand_rb: nand-rb-0 {
7a38d450 647 atmel,pins =
1004a297
BB		 648 <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
649 };
650
651 pinctrl_nand_cs: nand-cs-0 {
652 atmel,pins =
653 <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
7a38d450
JCPV		 654 };
655 };
656
d4fe9ac7
JCPV		 657 mmc0 {
658 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
659 atmel,pins =
c9d0f317
JCPV		 660 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
661 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
662 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
d4fe9ac7
JCPV		 663 };
664
665 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
666 atmel,pins =
c9d0f317
JCPV		 667 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
668 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
669 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
d4fe9ac7
JCPV		 670 };
671
672 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
673 atmel,pins =
c9d0f317
JCPV		 674 <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
675 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
676 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
677 AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
d4fe9ac7
JCPV		 678 };
679 };
680
544ae6b2
BS		 681 ssc0 {
682 pinctrl_ssc0_tx: ssc0_tx-0 {
683 atmel,pins =
c9d0f317
JCPV		 684 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
685 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
686 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
544ae6b2
BS		 687 };
688
689 pinctrl_ssc0_rx: ssc0_rx-0 {
690 atmel,pins =
c9d0f317
JCPV		 691 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
692 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
693 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
544ae6b2
BS		 694 };
695 };
696
a68b728f
WY		 697 spi0 {
698 pinctrl_spi0: spi0-0 {
699 atmel,pins =
c9d0f317
JCPV		 700 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
701 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
702 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
a68b728f
WY		 703 };
704 };
705
706 spi1 {
707 pinctrl_spi1: spi1-0 {
708 atmel,pins =
c9d0f317
JCPV		 709 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
710 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
711 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
a68b728f
WY		 712 };
713 };
714
1f84d27b 715 i2c0 {
716 pinctrl_i2c0: i2c0-0 {
717 atmel,pins =
718 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
719 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
720 };
721 };
722
723 i2c1 {
724 pinctrl_i2c1: i2c1-0 {
725 atmel,pins =
726 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
727 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
728 };
729 };
730
028633c2
BB		 731 tcb0 {
732 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
733 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
734 };
735
736 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
737 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
738 };
739
740 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
741 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
742 };
743
744 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
745 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
746 };
747
748 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
749 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
750 };
751
752 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
753 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
754 };
755
756 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
757 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
758 };
759
760 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
761 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
762 };
763
764 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
765 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
766 };
767 };
768
769 tcb1 {
770 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
771 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
772 };
773
774 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
775 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
776 };
777
778 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
779 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
780 };
781
782 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
783 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
784 };
785
786 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
787 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
788 };
789
790 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
791 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
792 };
793
794 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
795 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
796 };
797
798 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
799 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
800 };
801
802 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
803 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
a68b728f
WY		 804 };
805 };
806
e4541ff2
JCPV		 807 pioA: gpio@fffff400 {
808 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
809 reg = <0xfffff400 0x200>;
5e8b3bc3 810 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 811 #gpio-cells = <2>;
812 gpio-controller;
813 interrupt-controller;
814 #interrupt-cells = <2>;
68f1938e 815 clocks = <&pioAB_clk>;
e4541ff2
JCPV		 816 };
817
818 pioB: gpio@fffff600 {
819 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
820 reg = <0xfffff600 0x200>;
5e8b3bc3 821 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 822 #gpio-cells = <2>;
823 gpio-controller;
824 interrupt-controller;
825 #interrupt-cells = <2>;
68f1938e 826 clocks = <&pioAB_clk>;
e4541ff2
JCPV		 827 };
828
829 pioC: gpio@fffff800 {
830 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
831 reg = <0xfffff800 0x200>;
5e8b3bc3 832 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 833 #gpio-cells = <2>;
834 gpio-controller;
835 interrupt-controller;
836 #interrupt-cells = <2>;
68f1938e 837 clocks = <&pioCD_clk>;
e4541ff2
JCPV		 838 };
839
840 pioD: gpio@fffffa00 {
841 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
842 reg = <0xfffffa00 0x200>;
5e8b3bc3 843 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 844 #gpio-cells = <2>;
845 gpio-controller;
846 interrupt-controller;
847 #interrupt-cells = <2>;
68f1938e 848 clocks = <&pioCD_clk>;
e4541ff2 849 };
cce783c6
HX		 850 };
851
852 dbgu: serial@fffff200 {
8c07f664 853 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
cce783c6 854 reg = <0xfffff200 0x200>;
5e8b3bc3 855 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
ec6754a7
JCPV		 856 pinctrl-names = "default";
857 pinctrl-0 = <&pinctrl_dbgu>;
68f1938e
BB		 858 clocks = <&mck>;
859 clock-names = "usart";
cce783c6
HX		 860 status = "disabled";
861 };
862
544ae6b2
BS		 863 ssc0: ssc@f0010000 {
864 compatible = "atmel,at91sam9g45-ssc";
865 reg = <0xf0010000 0x4000>;
5e8b3bc3 866 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
ffcd77e2
BS		 867 dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
868 <&dma 0 AT91_DMA_CFG_PER_ID(22)>;
869 dma-names = "tx", "rx";
544ae6b2
BS		 870 pinctrl-names = "default";
871 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
68f1938e
BB		 872 clocks = <&ssc0_clk>;
873 clock-names = "pclk";
544ae6b2
BS		 874 status = "disabled";
875 };
876
cce783c6
HX		 877 usart0: serial@f801c000 {
878 compatible = "atmel,at91sam9260-usart";
879 reg = <0xf801c000 0x4000>;
5e8b3bc3 880 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 881 pinctrl-names = "default";
9e3129e9 882 pinctrl-0 = <&pinctrl_usart0>;
68f1938e
BB		 883 clocks = <&usart0_clk>;
884 clock-names = "usart";
cce783c6
HX		 885 status = "disabled";
886 };
887
888 usart1: serial@f8020000 {
889 compatible = "atmel,at91sam9260-usart";
890 reg = <0xf8020000 0x4000>;
5e8b3bc3 891 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 892 pinctrl-names = "default";
9e3129e9 893 pinctrl-0 = <&pinctrl_usart1>;
68f1938e
BB		 894 clocks = <&usart1_clk>;
895 clock-names = "usart";
cce783c6
HX		 896 status = "disabled";
897 };
898
899 usart2: serial@f8024000 {
900 compatible = "atmel,at91sam9260-usart";
901 reg = <0xf8024000 0x4000>;
5e8b3bc3 902 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 903 pinctrl-names = "default";
9e3129e9 904 pinctrl-0 = <&pinctrl_usart2>;
68f1938e
BB		 905 clocks = <&usart2_clk>;
906 clock-names = "usart";
cce783c6
HX		 907 status = "disabled";
908 };
909
910 usart3: serial@f8028000 {
911 compatible = "atmel,at91sam9260-usart";
912 reg = <0xf8028000 0x4000>;
5e8b3bc3 913 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 914 pinctrl-names = "default";
9e3129e9 915 pinctrl-0 = <&pinctrl_usart3>;
68f1938e
BB		 916 clocks = <&usart3_clk>;
917 clock-names = "usart";
cce783c6
HX		 918 status = "disabled";
919 };
05dcd361
LD		 920
921 i2c0: i2c@f8010000 {
922 compatible = "atmel,at91sam9x5-i2c";
923 reg = <0xf8010000 0x100>;
5e8b3bc3 924 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 925 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
926 <&dma 1 AT91_DMA_CFG_PER_ID(14)>;
d9a63a45 927 dma-names = "tx", "rx";
05dcd361
LD		 928 #address-cells = <1>;
929 #size-cells = <0>;
1f84d27b 930 pinctrl-names = "default";
931 pinctrl-0 = <&pinctrl_i2c0>;
68f1938e 932 clocks = <&twi0_clk>;
05dcd361
LD		 933 status = "disabled";
934 };
935
936 i2c1: i2c@f8014000 {
937 compatible = "atmel,at91sam9x5-i2c";
938 reg = <0xf8014000 0x100>;
5e8b3bc3 939 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 940 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
941 <&dma 1 AT91_DMA_CFG_PER_ID(16)>;
d9a63a45 942 dma-names = "tx", "rx";
05dcd361
LD		 943 #address-cells = <1>;
944 #size-cells = <0>;
1f84d27b 945 pinctrl-names = "default";
946 pinctrl-0 = <&pinctrl_i2c1>;
68f1938e 947 clocks = <&twi1_clk>;
05dcd361
LD		 948 status = "disabled";
949 };
d50f88a0
RG		 950
951 spi0: spi@f0000000 {
952 #address-cells = <1>;
953 #size-cells = <0>;
954 compatible = "atmel,at91rm9200-spi";
955 reg = <0xf0000000 0x100>;
5e8b3bc3 956 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
c07b000f
NF		 957 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
958 <&dma 1 AT91_DMA_CFG_PER_ID(2)>;
959 dma-names = "tx", "rx";
a68b728f
WY		 960 pinctrl-names = "default";
961 pinctrl-0 = <&pinctrl_spi0>;
68f1938e
BB		 962 clocks = <&spi0_clk>;
963 clock-names = "spi_clk";
d50f88a0
RG		 964 status = "disabled";
965 };
966
967 spi1: spi@f0004000 {
968 #address-cells = <1>;
969 #size-cells = <0>;
970 compatible = "atmel,at91rm9200-spi";
971 reg = <0xf0004000 0x100>;
5e8b3bc3 972 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
c07b000f
NF		 973 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
974 <&dma 1 AT91_DMA_CFG_PER_ID(4)>;
975 dma-names = "tx", "rx";
a68b728f
WY		 976 pinctrl-names = "default";
977 pinctrl-0 = <&pinctrl_spi1>;
68f1938e
BB		 978 clocks = <&spi1_clk>;
979 clock-names = "spi_clk";
d50f88a0
RG		 980 status = "disabled";
981 };
136d3556
WY		 982
983 watchdog@fffffe40 {
984 compatible = "atmel,at91sam9260-wdt";
985 reg = <0xfffffe40 0x10>;
fe46aa67 986 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
67451069 987 clocks = <&clk32k>;
fe46aa67
BB		 988 atmel,watchdog-type = "hardware";
989 atmel,reset-type = "all";
990 atmel,dbg-halt;
136d3556
WY		 991 status = "disabled";
992 };
f3ab0527 993
52820d26
AB		 994 rtc@fffffeb0 {
995 compatible = "atmel,at91rm9200-rtc";
996 reg = <0xfffffeb0 0x40>;
997 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
67451069 998 clocks = <&clk32k>;
52820d26
AB		 999 status = "disabled";
1000 };
1001
f3ab0527
BS		 1002 pwm0: pwm@f8034000 {
1003 compatible = "atmel,at91sam9rl-pwm";
1004 reg = <0xf8034000 0x300>;
1005 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
1006 #pwm-cells = <3>;
68f1938e 1007 clocks = <&pwm_clk>;
f3ab0527
BS		 1008 status = "disabled";
1009 };
13f7ad3d
BS		 1010
1011 usb1: gadget@f803c000 {
1012 compatible = "atmel,at91sam9260-udc";
1013 reg = <0xf803c000 0x4000>;
1014 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
1015 clocks = <&udphs_clk>, <&udpck>;
1016 clock-names = "pclk", "hclk";
1017 status = "disabled";
1018 };
cce783c6
HX		 1019 };
1020
cce783c6
HX		 1021 usb0: ohci@00500000 {
1022 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1023 reg = <0x00500000 0x00100000>;
5e8b3bc3 1024 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
f8073708
BB		 1025 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1026 clock-names = "ohci_clk", "hclk", "uhpck";
cce783c6
HX		 1027 status = "disabled";
1028 };
d9c41bf3
BB		 1029
1030 ebi: ebi@10000000 {
1031 compatible = "atmel,at91sam9x5-ebi";
1032 #address-cells = <2>;
1033 #size-cells = <1>;
1034 atmel,smc = <&smc>;
1035 atmel,matrix = <&matrix>;
1036 reg = <0x10000000 0x60000000>;
1037 ranges = <0x0 0x0 0x10000000 0x10000000
1038 0x1 0x0 0x20000000 0x10000000
1039 0x2 0x0 0x30000000 0x10000000
1040 0x3 0x0 0x40000000 0x10000000
1041 0x4 0x0 0x50000000 0x10000000
1042 0x5 0x0 0x60000000 0x10000000>;
1043 clocks = <&mck>;
1044 status = "disabled";
1045
1046 nand_controller: nand-controller {
1047 compatible = "atmel,at91sam9g45-nand-controller";
1048 ecc-engine = <&pmecc>;
1049 #address-cells = <2>;
1050 #size-cells = <1>;
1051 ranges;
1052 status = "disabled";
1053 };
1054 };
cce783c6
HX		 1055 };
1056
e152e3f7 1057 i2c-gpio-0 {
cce783c6 1058 compatible = "i2c-gpio";
92f8629b
JCPV		 1059 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
1060 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
cce783c6
HX		 1061 >;
1062 i2c-gpio,sda-open-drain;
1063 i2c-gpio,scl-open-drain;
1064 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1067 status = "disabled";
1068 };
1069};
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