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Commit | Line | Data |
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5fa2f9af BS |
1 | /* |
2 | * DTS file for CSR SiRFatlas6 SoC | |
3 | * | |
4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
10 | / { | |
11 | compatible = "sirf,atlas6"; | |
12 | #address-cells = <1>; | |
13 | #size-cells = <1>; | |
14 | interrupt-parent = <&intc>; | |
15 | ||
16 | cpus { | |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
20 | cpu@0 { | |
21 | reg = <0x0>; | |
22 | d-cache-line-size = <32>; | |
23 | i-cache-line-size = <32>; | |
24 | d-cache-size = <32768>; | |
25 | i-cache-size = <32768>; | |
26 | /* from bootloader */ | |
27 | timebase-frequency = <0>; | |
28 | bus-frequency = <0>; | |
29 | clock-frequency = <0>; | |
683659f3 RY |
30 | clocks = <&clks 12>; |
31 | operating-points = < | |
32 | /* kHz uV */ | |
33 | 200000 1025000 | |
34 | 400000 1025000 | |
35 | 600000 1050000 | |
36 | 800000 1100000 | |
37 | >; | |
38 | clock-latency = <150000>; | |
5fa2f9af BS |
39 | }; |
40 | }; | |
41 | ||
42 | axi { | |
43 | compatible = "simple-bus"; | |
44 | #address-cells = <1>; | |
45 | #size-cells = <1>; | |
46 | ranges = <0x40000000 0x40000000 0x80000000>; | |
47 | ||
48 | intc: interrupt-controller@80020000 { | |
49 | #interrupt-cells = <1>; | |
50 | interrupt-controller; | |
51 | compatible = "sirf,prima2-intc"; | |
52 | reg = <0x80020000 0x1000>; | |
53 | }; | |
54 | ||
55 | sys-iobg { | |
56 | compatible = "simple-bus"; | |
57 | #address-cells = <1>; | |
58 | #size-cells = <1>; | |
59 | ranges = <0x88000000 0x88000000 0x40000>; | |
60 | ||
61 | clks: clock-controller@88000000 { | |
62 | compatible = "sirf,atlas6-clkc"; | |
63 | reg = <0x88000000 0x1000>; | |
64 | interrupts = <3>; | |
65 | #clock-cells = <1>; | |
66 | }; | |
67 | ||
e7eda91f | 68 | rstc: reset-controller@88010000 { |
5fa2f9af BS |
69 | compatible = "sirf,prima2-rstc"; |
70 | reg = <0x88010000 0x1000>; | |
e7eda91f | 71 | #reset-cells = <1>; |
5fa2f9af BS |
72 | }; |
73 | ||
74 | rsc-controller@88020000 { | |
75 | compatible = "sirf,prima2-rsc"; | |
76 | reg = <0x88020000 0x1000>; | |
77 | }; | |
0671840c BS |
78 | |
79 | cphifbg@88030000 { | |
80 | compatible = "sirf,prima2-cphifbg"; | |
81 | reg = <0x88030000 0x1000>; | |
794f8b21 | 82 | clocks = <&clks 42>; |
0671840c | 83 | }; |
5fa2f9af BS |
84 | }; |
85 | ||
86 | mem-iobg { | |
87 | compatible = "simple-bus"; | |
88 | #address-cells = <1>; | |
89 | #size-cells = <1>; | |
90 | ranges = <0x90000000 0x90000000 0x10000>; | |
91 | ||
92 | memory-controller@90000000 { | |
93 | compatible = "sirf,prima2-memc"; | |
5fadea22 | 94 | reg = <0x90000000 0x2000>; |
5fa2f9af BS |
95 | interrupts = <27>; |
96 | clocks = <&clks 5>; | |
97 | }; | |
5fadea22 YH |
98 | |
99 | memc-monitor { | |
100 | compatible = "sirf,prima2-memcmon"; | |
101 | reg = <0x90002000 0x200>; | |
102 | interrupts = <4>; | |
103 | clocks = <&clks 32>; | |
104 | }; | |
5fa2f9af BS |
105 | }; |
106 | ||
107 | disp-iobg { | |
108 | compatible = "simple-bus"; | |
109 | #address-cells = <1>; | |
110 | #size-cells = <1>; | |
111 | ranges = <0x90010000 0x90010000 0x30000>; | |
112 | ||
113 | lcd@90010000 { | |
114 | compatible = "sirf,prima2-lcd"; | |
115 | reg = <0x90010000 0x20000>; | |
116 | interrupts = <30>; | |
117 | clocks = <&clks 34>; | |
118 | display=<&display>; | |
119 | /* later transfer to pwm */ | |
120 | bl-gpio = <&gpio 7 0>; | |
121 | default-panel = <&panel0>; | |
122 | }; | |
123 | ||
124 | vpp@90020000 { | |
125 | compatible = "sirf,prima2-vpp"; | |
126 | reg = <0x90020000 0x10000>; | |
127 | interrupts = <31>; | |
128 | clocks = <&clks 35>; | |
129 | }; | |
130 | }; | |
131 | ||
132 | graphics-iobg { | |
133 | compatible = "simple-bus"; | |
134 | #address-cells = <1>; | |
135 | #size-cells = <1>; | |
136 | ranges = <0x98000000 0x98000000 0x8000000>; | |
137 | ||
138 | graphics@98000000 { | |
139 | compatible = "powervr,sgx510"; | |
140 | reg = <0x98000000 0x8000000>; | |
141 | interrupts = <6>; | |
142 | clocks = <&clks 32>; | |
143 | }; | |
144 | }; | |
145 | ||
304ec42f JC |
146 | graphics2d-iobg { |
147 | compatible = "simple-bus"; | |
148 | #address-cells = <1>; | |
149 | #size-cells = <1>; | |
150 | ranges = <0xa0000000 0xa0000000 0x8000000>; | |
151 | ||
152 | ble@a0000000 { | |
153 | compatible = "sirf,atlas6-ble"; | |
154 | reg = <0xa0000000 0x2000>; | |
155 | interrupts = <5>; | |
156 | clocks = <&clks 33>; | |
157 | }; | |
158 | }; | |
159 | ||
5fa2f9af BS |
160 | dsp-iobg { |
161 | compatible = "simple-bus"; | |
162 | #address-cells = <1>; | |
163 | #size-cells = <1>; | |
164 | ranges = <0xa8000000 0xa8000000 0x2000000>; | |
165 | ||
166 | dspif@a8000000 { | |
167 | compatible = "sirf,prima2-dspif"; | |
168 | reg = <0xa8000000 0x10000>; | |
169 | interrupts = <9>; | |
170 | }; | |
171 | ||
172 | gps@a8010000 { | |
173 | compatible = "sirf,prima2-gps"; | |
174 | reg = <0xa8010000 0x10000>; | |
175 | interrupts = <7>; | |
176 | clocks = <&clks 9>; | |
177 | }; | |
178 | ||
179 | dsp@a9000000 { | |
180 | compatible = "sirf,prima2-dsp"; | |
181 | reg = <0xa9000000 0x1000000>; | |
182 | interrupts = <8>; | |
183 | clocks = <&clks 8>; | |
184 | }; | |
185 | }; | |
186 | ||
187 | peri-iobg { | |
188 | compatible = "simple-bus"; | |
189 | #address-cells = <1>; | |
190 | #size-cells = <1>; | |
191 | ranges = <0xb0000000 0xb0000000 0x180000>, | |
192 | <0x56000000 0x56000000 0x1b00000>; | |
193 | ||
194 | timer@b0020000 { | |
195 | compatible = "sirf,prima2-tick"; | |
196 | reg = <0xb0020000 0x1000>; | |
197 | interrupts = <0>; | |
198 | }; | |
199 | ||
200 | nand@b0030000 { | |
201 | compatible = "sirf,prima2-nand"; | |
202 | reg = <0xb0030000 0x10000>; | |
203 | interrupts = <41>; | |
204 | clocks = <&clks 26>; | |
205 | }; | |
206 | ||
207 | audio@b0040000 { | |
208 | compatible = "sirf,prima2-audio"; | |
209 | reg = <0xb0040000 0x10000>; | |
210 | interrupts = <35>; | |
211 | clocks = <&clks 27>; | |
212 | }; | |
213 | ||
214 | uart0: uart@b0050000 { | |
215 | cell-index = <0>; | |
216 | compatible = "sirf,prima2-uart"; | |
217 | reg = <0xb0050000 0x1000>; | |
218 | interrupts = <17>; | |
219 | fifosize = <128>; | |
220 | clocks = <&clks 13>; | |
9be16b38 QL |
221 | dmas = <&dmac1 5>, <&dmac0 2>; |
222 | dma-names = "rx", "tx"; | |
5fa2f9af BS |
223 | }; |
224 | ||
225 | uart1: uart@b0060000 { | |
226 | cell-index = <1>; | |
227 | compatible = "sirf,prima2-uart"; | |
228 | reg = <0xb0060000 0x1000>; | |
229 | interrupts = <18>; | |
230 | fifosize = <32>; | |
231 | clocks = <&clks 14>; | |
9be16b38 | 232 | dma-names = "no-rx", "no-tx"; |
5fa2f9af BS |
233 | }; |
234 | ||
235 | uart2: uart@b0070000 { | |
236 | cell-index = <2>; | |
237 | compatible = "sirf,prima2-uart"; | |
238 | reg = <0xb0070000 0x1000>; | |
239 | interrupts = <19>; | |
240 | fifosize = <128>; | |
241 | clocks = <&clks 15>; | |
9be16b38 QL |
242 | dmas = <&dmac0 6>, <&dmac0 7>; |
243 | dma-names = "rx", "tx"; | |
5fa2f9af BS |
244 | }; |
245 | ||
246 | usp0: usp@b0080000 { | |
247 | cell-index = <0>; | |
248 | compatible = "sirf,prima2-usp"; | |
249 | reg = <0xb0080000 0x10000>; | |
250 | interrupts = <20>; | |
a1369978 | 251 | fifosize = <128>; |
5fa2f9af | 252 | clocks = <&clks 28>; |
9be16b38 QL |
253 | dmas = <&dmac1 1>, <&dmac1 2>; |
254 | dma-names = "rx", "tx"; | |
5fa2f9af BS |
255 | }; |
256 | ||
257 | usp1: usp@b0090000 { | |
258 | cell-index = <1>; | |
259 | compatible = "sirf,prima2-usp"; | |
260 | reg = <0xb0090000 0x10000>; | |
261 | interrupts = <21>; | |
a1369978 | 262 | fifosize = <128>; |
5fa2f9af | 263 | clocks = <&clks 29>; |
9be16b38 QL |
264 | dmas = <&dmac0 14>, <&dmac0 15>; |
265 | dma-names = "rx", "tx"; | |
5fa2f9af BS |
266 | }; |
267 | ||
268 | dmac0: dma-controller@b00b0000 { | |
269 | cell-index = <0>; | |
270 | compatible = "sirf,prima2-dmac"; | |
271 | reg = <0xb00b0000 0x10000>; | |
272 | interrupts = <12>; | |
273 | clocks = <&clks 24>; | |
2e041c94 | 274 | #dma-cells = <1>; |
5fa2f9af BS |
275 | }; |
276 | ||
277 | dmac1: dma-controller@b0160000 { | |
278 | cell-index = <1>; | |
279 | compatible = "sirf,prima2-dmac"; | |
280 | reg = <0xb0160000 0x10000>; | |
281 | interrupts = <13>; | |
282 | clocks = <&clks 25>; | |
2e041c94 | 283 | #dma-cells = <1>; |
5fa2f9af BS |
284 | }; |
285 | ||
286 | vip@b00C0000 { | |
287 | compatible = "sirf,prima2-vip"; | |
288 | reg = <0xb00C0000 0x10000>; | |
289 | clocks = <&clks 31>; | |
262bcc1d RW |
290 | interrupts = <14>; |
291 | sirf,vip-dma-rx-channel = <16>; | |
5fa2f9af BS |
292 | }; |
293 | ||
294 | spi0: spi@b00d0000 { | |
295 | cell-index = <0>; | |
296 | compatible = "sirf,prima2-spi"; | |
297 | reg = <0xb00d0000 0x10000>; | |
298 | interrupts = <15>; | |
299 | sirf,spi-num-chipselects = <1>; | |
300 | cs-gpios = <&gpio 0 0>; | |
301 | sirf,spi-dma-rx-channel = <25>; | |
302 | sirf,spi-dma-tx-channel = <20>; | |
303 | #address-cells = <1>; | |
304 | #size-cells = <0>; | |
305 | clocks = <&clks 19>; | |
306 | status = "disabled"; | |
307 | }; | |
308 | ||
309 | spi1: spi@b0170000 { | |
310 | cell-index = <1>; | |
311 | compatible = "sirf,prima2-spi"; | |
312 | reg = <0xb0170000 0x10000>; | |
313 | interrupts = <16>; | |
6f425115 BS |
314 | sirf,spi-num-chipselects = <1>; |
315 | sirf,spi-dma-rx-channel = <12>; | |
316 | sirf,spi-dma-tx-channel = <13>; | |
317 | #address-cells = <1>; | |
318 | #size-cells = <0>; | |
5fa2f9af BS |
319 | clocks = <&clks 20>; |
320 | status = "disabled"; | |
321 | }; | |
322 | ||
323 | i2c0: i2c@b00e0000 { | |
324 | cell-index = <0>; | |
325 | compatible = "sirf,prima2-i2c"; | |
326 | reg = <0xb00e0000 0x10000>; | |
327 | interrupts = <24>; | |
328 | #address-cells = <1>; | |
329 | #size-cells = <0>; | |
330 | clocks = <&clks 17>; | |
331 | }; | |
332 | ||
333 | i2c1: i2c@b00f0000 { | |
334 | cell-index = <1>; | |
335 | compatible = "sirf,prima2-i2c"; | |
336 | reg = <0xb00f0000 0x10000>; | |
337 | interrupts = <25>; | |
338 | #address-cells = <1>; | |
339 | #size-cells = <0>; | |
340 | clocks = <&clks 18>; | |
341 | }; | |
342 | ||
343 | tsc@b0110000 { | |
344 | compatible = "sirf,prima2-tsc"; | |
345 | reg = <0xb0110000 0x10000>; | |
346 | interrupts = <33>; | |
347 | clocks = <&clks 16>; | |
348 | }; | |
349 | ||
350 | gpio: pinctrl@b0120000 { | |
351 | #gpio-cells = <2>; | |
352 | #interrupt-cells = <2>; | |
353 | compatible = "sirf,atlas6-pinctrl"; | |
354 | reg = <0xb0120000 0x10000>; | |
355 | interrupts = <43 44 45 46 47>; | |
356 | gpio-controller; | |
357 | interrupt-controller; | |
358 | ||
359 | lcd_16pins_a: lcd0@0 { | |
360 | lcd { | |
361 | sirf,pins = "lcd_16bitsgrp"; | |
362 | sirf,function = "lcd_16bits"; | |
363 | }; | |
364 | }; | |
365 | lcd_18pins_a: lcd0@1 { | |
366 | lcd { | |
367 | sirf,pins = "lcd_18bitsgrp"; | |
368 | sirf,function = "lcd_18bits"; | |
369 | }; | |
370 | }; | |
371 | lcd_24pins_a: lcd0@2 { | |
372 | lcd { | |
373 | sirf,pins = "lcd_24bitsgrp"; | |
374 | sirf,function = "lcd_24bits"; | |
375 | }; | |
376 | }; | |
377 | lcdrom_pins_a: lcdrom0@0 { | |
378 | lcd { | |
379 | sirf,pins = "lcdromgrp"; | |
380 | sirf,function = "lcdrom"; | |
381 | }; | |
382 | }; | |
383 | uart0_pins_a: uart0@0 { | |
384 | uart { | |
385 | sirf,pins = "uart0grp"; | |
386 | sirf,function = "uart0"; | |
387 | }; | |
388 | }; | |
031b8ce0 QL |
389 | uart0_noflow_pins_a: uart0@1 { |
390 | uart { | |
391 | sirf,pins = "uart0_nostreamctrlgrp"; | |
392 | sirf,function = "uart0_nostreamctrl"; | |
393 | }; | |
394 | }; | |
5fa2f9af BS |
395 | uart1_pins_a: uart1@0 { |
396 | uart { | |
397 | sirf,pins = "uart1grp"; | |
398 | sirf,function = "uart1"; | |
399 | }; | |
400 | }; | |
401 | uart2_pins_a: uart2@0 { | |
402 | uart { | |
403 | sirf,pins = "uart2grp"; | |
404 | sirf,function = "uart2"; | |
405 | }; | |
406 | }; | |
407 | uart2_noflow_pins_a: uart2@1 { | |
408 | uart { | |
409 | sirf,pins = "uart2_nostreamctrlgrp"; | |
410 | sirf,function = "uart2_nostreamctrl"; | |
411 | }; | |
412 | }; | |
413 | spi0_pins_a: spi0@0 { | |
414 | spi { | |
415 | sirf,pins = "spi0grp"; | |
416 | sirf,function = "spi0"; | |
417 | }; | |
418 | }; | |
419 | spi1_pins_a: spi1@0 { | |
420 | spi { | |
421 | sirf,pins = "spi1grp"; | |
422 | sirf,function = "spi1"; | |
423 | }; | |
424 | }; | |
425 | i2c0_pins_a: i2c0@0 { | |
426 | i2c { | |
427 | sirf,pins = "i2c0grp"; | |
428 | sirf,function = "i2c0"; | |
429 | }; | |
430 | }; | |
431 | i2c1_pins_a: i2c1@0 { | |
432 | i2c { | |
433 | sirf,pins = "i2c1grp"; | |
434 | sirf,function = "i2c1"; | |
435 | }; | |
436 | }; | |
437 | pwm0_pins_a: pwm0@0 { | |
438 | pwm { | |
439 | sirf,pins = "pwm0grp"; | |
440 | sirf,function = "pwm0"; | |
441 | }; | |
442 | }; | |
443 | pwm1_pins_a: pwm1@0 { | |
444 | pwm { | |
445 | sirf,pins = "pwm1grp"; | |
446 | sirf,function = "pwm1"; | |
447 | }; | |
448 | }; | |
449 | pwm2_pins_a: pwm2@0 { | |
450 | pwm { | |
451 | sirf,pins = "pwm2grp"; | |
452 | sirf,function = "pwm2"; | |
453 | }; | |
454 | }; | |
455 | pwm3_pins_a: pwm3@0 { | |
456 | pwm { | |
457 | sirf,pins = "pwm3grp"; | |
458 | sirf,function = "pwm3"; | |
459 | }; | |
460 | }; | |
461 | pwm4_pins_a: pwm4@0 { | |
462 | pwm { | |
463 | sirf,pins = "pwm4grp"; | |
464 | sirf,function = "pwm4"; | |
465 | }; | |
466 | }; | |
467 | gps_pins_a: gps@0 { | |
468 | gps { | |
469 | sirf,pins = "gpsgrp"; | |
470 | sirf,function = "gps"; | |
471 | }; | |
472 | }; | |
473 | vip_pins_a: vip@0 { | |
474 | vip { | |
475 | sirf,pins = "vipgrp"; | |
476 | sirf,function = "vip"; | |
477 | }; | |
478 | }; | |
479 | sdmmc0_pins_a: sdmmc0@0 { | |
480 | sdmmc0 { | |
481 | sirf,pins = "sdmmc0grp"; | |
482 | sirf,function = "sdmmc0"; | |
483 | }; | |
484 | }; | |
485 | sdmmc1_pins_a: sdmmc1@0 { | |
486 | sdmmc1 { | |
487 | sirf,pins = "sdmmc1grp"; | |
488 | sirf,function = "sdmmc1"; | |
489 | }; | |
490 | }; | |
491 | sdmmc2_pins_a: sdmmc2@0 { | |
492 | sdmmc2 { | |
493 | sirf,pins = "sdmmc2grp"; | |
494 | sirf,function = "sdmmc2"; | |
495 | }; | |
496 | }; | |
497 | sdmmc2_nowp_pins_a: sdmmc2_nowp@0 { | |
498 | sdmmc2_nowp { | |
499 | sirf,pins = "sdmmc2_nowpgrp"; | |
500 | sirf,function = "sdmmc2_nowp"; | |
501 | }; | |
502 | }; | |
503 | sdmmc3_pins_a: sdmmc3@0 { | |
504 | sdmmc3 { | |
505 | sirf,pins = "sdmmc3grp"; | |
506 | sirf,function = "sdmmc3"; | |
507 | }; | |
508 | }; | |
509 | sdmmc5_pins_a: sdmmc5@0 { | |
510 | sdmmc5 { | |
511 | sirf,pins = "sdmmc5grp"; | |
512 | sirf,function = "sdmmc5"; | |
513 | }; | |
514 | }; | |
515 | i2s_pins_a: i2s@0 { | |
516 | i2s { | |
517 | sirf,pins = "i2sgrp"; | |
518 | sirf,function = "i2s"; | |
519 | }; | |
520 | }; | |
521 | i2s_no_din_pins_a: i2s_no_din@0 { | |
522 | i2s_no_din { | |
523 | sirf,pins = "i2s_no_dingrp"; | |
524 | sirf,function = "i2s_no_din"; | |
525 | }; | |
526 | }; | |
527 | i2s_6chn_pins_a: i2s_6chn@0 { | |
528 | i2s_6chn { | |
529 | sirf,pins = "i2s_6chngrp"; | |
530 | sirf,function = "i2s_6chn"; | |
531 | }; | |
532 | }; | |
533 | ac97_pins_a: ac97@0 { | |
534 | ac97 { | |
535 | sirf,pins = "ac97grp"; | |
536 | sirf,function = "ac97"; | |
537 | }; | |
538 | }; | |
539 | nand_pins_a: nand@0 { | |
540 | nand { | |
541 | sirf,pins = "nandgrp"; | |
542 | sirf,function = "nand"; | |
543 | }; | |
544 | }; | |
545 | usp0_pins_a: usp0@0 { | |
546 | usp0 { | |
547 | sirf,pins = "usp0grp"; | |
548 | sirf,function = "usp0"; | |
549 | }; | |
550 | }; | |
d58e9a02 QL |
551 | usp0_uart_nostreamctrl_pins_a: usp0@1 { |
552 | usp0 { | |
553 | sirf,pins = "usp0_uart_nostreamctrl_grp"; | |
554 | sirf,function = "usp0_uart_nostreamctrl"; | |
555 | }; | |
556 | }; | |
00954c1b RY |
557 | usp0_only_utfs_pins_a: usp0@2 { |
558 | usp0 { | |
559 | sirf,pins = "usp0_only_utfs_grp"; | |
560 | sirf,function = "usp0_only_utfs"; | |
561 | }; | |
562 | }; | |
563 | usp0_only_urfs_pins_a: usp0@3 { | |
564 | usp0 { | |
565 | sirf,pins = "usp0_only_urfs_grp"; | |
566 | sirf,function = "usp0_only_urfs"; | |
567 | }; | |
568 | }; | |
5fa2f9af BS |
569 | usp1_pins_a: usp1@0 { |
570 | usp1 { | |
571 | sirf,pins = "usp1grp"; | |
572 | sirf,function = "usp1"; | |
573 | }; | |
574 | }; | |
ec2b50ca QL |
575 | usp1_uart_nostreamctrl_pins_a: usp1@1 { |
576 | usp1 { | |
577 | sirf,pins = "usp1_uart_nostreamctrl_grp"; | |
578 | sirf,function = "usp1_uart_nostreamctrl"; | |
579 | }; | |
580 | }; | |
5fa2f9af BS |
581 | usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { |
582 | usb0_upli_drvbus { | |
583 | sirf,pins = "usb0_upli_drvbusgrp"; | |
584 | sirf,function = "usb0_upli_drvbus"; | |
585 | }; | |
586 | }; | |
587 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | |
588 | usb1_utmi_drvbus { | |
589 | sirf,pins = "usb1_utmi_drvbusgrp"; | |
590 | sirf,function = "usb1_utmi_drvbus"; | |
591 | }; | |
592 | }; | |
6a08a92e RW |
593 | usb1_dp_dn_pins_a: usb1_dp_dn@0 { |
594 | usb1_dp_dn { | |
595 | sirf,pins = "usb1_dp_dngrp"; | |
596 | sirf,function = "usb1_dp_dn"; | |
597 | }; | |
598 | }; | |
599 | uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { | |
600 | uart1_route_io_usb1 { | |
601 | sirf,pins = "uart1_route_io_usb1grp"; | |
602 | sirf,function = "uart1_route_io_usb1"; | |
603 | }; | |
604 | }; | |
5fa2f9af BS |
605 | warm_rst_pins_a: warm_rst@0 { |
606 | warm_rst { | |
607 | sirf,pins = "warm_rstgrp"; | |
608 | sirf,function = "warm_rst"; | |
609 | }; | |
610 | }; | |
611 | pulse_count_pins_a: pulse_count@0 { | |
612 | pulse_count { | |
613 | sirf,pins = "pulse_countgrp"; | |
614 | sirf,function = "pulse_count"; | |
615 | }; | |
616 | }; | |
c8078de8 BS |
617 | cko0_pins_a: cko0@0 { |
618 | cko0 { | |
619 | sirf,pins = "cko0grp"; | |
620 | sirf,function = "cko0"; | |
5fa2f9af BS |
621 | }; |
622 | }; | |
c8078de8 BS |
623 | cko1_pins_a: cko1@0 { |
624 | cko1 { | |
625 | sirf,pins = "cko1grp"; | |
626 | sirf,function = "cko1"; | |
5fa2f9af BS |
627 | }; |
628 | }; | |
629 | }; | |
630 | ||
631 | pwm@b0130000 { | |
632 | compatible = "sirf,prima2-pwm"; | |
633 | reg = <0xb0130000 0x10000>; | |
634 | clocks = <&clks 21>; | |
635 | }; | |
636 | ||
637 | efusesys@b0140000 { | |
638 | compatible = "sirf,prima2-efuse"; | |
639 | reg = <0xb0140000 0x10000>; | |
640 | clocks = <&clks 22>; | |
641 | }; | |
642 | ||
643 | pulsec@b0150000 { | |
644 | compatible = "sirf,prima2-pulsec"; | |
645 | reg = <0xb0150000 0x10000>; | |
646 | interrupts = <48>; | |
647 | clocks = <&clks 23>; | |
648 | }; | |
649 | ||
650 | pci-iobg { | |
651 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | |
652 | #address-cells = <1>; | |
653 | #size-cells = <1>; | |
654 | ranges = <0x56000000 0x56000000 0x1b00000>; | |
655 | ||
656 | sd0: sdhci@56000000 { | |
657 | cell-index = <0>; | |
658 | compatible = "sirf,prima2-sdhc"; | |
659 | reg = <0x56000000 0x100000>; | |
660 | interrupts = <38>; | |
661 | bus-width = <8>; | |
662 | clocks = <&clks 36>; | |
663 | }; | |
664 | ||
665 | sd1: sdhci@56100000 { | |
666 | cell-index = <1>; | |
667 | compatible = "sirf,prima2-sdhc"; | |
668 | reg = <0x56100000 0x100000>; | |
669 | interrupts = <38>; | |
670 | status = "disabled"; | |
7f97c303 | 671 | bus-width = <4>; |
5fa2f9af BS |
672 | clocks = <&clks 36>; |
673 | }; | |
674 | ||
675 | sd2: sdhci@56200000 { | |
676 | cell-index = <2>; | |
677 | compatible = "sirf,prima2-sdhc"; | |
678 | reg = <0x56200000 0x100000>; | |
679 | interrupts = <23>; | |
680 | status = "disabled"; | |
7f97c303 | 681 | bus-width = <4>; |
5fa2f9af BS |
682 | clocks = <&clks 37>; |
683 | }; | |
684 | ||
685 | sd3: sdhci@56300000 { | |
686 | cell-index = <3>; | |
687 | compatible = "sirf,prima2-sdhc"; | |
688 | reg = <0x56300000 0x100000>; | |
689 | interrupts = <23>; | |
690 | status = "disabled"; | |
7f97c303 | 691 | bus-width = <4>; |
5fa2f9af BS |
692 | clocks = <&clks 37>; |
693 | }; | |
694 | ||
695 | sd5: sdhci@56500000 { | |
696 | cell-index = <5>; | |
697 | compatible = "sirf,prima2-sdhc"; | |
698 | reg = <0x56500000 0x100000>; | |
699 | interrupts = <39>; | |
700 | status = "disabled"; | |
7f97c303 | 701 | bus-width = <4>; |
5fa2f9af BS |
702 | clocks = <&clks 38>; |
703 | }; | |
704 | ||
705 | pci-copy@57900000 { | |
706 | compatible = "sirf,prima2-pcicp"; | |
707 | reg = <0x57900000 0x100000>; | |
708 | interrupts = <40>; | |
709 | }; | |
710 | ||
711 | rom-interface@57a00000 { | |
712 | compatible = "sirf,prima2-romif"; | |
713 | reg = <0x57a00000 0x100000>; | |
714 | }; | |
715 | }; | |
716 | }; | |
717 | ||
718 | rtc-iobg { | |
e88b815e | 719 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; |
5fa2f9af BS |
720 | #address-cells = <1>; |
721 | #size-cells = <1>; | |
722 | reg = <0x80030000 0x10000>; | |
723 | ||
724 | gpsrtc@1000 { | |
725 | compatible = "sirf,prima2-gpsrtc"; | |
726 | reg = <0x1000 0x1000>; | |
727 | interrupts = <55 56 57>; | |
728 | }; | |
729 | ||
730 | sysrtc@2000 { | |
731 | compatible = "sirf,prima2-sysrtc"; | |
732 | reg = <0x2000 0x1000>; | |
733 | interrupts = <52 53 54>; | |
734 | }; | |
735 | ||
423ef791 XD |
736 | minigpsrtc@2000 { |
737 | compatible = "sirf,prima2-minigpsrtc"; | |
738 | reg = <0x2000 0x1000>; | |
739 | interrupts = <54>; | |
740 | }; | |
741 | ||
5fa2f9af BS |
742 | pwrc@3000 { |
743 | compatible = "sirf,prima2-pwrc"; | |
744 | reg = <0x3000 0x1000>; | |
745 | interrupts = <32>; | |
746 | }; | |
747 | }; | |
748 | ||
749 | uus-iobg { | |
750 | compatible = "simple-bus"; | |
751 | #address-cells = <1>; | |
752 | #size-cells = <1>; | |
753 | ranges = <0xb8000000 0xb8000000 0x40000>; | |
754 | ||
755 | usb0: usb@b00e0000 { | |
756 | compatible = "chipidea,ci13611a-prima2"; | |
757 | reg = <0xb8000000 0x10000>; | |
758 | interrupts = <10>; | |
759 | clocks = <&clks 40>; | |
760 | }; | |
761 | ||
762 | usb1: usb@b00f0000 { | |
763 | compatible = "chipidea,ci13611a-prima2"; | |
764 | reg = <0xb8010000 0x10000>; | |
765 | interrupts = <11>; | |
766 | clocks = <&clks 41>; | |
767 | }; | |
768 | ||
769 | security@b00f0000 { | |
770 | compatible = "sirf,prima2-security"; | |
771 | reg = <0xb8030000 0x10000>; | |
772 | interrupts = <42>; | |
773 | clocks = <&clks 7>; | |
774 | }; | |
775 | }; | |
776 | }; | |
777 | }; |