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ARM: dts: sirf: add lost minigpsrtc device node
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1/*
2 * DTS file for CSR SiRFatlas6 SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,atlas6";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 reg = <0x0>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
25 i-cache-size = <32768>;
26 /* from bootloader */
27 timebase-frequency = <0>;
28 bus-frequency = <0>;
29 clock-frequency = <0>;
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30 clocks = <&clks 12>;
31 operating-points = <
32 /* kHz uV */
33 200000 1025000
34 400000 1025000
35 600000 1050000
36 800000 1100000
37 >;
38 clock-latency = <150000>;
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39 };
40 };
41
42 axi {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges = <0x40000000 0x40000000 0x80000000>;
47
48 intc: interrupt-controller@80020000 {
49 #interrupt-cells = <1>;
50 interrupt-controller;
51 compatible = "sirf,prima2-intc";
52 reg = <0x80020000 0x1000>;
53 };
54
55 sys-iobg {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges = <0x88000000 0x88000000 0x40000>;
60
61 clks: clock-controller@88000000 {
62 compatible = "sirf,atlas6-clkc";
63 reg = <0x88000000 0x1000>;
64 interrupts = <3>;
65 #clock-cells = <1>;
66 };
67
68 reset-controller@88010000 {
69 compatible = "sirf,prima2-rstc";
70 reg = <0x88010000 0x1000>;
71 };
72
73 rsc-controller@88020000 {
74 compatible = "sirf,prima2-rsc";
75 reg = <0x88020000 0x1000>;
76 };
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77
78 cphifbg@88030000 {
79 compatible = "sirf,prima2-cphifbg";
80 reg = <0x88030000 0x1000>;
794f8b21 81 clocks = <&clks 42>;
0671840c 82 };
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83 };
84
85 mem-iobg {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges = <0x90000000 0x90000000 0x10000>;
90
91 memory-controller@90000000 {
92 compatible = "sirf,prima2-memc";
5fadea22 93 reg = <0x90000000 0x2000>;
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94 interrupts = <27>;
95 clocks = <&clks 5>;
96 };
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97
98 memc-monitor {
99 compatible = "sirf,prima2-memcmon";
100 reg = <0x90002000 0x200>;
101 interrupts = <4>;
102 clocks = <&clks 32>;
103 };
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104 };
105
106 disp-iobg {
107 compatible = "simple-bus";
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0x90010000 0x90010000 0x30000>;
111
112 lcd@90010000 {
113 compatible = "sirf,prima2-lcd";
114 reg = <0x90010000 0x20000>;
115 interrupts = <30>;
116 clocks = <&clks 34>;
117 display=<&display>;
118 /* later transfer to pwm */
119 bl-gpio = <&gpio 7 0>;
120 default-panel = <&panel0>;
121 };
122
123 vpp@90020000 {
124 compatible = "sirf,prima2-vpp";
125 reg = <0x90020000 0x10000>;
126 interrupts = <31>;
127 clocks = <&clks 35>;
128 };
129 };
130
131 graphics-iobg {
132 compatible = "simple-bus";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 ranges = <0x98000000 0x98000000 0x8000000>;
136
137 graphics@98000000 {
138 compatible = "powervr,sgx510";
139 reg = <0x98000000 0x8000000>;
140 interrupts = <6>;
141 clocks = <&clks 32>;
142 };
143 };
144
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145 graphics2d-iobg {
146 compatible = "simple-bus";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 ranges = <0xa0000000 0xa0000000 0x8000000>;
150
151 ble@a0000000 {
152 compatible = "sirf,atlas6-ble";
153 reg = <0xa0000000 0x2000>;
154 interrupts = <5>;
155 clocks = <&clks 33>;
156 };
157 };
158
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159 dsp-iobg {
160 compatible = "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges = <0xa8000000 0xa8000000 0x2000000>;
164
165 dspif@a8000000 {
166 compatible = "sirf,prima2-dspif";
167 reg = <0xa8000000 0x10000>;
168 interrupts = <9>;
169 };
170
171 gps@a8010000 {
172 compatible = "sirf,prima2-gps";
173 reg = <0xa8010000 0x10000>;
174 interrupts = <7>;
175 clocks = <&clks 9>;
176 };
177
178 dsp@a9000000 {
179 compatible = "sirf,prima2-dsp";
180 reg = <0xa9000000 0x1000000>;
181 interrupts = <8>;
182 clocks = <&clks 8>;
183 };
184 };
185
186 peri-iobg {
187 compatible = "simple-bus";
188 #address-cells = <1>;
189 #size-cells = <1>;
190 ranges = <0xb0000000 0xb0000000 0x180000>,
191 <0x56000000 0x56000000 0x1b00000>;
192
193 timer@b0020000 {
194 compatible = "sirf,prima2-tick";
195 reg = <0xb0020000 0x1000>;
196 interrupts = <0>;
197 };
198
199 nand@b0030000 {
200 compatible = "sirf,prima2-nand";
201 reg = <0xb0030000 0x10000>;
202 interrupts = <41>;
203 clocks = <&clks 26>;
204 };
205
206 audio@b0040000 {
207 compatible = "sirf,prima2-audio";
208 reg = <0xb0040000 0x10000>;
209 interrupts = <35>;
210 clocks = <&clks 27>;
211 };
212
213 uart0: uart@b0050000 {
214 cell-index = <0>;
215 compatible = "sirf,prima2-uart";
216 reg = <0xb0050000 0x1000>;
217 interrupts = <17>;
218 fifosize = <128>;
219 clocks = <&clks 13>;
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220 sirf,uart-dma-rx-channel = <21>;
221 sirf,uart-dma-tx-channel = <2>;
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222 };
223
224 uart1: uart@b0060000 {
225 cell-index = <1>;
226 compatible = "sirf,prima2-uart";
227 reg = <0xb0060000 0x1000>;
228 interrupts = <18>;
229 fifosize = <32>;
230 clocks = <&clks 14>;
231 };
232
233 uart2: uart@b0070000 {
234 cell-index = <2>;
235 compatible = "sirf,prima2-uart";
236 reg = <0xb0070000 0x1000>;
237 interrupts = <19>;
238 fifosize = <128>;
239 clocks = <&clks 15>;
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240 sirf,uart-dma-rx-channel = <6>;
241 sirf,uart-dma-tx-channel = <7>;
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242 };
243
244 usp0: usp@b0080000 {
245 cell-index = <0>;
246 compatible = "sirf,prima2-usp";
247 reg = <0xb0080000 0x10000>;
248 interrupts = <20>;
a1369978 249 fifosize = <128>;
5fa2f9af 250 clocks = <&clks 28>;
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251 sirf,usp-dma-rx-channel = <17>;
252 sirf,usp-dma-tx-channel = <18>;
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253 };
254
255 usp1: usp@b0090000 {
256 cell-index = <1>;
257 compatible = "sirf,prima2-usp";
258 reg = <0xb0090000 0x10000>;
259 interrupts = <21>;
a1369978 260 fifosize = <128>;
5fa2f9af 261 clocks = <&clks 29>;
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262 sirf,usp-dma-rx-channel = <14>;
263 sirf,usp-dma-tx-channel = <15>;
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264 };
265
266 dmac0: dma-controller@b00b0000 {
267 cell-index = <0>;
268 compatible = "sirf,prima2-dmac";
269 reg = <0xb00b0000 0x10000>;
270 interrupts = <12>;
271 clocks = <&clks 24>;
272 };
273
274 dmac1: dma-controller@b0160000 {
275 cell-index = <1>;
276 compatible = "sirf,prima2-dmac";
277 reg = <0xb0160000 0x10000>;
278 interrupts = <13>;
279 clocks = <&clks 25>;
280 };
281
282 vip@b00C0000 {
283 compatible = "sirf,prima2-vip";
284 reg = <0xb00C0000 0x10000>;
285 clocks = <&clks 31>;
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286 interrupts = <14>;
287 sirf,vip-dma-rx-channel = <16>;
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288 };
289
290 spi0: spi@b00d0000 {
291 cell-index = <0>;
292 compatible = "sirf,prima2-spi";
293 reg = <0xb00d0000 0x10000>;
294 interrupts = <15>;
295 sirf,spi-num-chipselects = <1>;
296 cs-gpios = <&gpio 0 0>;
297 sirf,spi-dma-rx-channel = <25>;
298 sirf,spi-dma-tx-channel = <20>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 clocks = <&clks 19>;
302 status = "disabled";
303 };
304
305 spi1: spi@b0170000 {
306 cell-index = <1>;
307 compatible = "sirf,prima2-spi";
308 reg = <0xb0170000 0x10000>;
309 interrupts = <16>;
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310 sirf,spi-num-chipselects = <1>;
311 sirf,spi-dma-rx-channel = <12>;
312 sirf,spi-dma-tx-channel = <13>;
313 #address-cells = <1>;
314 #size-cells = <0>;
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315 clocks = <&clks 20>;
316 status = "disabled";
317 };
318
319 i2c0: i2c@b00e0000 {
320 cell-index = <0>;
321 compatible = "sirf,prima2-i2c";
322 reg = <0xb00e0000 0x10000>;
323 interrupts = <24>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 clocks = <&clks 17>;
327 };
328
329 i2c1: i2c@b00f0000 {
330 cell-index = <1>;
331 compatible = "sirf,prima2-i2c";
332 reg = <0xb00f0000 0x10000>;
333 interrupts = <25>;
334 #address-cells = <1>;
335 #size-cells = <0>;
336 clocks = <&clks 18>;
337 };
338
339 tsc@b0110000 {
340 compatible = "sirf,prima2-tsc";
341 reg = <0xb0110000 0x10000>;
342 interrupts = <33>;
343 clocks = <&clks 16>;
344 };
345
346 gpio: pinctrl@b0120000 {
347 #gpio-cells = <2>;
348 #interrupt-cells = <2>;
349 compatible = "sirf,atlas6-pinctrl";
350 reg = <0xb0120000 0x10000>;
351 interrupts = <43 44 45 46 47>;
352 gpio-controller;
353 interrupt-controller;
354
355 lcd_16pins_a: lcd0@0 {
356 lcd {
357 sirf,pins = "lcd_16bitsgrp";
358 sirf,function = "lcd_16bits";
359 };
360 };
361 lcd_18pins_a: lcd0@1 {
362 lcd {
363 sirf,pins = "lcd_18bitsgrp";
364 sirf,function = "lcd_18bits";
365 };
366 };
367 lcd_24pins_a: lcd0@2 {
368 lcd {
369 sirf,pins = "lcd_24bitsgrp";
370 sirf,function = "lcd_24bits";
371 };
372 };
373 lcdrom_pins_a: lcdrom0@0 {
374 lcd {
375 sirf,pins = "lcdromgrp";
376 sirf,function = "lcdrom";
377 };
378 };
379 uart0_pins_a: uart0@0 {
380 uart {
381 sirf,pins = "uart0grp";
382 sirf,function = "uart0";
383 };
384 };
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QL
385 uart0_noflow_pins_a: uart0@1 {
386 uart {
387 sirf,pins = "uart0_nostreamctrlgrp";
388 sirf,function = "uart0_nostreamctrl";
389 };
390 };
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391 uart1_pins_a: uart1@0 {
392 uart {
393 sirf,pins = "uart1grp";
394 sirf,function = "uart1";
395 };
396 };
397 uart2_pins_a: uart2@0 {
398 uart {
399 sirf,pins = "uart2grp";
400 sirf,function = "uart2";
401 };
402 };
403 uart2_noflow_pins_a: uart2@1 {
404 uart {
405 sirf,pins = "uart2_nostreamctrlgrp";
406 sirf,function = "uart2_nostreamctrl";
407 };
408 };
409 spi0_pins_a: spi0@0 {
410 spi {
411 sirf,pins = "spi0grp";
412 sirf,function = "spi0";
413 };
414 };
415 spi1_pins_a: spi1@0 {
416 spi {
417 sirf,pins = "spi1grp";
418 sirf,function = "spi1";
419 };
420 };
421 i2c0_pins_a: i2c0@0 {
422 i2c {
423 sirf,pins = "i2c0grp";
424 sirf,function = "i2c0";
425 };
426 };
427 i2c1_pins_a: i2c1@0 {
428 i2c {
429 sirf,pins = "i2c1grp";
430 sirf,function = "i2c1";
431 };
432 };
433 pwm0_pins_a: pwm0@0 {
434 pwm {
435 sirf,pins = "pwm0grp";
436 sirf,function = "pwm0";
437 };
438 };
439 pwm1_pins_a: pwm1@0 {
440 pwm {
441 sirf,pins = "pwm1grp";
442 sirf,function = "pwm1";
443 };
444 };
445 pwm2_pins_a: pwm2@0 {
446 pwm {
447 sirf,pins = "pwm2grp";
448 sirf,function = "pwm2";
449 };
450 };
451 pwm3_pins_a: pwm3@0 {
452 pwm {
453 sirf,pins = "pwm3grp";
454 sirf,function = "pwm3";
455 };
456 };
457 pwm4_pins_a: pwm4@0 {
458 pwm {
459 sirf,pins = "pwm4grp";
460 sirf,function = "pwm4";
461 };
462 };
463 gps_pins_a: gps@0 {
464 gps {
465 sirf,pins = "gpsgrp";
466 sirf,function = "gps";
467 };
468 };
469 vip_pins_a: vip@0 {
470 vip {
471 sirf,pins = "vipgrp";
472 sirf,function = "vip";
473 };
474 };
475 sdmmc0_pins_a: sdmmc0@0 {
476 sdmmc0 {
477 sirf,pins = "sdmmc0grp";
478 sirf,function = "sdmmc0";
479 };
480 };
481 sdmmc1_pins_a: sdmmc1@0 {
482 sdmmc1 {
483 sirf,pins = "sdmmc1grp";
484 sirf,function = "sdmmc1";
485 };
486 };
487 sdmmc2_pins_a: sdmmc2@0 {
488 sdmmc2 {
489 sirf,pins = "sdmmc2grp";
490 sirf,function = "sdmmc2";
491 };
492 };
493 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
494 sdmmc2_nowp {
495 sirf,pins = "sdmmc2_nowpgrp";
496 sirf,function = "sdmmc2_nowp";
497 };
498 };
499 sdmmc3_pins_a: sdmmc3@0 {
500 sdmmc3 {
501 sirf,pins = "sdmmc3grp";
502 sirf,function = "sdmmc3";
503 };
504 };
505 sdmmc5_pins_a: sdmmc5@0 {
506 sdmmc5 {
507 sirf,pins = "sdmmc5grp";
508 sirf,function = "sdmmc5";
509 };
510 };
511 i2s_pins_a: i2s@0 {
512 i2s {
513 sirf,pins = "i2sgrp";
514 sirf,function = "i2s";
515 };
516 };
517 i2s_no_din_pins_a: i2s_no_din@0 {
518 i2s_no_din {
519 sirf,pins = "i2s_no_dingrp";
520 sirf,function = "i2s_no_din";
521 };
522 };
523 i2s_6chn_pins_a: i2s_6chn@0 {
524 i2s_6chn {
525 sirf,pins = "i2s_6chngrp";
526 sirf,function = "i2s_6chn";
527 };
528 };
529 ac97_pins_a: ac97@0 {
530 ac97 {
531 sirf,pins = "ac97grp";
532 sirf,function = "ac97";
533 };
534 };
535 nand_pins_a: nand@0 {
536 nand {
537 sirf,pins = "nandgrp";
538 sirf,function = "nand";
539 };
540 };
541 usp0_pins_a: usp0@0 {
542 usp0 {
543 sirf,pins = "usp0grp";
544 sirf,function = "usp0";
545 };
546 };
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QL
547 usp0_uart_nostreamctrl_pins_a: usp0@1 {
548 usp0 {
549 sirf,pins = "usp0_uart_nostreamctrl_grp";
550 sirf,function = "usp0_uart_nostreamctrl";
551 };
552 };
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553 usp1_pins_a: usp1@0 {
554 usp1 {
555 sirf,pins = "usp1grp";
556 sirf,function = "usp1";
557 };
558 };
559 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
560 usb0_upli_drvbus {
561 sirf,pins = "usb0_upli_drvbusgrp";
562 sirf,function = "usb0_upli_drvbus";
563 };
564 };
565 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
566 usb1_utmi_drvbus {
567 sirf,pins = "usb1_utmi_drvbusgrp";
568 sirf,function = "usb1_utmi_drvbus";
569 };
570 };
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571 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
572 usb1_dp_dn {
573 sirf,pins = "usb1_dp_dngrp";
574 sirf,function = "usb1_dp_dn";
575 };
576 };
577 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
578 uart1_route_io_usb1 {
579 sirf,pins = "uart1_route_io_usb1grp";
580 sirf,function = "uart1_route_io_usb1";
581 };
582 };
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583 warm_rst_pins_a: warm_rst@0 {
584 warm_rst {
585 sirf,pins = "warm_rstgrp";
586 sirf,function = "warm_rst";
587 };
588 };
589 pulse_count_pins_a: pulse_count@0 {
590 pulse_count {
591 sirf,pins = "pulse_countgrp";
592 sirf,function = "pulse_count";
593 };
594 };
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595 cko0_pins_a: cko0@0 {
596 cko0 {
597 sirf,pins = "cko0grp";
598 sirf,function = "cko0";
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599 };
600 };
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601 cko1_pins_a: cko1@0 {
602 cko1 {
603 sirf,pins = "cko1grp";
604 sirf,function = "cko1";
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605 };
606 };
607 };
608
609 pwm@b0130000 {
610 compatible = "sirf,prima2-pwm";
611 reg = <0xb0130000 0x10000>;
612 clocks = <&clks 21>;
613 };
614
615 efusesys@b0140000 {
616 compatible = "sirf,prima2-efuse";
617 reg = <0xb0140000 0x10000>;
618 clocks = <&clks 22>;
619 };
620
621 pulsec@b0150000 {
622 compatible = "sirf,prima2-pulsec";
623 reg = <0xb0150000 0x10000>;
624 interrupts = <48>;
625 clocks = <&clks 23>;
626 };
627
628 pci-iobg {
629 compatible = "sirf,prima2-pciiobg", "simple-bus";
630 #address-cells = <1>;
631 #size-cells = <1>;
632 ranges = <0x56000000 0x56000000 0x1b00000>;
633
634 sd0: sdhci@56000000 {
635 cell-index = <0>;
636 compatible = "sirf,prima2-sdhc";
637 reg = <0x56000000 0x100000>;
638 interrupts = <38>;
639 bus-width = <8>;
640 clocks = <&clks 36>;
641 };
642
643 sd1: sdhci@56100000 {
644 cell-index = <1>;
645 compatible = "sirf,prima2-sdhc";
646 reg = <0x56100000 0x100000>;
647 interrupts = <38>;
648 status = "disabled";
7f97c303 649 bus-width = <4>;
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BS
650 clocks = <&clks 36>;
651 };
652
653 sd2: sdhci@56200000 {
654 cell-index = <2>;
655 compatible = "sirf,prima2-sdhc";
656 reg = <0x56200000 0x100000>;
657 interrupts = <23>;
658 status = "disabled";
7f97c303 659 bus-width = <4>;
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BS
660 clocks = <&clks 37>;
661 };
662
663 sd3: sdhci@56300000 {
664 cell-index = <3>;
665 compatible = "sirf,prima2-sdhc";
666 reg = <0x56300000 0x100000>;
667 interrupts = <23>;
668 status = "disabled";
7f97c303 669 bus-width = <4>;
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BS
670 clocks = <&clks 37>;
671 };
672
673 sd5: sdhci@56500000 {
674 cell-index = <5>;
675 compatible = "sirf,prima2-sdhc";
676 reg = <0x56500000 0x100000>;
677 interrupts = <39>;
678 status = "disabled";
7f97c303 679 bus-width = <4>;
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BS
680 clocks = <&clks 38>;
681 };
682
683 pci-copy@57900000 {
684 compatible = "sirf,prima2-pcicp";
685 reg = <0x57900000 0x100000>;
686 interrupts = <40>;
687 };
688
689 rom-interface@57a00000 {
690 compatible = "sirf,prima2-romif";
691 reg = <0x57a00000 0x100000>;
692 };
693 };
694 };
695
696 rtc-iobg {
e88b815e 697 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
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BS
698 #address-cells = <1>;
699 #size-cells = <1>;
700 reg = <0x80030000 0x10000>;
701
702 gpsrtc@1000 {
703 compatible = "sirf,prima2-gpsrtc";
704 reg = <0x1000 0x1000>;
705 interrupts = <55 56 57>;
706 };
707
708 sysrtc@2000 {
709 compatible = "sirf,prima2-sysrtc";
710 reg = <0x2000 0x1000>;
711 interrupts = <52 53 54>;
712 };
713
423ef791
XD
714 minigpsrtc@2000 {
715 compatible = "sirf,prima2-minigpsrtc";
716 reg = <0x2000 0x1000>;
717 interrupts = <54>;
718 };
719
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720 pwrc@3000 {
721 compatible = "sirf,prima2-pwrc";
722 reg = <0x3000 0x1000>;
723 interrupts = <32>;
724 };
725 };
726
727 uus-iobg {
728 compatible = "simple-bus";
729 #address-cells = <1>;
730 #size-cells = <1>;
731 ranges = <0xb8000000 0xb8000000 0x40000>;
732
733 usb0: usb@b00e0000 {
734 compatible = "chipidea,ci13611a-prima2";
735 reg = <0xb8000000 0x10000>;
736 interrupts = <10>;
737 clocks = <&clks 40>;
738 };
739
740 usb1: usb@b00f0000 {
741 compatible = "chipidea,ci13611a-prima2";
742 reg = <0xb8010000 0x10000>;
743 interrupts = <11>;
744 clocks = <&clks 41>;
745 };
746
747 security@b00f0000 {
748 compatible = "sirf,prima2-security";
749 reg = <0xb8030000 0x10000>;
750 interrupts = <42>;
751 clocks = <&clks 7>;
752 };
753 };
754 };
755};