[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / atlas6.dtsi

/*
 * DTS file for CSR SiRFatlas6 SoC
 *
 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

/include/ "skeleton.dtsi"
/ {
	compatible = "sirf,atlas6";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			/* from bootloader */
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	axi {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x40000000 0x40000000 0x80000000>;

		intc: interrupt-controller@80020000 {
			#interrupt-cells = <1>;
			interrupt-controller;
			compatible = "sirf,prima2-intc";
			reg = <0x80020000 0x1000>;
		};

		sys-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x88000000 0x88000000 0x40000>;

			clks: clock-controller@88000000 {
				compatible = "sirf,atlas6-clkc";
				reg = <0x88000000 0x1000>;
				interrupts = <3>;
				#clock-cells = <1>;
			};

			reset-controller@88010000 {
				compatible = "sirf,prima2-rstc";
				reg = <0x88010000 0x1000>;
			};

			rsc-controller@88020000 {
				compatible = "sirf,prima2-rsc";
				reg = <0x88020000 0x1000>;
			};
		};

		mem-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x90000000 0x90000000 0x10000>;

			memory-controller@90000000 {
				compatible = "sirf,prima2-memc";
				reg = <0x90000000 0x10000>;
				interrupts = <27>;
				clocks = <&clks 5>;
			};
		};

		disp-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x90010000 0x90010000 0x30000>;

			lcd@90010000 {
				compatible = "sirf,prima2-lcd";
				reg = <0x90010000 0x20000>;
				interrupts = <30>;
				clocks = <&clks 34>;
				display=<&display>;
				/* later transfer to pwm */
				bl-gpio = <&gpio 7 0>;
				default-panel = <&panel0>;
			};

			vpp@90020000 {
				compatible = "sirf,prima2-vpp";
				reg = <0x90020000 0x10000>;
				interrupts = <31>;
				clocks = <&clks 35>;
			};
		};

		graphics-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x98000000 0x98000000 0x8000000>;

			graphics@98000000 {
				compatible = "powervr,sgx510";
				reg = <0x98000000 0x8000000>;
				interrupts = <6>;
				clocks = <&clks 32>;
			};
		};

		dsp-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0xa8000000 0xa8000000 0x2000000>;

			dspif@a8000000 {
				compatible = "sirf,prima2-dspif";
				reg = <0xa8000000 0x10000>;
				interrupts = <9>;
			};

			gps@a8010000 {
				compatible = "sirf,prima2-gps";
				reg = <0xa8010000 0x10000>;
				interrupts = <7>;
				clocks = <&clks 9>;
			};

			dsp@a9000000 {
				compatible = "sirf,prima2-dsp";
				reg = <0xa9000000 0x1000000>;
				interrupts = <8>;
				clocks = <&clks 8>;
			};
		};

		peri-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0xb0000000 0xb0000000 0x180000>,
			       <0x56000000 0x56000000 0x1b00000>;

			timer@b0020000 {
				compatible = "sirf,prima2-tick";
				reg = <0xb0020000 0x1000>;
				interrupts = <0>;
			};

			nand@b0030000 {
				compatible = "sirf,prima2-nand";
				reg = <0xb0030000 0x10000>;
				interrupts = <41>;
				clocks = <&clks 26>;
			};

			audio@b0040000 {
				compatible = "sirf,prima2-audio";
				reg = <0xb0040000 0x10000>;
				interrupts = <35>;
				clocks = <&clks 27>;
			};

			uart0: uart@b0050000 {
				cell-index = <0>;
				compatible = "sirf,prima2-uart";
				reg = <0xb0050000 0x1000>;
				interrupts = <17>;
				fifosize = <128>;
				clocks = <&clks 13>;
			};

			uart1: uart@b0060000 {
				cell-index = <1>;
				compatible = "sirf,prima2-uart";
				reg = <0xb0060000 0x1000>;
				interrupts = <18>;
				fifosize = <32>;
				clocks = <&clks 14>;
			};

			uart2: uart@b0070000 {
				cell-index = <2>;
				compatible = "sirf,prima2-uart";
				reg = <0xb0070000 0x1000>;
				interrupts = <19>;
				fifosize = <128>;
				clocks = <&clks 15>;
			};

			usp0: usp@b0080000 {
				cell-index = <0>;
				compatible = "sirf,prima2-usp";
				reg = <0xb0080000 0x10000>;
				interrupts = <20>;
				clocks = <&clks 28>;
			};

			usp1: usp@b0090000 {
				cell-index = <1>;
				compatible = "sirf,prima2-usp";
				reg = <0xb0090000 0x10000>;
				interrupts = <21>;
				clocks = <&clks 29>;
			};

			dmac0: dma-controller@b00b0000 {
				cell-index = <0>;
				compatible = "sirf,prima2-dmac";
				reg = <0xb00b0000 0x10000>;
				interrupts = <12>;
				clocks = <&clks 24>;
			};

			dmac1: dma-controller@b0160000 {
				cell-index = <1>;
				compatible = "sirf,prima2-dmac";
				reg = <0xb0160000 0x10000>;
				interrupts = <13>;
				clocks = <&clks 25>;
			};

			vip@b00C0000 {
				compatible = "sirf,prima2-vip";
				reg = <0xb00C0000 0x10000>;
				clocks = <&clks 31>;
			};

			spi0: spi@b00d0000 {
				cell-index = <0>;
				compatible = "sirf,prima2-spi";
				reg = <0xb00d0000 0x10000>;
				interrupts = <15>;
				sirf,spi-num-chipselects = <1>;
				cs-gpios = <&gpio 0 0>;
				sirf,spi-dma-rx-channel = <25>;
				sirf,spi-dma-tx-channel = <20>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clks 19>;
				status = "disabled";
			};

			spi1: spi@b0170000 {
				cell-index = <1>;
				compatible = "sirf,prima2-spi";
				reg = <0xb0170000 0x10000>;
				interrupts = <16>;
				clocks = <&clks 20>;
				status = "disabled";
			};

			i2c0: i2c@b00e0000 {
				cell-index = <0>;
				compatible = "sirf,prima2-i2c";
				reg = <0xb00e0000 0x10000>;
				interrupts = <24>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clks 17>;
			};

			i2c1: i2c@b00f0000 {
				cell-index = <1>;
				compatible = "sirf,prima2-i2c";
				reg = <0xb00f0000 0x10000>;
				interrupts = <25>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clks 18>;
			};

			tsc@b0110000 {
				compatible = "sirf,prima2-tsc";
				reg = <0xb0110000 0x10000>;
				interrupts = <33>;
				clocks = <&clks 16>;
			};

			gpio: pinctrl@b0120000 {
				#gpio-cells = <2>;
				#interrupt-cells = <2>;
				compatible = "sirf,atlas6-pinctrl";
				reg = <0xb0120000 0x10000>;
				interrupts = <43 44 45 46 47>;
				gpio-controller;
				interrupt-controller;

				lcd_16pins_a: lcd0@0 {
					lcd {
						sirf,pins = "lcd_16bitsgrp";
						sirf,function = "lcd_16bits";
					};
				};
				lcd_18pins_a: lcd0@1 {
					lcd {
						sirf,pins = "lcd_18bitsgrp";
						sirf,function = "lcd_18bits";
					};
				};
				lcd_24pins_a: lcd0@2 {
					lcd {
						sirf,pins = "lcd_24bitsgrp";
						sirf,function = "lcd_24bits";
					};
				};
				lcdrom_pins_a: lcdrom0@0 {
					lcd {
						sirf,pins = "lcdromgrp";
						sirf,function = "lcdrom";
					};
				};
				uart0_pins_a: uart0@0 {
					uart {
						sirf,pins = "uart0grp";
						sirf,function = "uart0";
					};
				};
				uart0_noflow_pins_a: uart0@1 {
					uart {
						sirf,pins = "uart0_nostreamctrlgrp";
						sirf,function = "uart0_nostreamctrl";
					};
				};
				uart1_pins_a: uart1@0 {
					uart {
						sirf,pins = "uart1grp";
						sirf,function = "uart1";
					};
				};
				uart2_pins_a: uart2@0 {
					uart {
						sirf,pins = "uart2grp";
						sirf,function = "uart2";
					};
				};
				uart2_noflow_pins_a: uart2@1 {
					uart {
						sirf,pins = "uart2_nostreamctrlgrp";
						sirf,function = "uart2_nostreamctrl";
					};
				};
				spi0_pins_a: spi0@0 {
					spi {
						sirf,pins = "spi0grp";
						sirf,function = "spi0";
					};
				};
				spi1_pins_a: spi1@0 {
					spi {
						sirf,pins = "spi1grp";
						sirf,function = "spi1";
					};
				};
				i2c0_pins_a: i2c0@0 {
					i2c {
						sirf,pins = "i2c0grp";
						sirf,function = "i2c0";
					};
				};
				i2c1_pins_a: i2c1@0 {
					i2c {
						sirf,pins = "i2c1grp";
						sirf,function = "i2c1";
					};
				};
                                pwm0_pins_a: pwm0@0 {
                                        pwm {
                                                sirf,pins = "pwm0grp";
                                                sirf,function = "pwm0";
                                        };
                                };
                                pwm1_pins_a: pwm1@0 {
                                        pwm {
                                                sirf,pins = "pwm1grp";
                                                sirf,function = "pwm1";
                                        };
                                };
                                pwm2_pins_a: pwm2@0 {
                                        pwm {
                                                sirf,pins = "pwm2grp";
                                                sirf,function = "pwm2";
                                        };
                                };
                                pwm3_pins_a: pwm3@0 {
                                        pwm {
                                                sirf,pins = "pwm3grp";
                                                sirf,function = "pwm3";
                                        };
                                };
				pwm4_pins_a: pwm4@0 {
                                        pwm {
                                                sirf,pins = "pwm4grp";
                                                sirf,function = "pwm4";
                                        };
                                };
                                gps_pins_a: gps@0 {
                                        gps {
                                                sirf,pins = "gpsgrp";
                                                sirf,function = "gps";
                                        };
                                };
                                vip_pins_a: vip@0 {
                                        vip {
                                                sirf,pins = "vipgrp";
                                                sirf,function = "vip";
                                        };
                                };
                                sdmmc0_pins_a: sdmmc0@0 {
                                        sdmmc0 {
                                                sirf,pins = "sdmmc0grp";
                                                sirf,function = "sdmmc0";
                                        };
                                };
                                sdmmc1_pins_a: sdmmc1@0 {
                                        sdmmc1 {
                                                sirf,pins = "sdmmc1grp";
                                                sirf,function = "sdmmc1";
                                        };
                                };
                                sdmmc2_pins_a: sdmmc2@0 {
                                        sdmmc2 {
                                                sirf,pins = "sdmmc2grp";
                                                sirf,function = "sdmmc2";
                                        };
                                };
				sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
                                        sdmmc2_nowp {
                                                sirf,pins = "sdmmc2_nowpgrp";
                                                sirf,function = "sdmmc2_nowp";
                                        };
                                };
                                sdmmc3_pins_a: sdmmc3@0 {
                                        sdmmc3 {
                                                sirf,pins = "sdmmc3grp";
                                                sirf,function = "sdmmc3";
                                        };
                                };
                                sdmmc5_pins_a: sdmmc5@0 {
                                        sdmmc5 {
                                                sirf,pins = "sdmmc5grp";
                                                sirf,function = "sdmmc5";
                                        };
                                };
                                i2s_pins_a: i2s@0 {
                                        i2s {
                                                sirf,pins = "i2sgrp";
                                                sirf,function = "i2s";
                                        };
                                };
				i2s_no_din_pins_a: i2s_no_din@0 {
                                        i2s_no_din {
                                                sirf,pins = "i2s_no_dingrp";
                                                sirf,function = "i2s_no_din";
                                        };
                                };
				i2s_6chn_pins_a: i2s_6chn@0 {
                                        i2s_6chn {
                                                sirf,pins = "i2s_6chngrp";
                                                sirf,function = "i2s_6chn";
                                        };
                                };
                                ac97_pins_a: ac97@0 {
                                        ac97 {
                                                sirf,pins = "ac97grp";
                                                sirf,function = "ac97";
                                        };
                                };
                                nand_pins_a: nand@0 {
                                        nand {
                                                sirf,pins = "nandgrp";
                                                sirf,function = "nand";
                                        };
                                };
                                usp0_pins_a: usp0@0 {
                                        usp0 {
                                                sirf,pins = "usp0grp";
                                                sirf,function = "usp0";
                                        };
                                };
				usp0_uart_nostreamctrl_pins_a: usp0@1 {
                                        usp0 {
                                                sirf,pins = "usp0_uart_nostreamctrl_grp";
                                                sirf,function = "usp0_uart_nostreamctrl";
                                        };
                                };
                                usp1_pins_a: usp1@0 {
                                        usp1 {
                                                sirf,pins = "usp1grp";
                                                sirf,function = "usp1";
                                        };
                                };
                                usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
                                        usb0_upli_drvbus {
                                                sirf,pins = "usb0_upli_drvbusgrp";
                                                sirf,function = "usb0_upli_drvbus";
                                        };
                                };
                                usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
                                        usb1_utmi_drvbus {
                                                sirf,pins = "usb1_utmi_drvbusgrp";
                                                sirf,function = "usb1_utmi_drvbus";
                                        };
                                };
                                warm_rst_pins_a: warm_rst@0 {
                                        warm_rst {
                                                sirf,pins = "warm_rstgrp";
                                                sirf,function = "warm_rst";
                                        };
                                };
                                pulse_count_pins_a: pulse_count@0 {
                                        pulse_count {
                                                sirf,pins = "pulse_countgrp";
                                                sirf,function = "pulse_count";
                                        };
                                };
                                cko0_pins_a: cko0@0 {
                                        cko0 {
                                                sirf,pins = "cko0grp";
                                                sirf,function = "cko0";
                                        };
                                };
                                cko1_pins_a: cko1@0 {
                                        cko1 {
                                                sirf,pins = "cko1grp";
                                                sirf,function = "cko1";
                                        };
                                };
			};

			pwm@b0130000 {
				compatible = "sirf,prima2-pwm";
				reg = <0xb0130000 0x10000>;
				clocks = <&clks 21>;
			};

			efusesys@b0140000 {
				compatible = "sirf,prima2-efuse";
				reg = <0xb0140000 0x10000>;
				clocks = <&clks 22>;
			};

			pulsec@b0150000 {
				compatible = "sirf,prima2-pulsec";
				reg = <0xb0150000 0x10000>;
				interrupts = <48>;
				clocks = <&clks 23>;
			};

			pci-iobg {
				compatible = "sirf,prima2-pciiobg", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x56000000 0x56000000 0x1b00000>;

				sd0: sdhci@56000000 {
					cell-index = <0>;
					compatible = "sirf,prima2-sdhc";
					reg = <0x56000000 0x100000>;
					interrupts = <38>;
					bus-width = <8>;
					clocks = <&clks 36>;
				};

				sd1: sdhci@56100000 {
					cell-index = <1>;
					compatible = "sirf,prima2-sdhc";
					reg = <0x56100000 0x100000>;
					interrupts = <38>;
					status = "disabled";
					clocks = <&clks 36>;
				};

				sd2: sdhci@56200000 {
					cell-index = <2>;
					compatible = "sirf,prima2-sdhc";
					reg = <0x56200000 0x100000>;
					interrupts = <23>;
					status = "disabled";
					clocks = <&clks 37>;
				};

				sd3: sdhci@56300000 {
					cell-index = <3>;
					compatible = "sirf,prima2-sdhc";
					reg = <0x56300000 0x100000>;
					interrupts = <23>;
					status = "disabled";
					clocks = <&clks 37>;
				};

				sd5: sdhci@56500000 {
					cell-index = <5>;
					compatible = "sirf,prima2-sdhc";
					reg = <0x56500000 0x100000>;
					interrupts = <39>;
					status = "disabled";
					clocks = <&clks 38>;
				};

				pci-copy@57900000 {
					compatible = "sirf,prima2-pcicp";
					reg = <0x57900000 0x100000>;
					interrupts = <40>;
				};

				rom-interface@57a00000 {
					compatible = "sirf,prima2-romif";
					reg = <0x57a00000 0x100000>;
				};
			};
		};

		rtc-iobg {
			compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x80030000 0x10000>;

			gpsrtc@1000 {
				compatible = "sirf,prima2-gpsrtc";
				reg = <0x1000 0x1000>;
				interrupts = <55 56 57>;
			};

			sysrtc@2000 {
				compatible = "sirf,prima2-sysrtc";
				reg = <0x2000 0x1000>;
				interrupts = <52 53 54>;
			};

			pwrc@3000 {
				compatible = "sirf,prima2-pwrc";
				reg = <0x3000 0x1000>;
				interrupts = <32>;
			};
		};

		uus-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0xb8000000 0xb8000000 0x40000>;

			usb0: usb@b00e0000 {
				compatible = "chipidea,ci13611a-prima2";
				reg = <0xb8000000 0x10000>;
				interrupts = <10>;
				clocks = <&clks 40>;
			};

			usb1: usb@b00f0000 {
				compatible = "chipidea,ci13611a-prima2";
				reg = <0xb8010000 0x10000>;
				interrupts = <11>;
				clocks = <&clks 41>;
			};

			security@b00f0000 {
				compatible = "sirf,prima2-security";
				reg = <0xb8030000 0x10000>;
				interrupts = <42>;
				clocks = <&clks 7>;
			};
		};
	};
};
Commit	Line	Data
5fa2f9af BS	1	/*
	2	* DTS file for CSR SiRFatlas6 SoC
	3	*
	4	* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	/include/ "skeleton.dtsi"
	10	/ {
	11	compatible = "sirf,atlas6";
	12	#address-cells = <1>;
	13	#size-cells = <1>;
	14	interrupt-parent = <&intc>;
	15
	16	cpus {
	17	#address-cells = <1>;
	18	#size-cells = <0>;
	19
	20	cpu@0 {
	21	reg = <0x0>;
	22	d-cache-line-size = <32>;
	23	i-cache-line-size = <32>;
	24	d-cache-size = <32768>;
	25	i-cache-size = <32768>;
	26	/* from bootloader */
	27	timebase-frequency = <0>;
	28	bus-frequency = <0>;
	29	clock-frequency = <0>;
	30	};
	31	};
	32
	33	axi {
	34	compatible = "simple-bus";
	35	#address-cells = <1>;
	36	#size-cells = <1>;
	37	ranges = <0x40000000 0x40000000 0x80000000>;
	38
	39	intc: interrupt-controller@80020000 {
	40	#interrupt-cells = <1>;
	41	interrupt-controller;
	42	compatible = "sirf,prima2-intc";
	43	reg = <0x80020000 0x1000>;
	44	};
	45
	46	sys-iobg {
	47	compatible = "simple-bus";
	48	#address-cells = <1>;
	49	#size-cells = <1>;
	50	ranges = <0x88000000 0x88000000 0x40000>;
	51
	52	clks: clock-controller@88000000 {
	53	compatible = "sirf,atlas6-clkc";
	54	reg = <0x88000000 0x1000>;
	55	interrupts = <3>;
	56	#clock-cells = <1>;
	57	};
	58
	59	reset-controller@88010000 {
	60	compatible = "sirf,prima2-rstc";
	61	reg = <0x88010000 0x1000>;
	62	};
	63
	64	rsc-controller@88020000 {
65	compatible = "sirf,prima2-rsc";
66	reg = <0x88020000 0x1000>;
67	};
68	};
69
70	mem-iobg {
71	compatible = "simple-bus";
72	#address-cells = <1>;
73	#size-cells = <1>;
74	ranges = <0x90000000 0x90000000 0x10000>;
75
76	memory-controller@90000000 {
77	compatible = "sirf,prima2-memc";
78	reg = <0x90000000 0x10000>;
79	interrupts = <27>;
80	clocks = <&clks 5>;
81	};
82	};
83
84	disp-iobg {
85	compatible = "simple-bus";
86	#address-cells = <1>;
87	#size-cells = <1>;
88	ranges = <0x90010000 0x90010000 0x30000>;
89
90	lcd@90010000 {
91	compatible = "sirf,prima2-lcd";
92	reg = <0x90010000 0x20000>;
93	interrupts = <30>;
94	clocks = <&clks 34>;
95	display=<&display>;
96	/* later transfer to pwm */
97	bl-gpio = <&gpio 7 0>;
98	default-panel = <&panel0>;
99	};
100
101	vpp@90020000 {
102	compatible = "sirf,prima2-vpp";
103	reg = <0x90020000 0x10000>;
104	interrupts = <31>;
105	clocks = <&clks 35>;
106	};
107	};
108
109	graphics-iobg {
110	compatible = "simple-bus";
111	#address-cells = <1>;
112	#size-cells = <1>;
113	ranges = <0x98000000 0x98000000 0x8000000>;
114
115	graphics@98000000 {
116	compatible = "powervr,sgx510";
117	reg = <0x98000000 0x8000000>;
118	interrupts = <6>;
119	clocks = <&clks 32>;
120	};
121	};
122
123	dsp-iobg {
124	compatible = "simple-bus";
125	#address-cells = <1>;
126	#size-cells = <1>;
127	ranges = <0xa8000000 0xa8000000 0x2000000>;
128
129	dspif@a8000000 {
130	compatible = "sirf,prima2-dspif";
131	reg = <0xa8000000 0x10000>;
132	interrupts = <9>;
133	};
134
135	gps@a8010000 {
136	compatible = "sirf,prima2-gps";
137	reg = <0xa8010000 0x10000>;
138	interrupts = <7>;
139	clocks = <&clks 9>;
140	};
141
142	dsp@a9000000 {
143	compatible = "sirf,prima2-dsp";
144	reg = <0xa9000000 0x1000000>;
145	interrupts = <8>;
146	clocks = <&clks 8>;
147	};
148	};
149
150	peri-iobg {
151	compatible = "simple-bus";
152	#address-cells = <1>;
153	#size-cells = <1>;
154	ranges = <0xb0000000 0xb0000000 0x180000>,
155	<0x56000000 0x56000000 0x1b00000>;
156
157	timer@b0020000 {
158	compatible = "sirf,prima2-tick";
159	reg = <0xb0020000 0x1000>;
160	interrupts = <0>;
161	};
162
163	nand@b0030000 {
164	compatible = "sirf,prima2-nand";
165	reg = <0xb0030000 0x10000>;
166	interrupts = <41>;
167	clocks = <&clks 26>;
168	};
169
170	audio@b0040000 {
171	compatible = "sirf,prima2-audio";
172	reg = <0xb0040000 0x10000>;
173	interrupts = <35>;
174	clocks = <&clks 27>;
175	};
176
177	uart0: uart@b0050000 {
178	cell-index = <0>;
179	compatible = "sirf,prima2-uart";
180	reg = <0xb0050000 0x1000>;
181	interrupts = <17>;
182	fifosize = <128>;
183	clocks = <&clks 13>;
184	};
185
186	uart1: uart@b0060000 {
187	cell-index = <1>;
188	compatible = "sirf,prima2-uart";
189	reg = <0xb0060000 0x1000>;
190	interrupts = <18>;
191	fifosize = <32>;
192	clocks = <&clks 14>;
193	};
194
195	uart2: uart@b0070000 {
196	cell-index = <2>;
197	compatible = "sirf,prima2-uart";
198	reg = <0xb0070000 0x1000>;
199	interrupts = <19>;
200	fifosize = <128>;
201	clocks = <&clks 15>;
202	};
203
204	usp0: usp@b0080000 {
205	cell-index = <0>;
206	compatible = "sirf,prima2-usp";
207	reg = <0xb0080000 0x10000>;
208	interrupts = <20>;
209	clocks = <&clks 28>;
210	};
211
212	usp1: usp@b0090000 {
213	cell-index = <1>;
214	compatible = "sirf,prima2-usp";
215	reg = <0xb0090000 0x10000>;
216	interrupts = <21>;
217	clocks = <&clks 29>;
218	};
219
220	dmac0: dma-controller@b00b0000 {
221	cell-index = <0>;
222	compatible = "sirf,prima2-dmac";
223	reg = <0xb00b0000 0x10000>;
224	interrupts = <12>;
225	clocks = <&clks 24>;
226	};
227
228	dmac1: dma-controller@b0160000 {
229	cell-index = <1>;
230	compatible = "sirf,prima2-dmac";
231	reg = <0xb0160000 0x10000>;
232	interrupts = <13>;
233	clocks = <&clks 25>;
234	};
235
236	vip@b00C0000 {
237	compatible = "sirf,prima2-vip";
238	reg = <0xb00C0000 0x10000>;
239	clocks = <&clks 31>;
240	};
241
242	spi0: spi@b00d0000 {
243	cell-index = <0>;
244	compatible = "sirf,prima2-spi";
245	reg = <0xb00d0000 0x10000>;
246	interrupts = <15>;
247	sirf,spi-num-chipselects = <1>;
248	cs-gpios = <&gpio 0 0>;
249	sirf,spi-dma-rx-channel = <25>;
250	sirf,spi-dma-tx-channel = <20>;
251	#address-cells = <1>;
252	#size-cells = <0>;
253	clocks = <&clks 19>;
254	status = "disabled";
255	};
256
257	spi1: spi@b0170000 {
258	cell-index = <1>;
259	compatible = "sirf,prima2-spi";
260	reg = <0xb0170000 0x10000>;
261	interrupts = <16>;
262	clocks = <&clks 20>;
263	status = "disabled";
264	};
265
266	i2c0: i2c@b00e0000 {
267	cell-index = <0>;
268	compatible = "sirf,prima2-i2c";
269	reg = <0xb00e0000 0x10000>;
270	interrupts = <24>;
271	#address-cells = <1>;
272	#size-cells = <0>;
273	clocks = <&clks 17>;
274	};
275
276	i2c1: i2c@b00f0000 {
277	cell-index = <1>;
278	compatible = "sirf,prima2-i2c";
279	reg = <0xb00f0000 0x10000>;
280	interrupts = <25>;
281	#address-cells = <1>;
282	#size-cells = <0>;
283	clocks = <&clks 18>;
284	};
285
286	tsc@b0110000 {
287	compatible = "sirf,prima2-tsc";
288	reg = <0xb0110000 0x10000>;
289	interrupts = <33>;
290	clocks = <&clks 16>;
291	};
292
293	gpio: pinctrl@b0120000 {
294	#gpio-cells = <2>;
295	#interrupt-cells = <2>;
296	compatible = "sirf,atlas6-pinctrl";
297	reg = <0xb0120000 0x10000>;
298	interrupts = <43 44 45 46 47>;
299	gpio-controller;
300	interrupt-controller;
301
302	lcd_16pins_a: lcd0@0 {
303	lcd {
304	sirf,pins = "lcd_16bitsgrp";
305	sirf,function = "lcd_16bits";
306	};
307	};
308	lcd_18pins_a: lcd0@1 {
309	lcd {
310	sirf,pins = "lcd_18bitsgrp";
311	sirf,function = "lcd_18bits";
312	};
313	};
314	lcd_24pins_a: lcd0@2 {
315	lcd {
316	sirf,pins = "lcd_24bitsgrp";
317	sirf,function = "lcd_24bits";
318	};
319	};
320	lcdrom_pins_a: lcdrom0@0 {
321	lcd {
322	sirf,pins = "lcdromgrp";
323	sirf,function = "lcdrom";
324	};
325	};
326	uart0_pins_a: uart0@0 {
327	uart {
328	sirf,pins = "uart0grp";
329	sirf,function = "uart0";
330	};
331	};
031b8ce0 QL	332	uart0_noflow_pins_a: uart0@1 {
	333	uart {
	334	sirf,pins = "uart0_nostreamctrlgrp";
	335	sirf,function = "uart0_nostreamctrl";
	336	};
	337	};
5fa2f9af BS	338	uart1_pins_a: uart1@0 {
	339	uart {
	340	sirf,pins = "uart1grp";
	341	sirf,function = "uart1";
	342	};
	343	};
	344	uart2_pins_a: uart2@0 {
	345	uart {
	346	sirf,pins = "uart2grp";
	347	sirf,function = "uart2";
	348	};
	349	};
	350	uart2_noflow_pins_a: uart2@1 {
	351	uart {
	352	sirf,pins = "uart2_nostreamctrlgrp";
	353	sirf,function = "uart2_nostreamctrl";
	354	};
	355	};
	356	spi0_pins_a: spi0@0 {
	357	spi {
	358	sirf,pins = "spi0grp";
	359	sirf,function = "spi0";
	360	};
	361	};
	362	spi1_pins_a: spi1@0 {
	363	spi {
	364	sirf,pins = "spi1grp";
	365	sirf,function = "spi1";
	366	};
	367	};
	368	i2c0_pins_a: i2c0@0 {
	369	i2c {
	370	sirf,pins = "i2c0grp";
	371	sirf,function = "i2c0";
	372	};
	373	};
	374	i2c1_pins_a: i2c1@0 {
	375	i2c {
	376	sirf,pins = "i2c1grp";
	377	sirf,function = "i2c1";
	378	};
	379	};
	380	pwm0_pins_a: pwm0@0 {
	381	pwm {
	382	sirf,pins = "pwm0grp";
	383	sirf,function = "pwm0";
	384	};
	385	};
	386	pwm1_pins_a: pwm1@0 {
	387	pwm {
	388	sirf,pins = "pwm1grp";
	389	sirf,function = "pwm1";
	390	};
	391	};
	392	pwm2_pins_a: pwm2@0 {
	393	pwm {
	394	sirf,pins = "pwm2grp";
	395	sirf,function = "pwm2";
	396	};
	397	};
	398	pwm3_pins_a: pwm3@0 {
	399	pwm {
	400	sirf,pins = "pwm3grp";
	401	sirf,function = "pwm3";
402	};
403	};
404	pwm4_pins_a: pwm4@0 {
405	pwm {
406	sirf,pins = "pwm4grp";
407	sirf,function = "pwm4";
408	};
409	};
410	gps_pins_a: gps@0 {
411	gps {
412	sirf,pins = "gpsgrp";
413	sirf,function = "gps";
414	};
415	};
416	vip_pins_a: vip@0 {
417	vip {
418	sirf,pins = "vipgrp";
419	sirf,function = "vip";
420	};
421	};
422	sdmmc0_pins_a: sdmmc0@0 {
423	sdmmc0 {
424	sirf,pins = "sdmmc0grp";
425	sirf,function = "sdmmc0";
426	};
427	};
428	sdmmc1_pins_a: sdmmc1@0 {
429	sdmmc1 {
430	sirf,pins = "sdmmc1grp";
431	sirf,function = "sdmmc1";
432	};
433	};
434	sdmmc2_pins_a: sdmmc2@0 {
435	sdmmc2 {
436	sirf,pins = "sdmmc2grp";
437	sirf,function = "sdmmc2";
438	};
439	};
440	sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
441	sdmmc2_nowp {
442	sirf,pins = "sdmmc2_nowpgrp";
443	sirf,function = "sdmmc2_nowp";
444	};
445	};
446	sdmmc3_pins_a: sdmmc3@0 {
447	sdmmc3 {
448	sirf,pins = "sdmmc3grp";
449	sirf,function = "sdmmc3";
450	};
451	};
452	sdmmc5_pins_a: sdmmc5@0 {
453	sdmmc5 {
454	sirf,pins = "sdmmc5grp";
455	sirf,function = "sdmmc5";
456	};
457	};
458	i2s_pins_a: i2s@0 {
459	i2s {
460	sirf,pins = "i2sgrp";
461	sirf,function = "i2s";
462	};
463	};
464	i2s_no_din_pins_a: i2s_no_din@0 {
465	i2s_no_din {
466	sirf,pins = "i2s_no_dingrp";
467	sirf,function = "i2s_no_din";
468	};
469	};
470	i2s_6chn_pins_a: i2s_6chn@0 {
471	i2s_6chn {
472	sirf,pins = "i2s_6chngrp";
473	sirf,function = "i2s_6chn";
474	};
475	};
476	ac97_pins_a: ac97@0 {
477	ac97 {
478	sirf,pins = "ac97grp";
479	sirf,function = "ac97";
480	};
481	};
482	nand_pins_a: nand@0 {
483	nand {
484	sirf,pins = "nandgrp";
485	sirf,function = "nand";
486	};
487	};
488	usp0_pins_a: usp0@0 {
489	usp0 {
490	sirf,pins = "usp0grp";
491	sirf,function = "usp0";
492	};
493	};
d58e9a02 QL	494	usp0_uart_nostreamctrl_pins_a: usp0@1 {
	495	usp0 {
	496	sirf,pins = "usp0_uart_nostreamctrl_grp";
	497	sirf,function = "usp0_uart_nostreamctrl";
	498	};
	499	};
5fa2f9af BS	500	usp1_pins_a: usp1@0 {
	501	usp1 {
	502	sirf,pins = "usp1grp";
	503	sirf,function = "usp1";
	504	};
	505	};
	506	usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
	507	usb0_upli_drvbus {
	508	sirf,pins = "usb0_upli_drvbusgrp";
	509	sirf,function = "usb0_upli_drvbus";
	510	};
	511	};
	512	usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
	513	usb1_utmi_drvbus {
	514	sirf,pins = "usb1_utmi_drvbusgrp";
	515	sirf,function = "usb1_utmi_drvbus";
	516	};
	517	};
	518	warm_rst_pins_a: warm_rst@0 {
	519	warm_rst {
	520	sirf,pins = "warm_rstgrp";
	521	sirf,function = "warm_rst";
	522	};
	523	};
	524	pulse_count_pins_a: pulse_count@0 {
	525	pulse_count {
	526	sirf,pins = "pulse_countgrp";
	527	sirf,function = "pulse_count";
	528	};
	529	};
c8078de8 BS	530	cko0_pins_a: cko0@0 {
	531	cko0 {
	532	sirf,pins = "cko0grp";
	533	sirf,function = "cko0";
5fa2f9af BS	534	};
5fa2f9af BS	535	};
c8078de8 BS	536	cko1_pins_a: cko1@0 {
	537	cko1 {
	538	sirf,pins = "cko1grp";
	539	sirf,function = "cko1";
5fa2f9af BS	540	};
	541	};
	542	};
	543
	544	pwm@b0130000 {
	545	compatible = "sirf,prima2-pwm";
	546	reg = <0xb0130000 0x10000>;
	547	clocks = <&clks 21>;
	548	};
	549
	550	efusesys@b0140000 {
	551	compatible = "sirf,prima2-efuse";
	552	reg = <0xb0140000 0x10000>;
	553	clocks = <&clks 22>;
	554	};
	555
	556	pulsec@b0150000 {
	557	compatible = "sirf,prima2-pulsec";
	558	reg = <0xb0150000 0x10000>;
	559	interrupts = <48>;
	560	clocks = <&clks 23>;
	561	};
	562
	563	pci-iobg {
	564	compatible = "sirf,prima2-pciiobg", "simple-bus";
	565	#address-cells = <1>;
	566	#size-cells = <1>;
	567	ranges = <0x56000000 0x56000000 0x1b00000>;
	568
	569	sd0: sdhci@56000000 {
	570	cell-index = <0>;
	571	compatible = "sirf,prima2-sdhc";
	572	reg = <0x56000000 0x100000>;
	573	interrupts = <38>;
	574	bus-width = <8>;
	575	clocks = <&clks 36>;
	576	};
	577
	578	sd1: sdhci@56100000 {
	579	cell-index = <1>;
	580	compatible = "sirf,prima2-sdhc";
	581	reg = <0x56100000 0x100000>;
	582	interrupts = <38>;
	583	status = "disabled";
	584	clocks = <&clks 36>;
	585	};
	586
	587	sd2: sdhci@56200000 {
	588	cell-index = <2>;
	589	compatible = "sirf,prima2-sdhc";
	590	reg = <0x56200000 0x100000>;
	591	interrupts = <23>;
	592	status = "disabled";
	593	clocks = <&clks 37>;
	594	};
	595
	596	sd3: sdhci@56300000 {
	597	cell-index = <3>;
	598	compatible = "sirf,prima2-sdhc";
	599	reg = <0x56300000 0x100000>;
	600	interrupts = <23>;
	601	status = "disabled";
	602	clocks = <&clks 37>;
	603	};
604
605	sd5: sdhci@56500000 {
606	cell-index = <5>;
607	compatible = "sirf,prima2-sdhc";
608	reg = <0x56500000 0x100000>;
609	interrupts = <39>;
610	status = "disabled";
611	clocks = <&clks 38>;
612	};
613
614	pci-copy@57900000 {
615	compatible = "sirf,prima2-pcicp";
616	reg = <0x57900000 0x100000>;
617	interrupts = <40>;
618	};
619
620	rom-interface@57a00000 {
621	compatible = "sirf,prima2-romif";
622	reg = <0x57a00000 0x100000>;
623	};
624	};
625	};
626
627	rtc-iobg {
e88b815e	628	compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
5fa2f9af BS	629	#address-cells = <1>;
	630	#size-cells = <1>;
	631	reg = <0x80030000 0x10000>;
	632
	633	gpsrtc@1000 {
	634	compatible = "sirf,prima2-gpsrtc";
	635	reg = <0x1000 0x1000>;
	636	interrupts = <55 56 57>;
	637	};
	638
	639	sysrtc@2000 {
	640	compatible = "sirf,prima2-sysrtc";
	641	reg = <0x2000 0x1000>;
	642	interrupts = <52 53 54>;
	643	};
	644
	645	pwrc@3000 {
	646	compatible = "sirf,prima2-pwrc";
	647	reg = <0x3000 0x1000>;
	648	interrupts = <32>;
	649	};
	650	};
	651
	652	uus-iobg {
	653	compatible = "simple-bus";
	654	#address-cells = <1>;
	655	#size-cells = <1>;
	656	ranges = <0xb8000000 0xb8000000 0x40000>;
	657
	658	usb0: usb@b00e0000 {
	659	compatible = "chipidea,ci13611a-prima2";
	660	reg = <0xb8000000 0x10000>;
	661	interrupts = <10>;
	662	clocks = <&clks 40>;
	663	};
	664
	665	usb1: usb@b00f0000 {
	666	compatible = "chipidea,ci13611a-prima2";
	667	reg = <0xb8010000 0x10000>;
	668	interrupts = <11>;
	669	clocks = <&clks 41>;
	670	};
	671
	672	security@b00f0000 {
	673	compatible = "sirf,prima2-security";
	674	reg = <0xb8030000 0x10000>;
	675	interrupts = <42>;
	676	clocks = <&clks 7>;
	677	};
	678	};
	679	};
	680	};