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c9ad7bc5 SB |
1 | /* |
2 | * BSD LICENSE | |
3 | * | |
4 | * Copyright(c) 2014 Broadcom Corporation. All rights reserved. | |
5 | * | |
6 | * Redistribution and use in source and binary forms, with or without | |
7 | * modification, are permitted provided that the following conditions | |
8 | * are met: | |
9 | * | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in | |
14 | * the documentation and/or other materials provided with the | |
15 | * distribution. | |
16 | * * Neither the name of Broadcom Corporation nor the names of its | |
17 | * contributors may be used to endorse or promote products derived | |
18 | * from this software without specific prior written permission. | |
19 | * | |
20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
23 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
24 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
25 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
26 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
31 | */ | |
32 | ||
33 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
34 | #include <dt-bindings/interrupt-controller/irq.h> | |
35e372a3 | 35 | #include <dt-bindings/clock/bcm-cygnus.h> |
c9ad7bc5 SB |
36 | |
37 | #include "skeleton.dtsi" | |
38 | ||
39 | / { | |
40 | compatible = "brcm,cygnus"; | |
41 | model = "Broadcom Cygnus SoC"; | |
42 | interrupt-parent = <&gic>; | |
43 | ||
44 | cpus { | |
45 | #address-cells = <1>; | |
46 | #size-cells = <0>; | |
47 | ||
48 | cpu@0 { | |
49 | device_type = "cpu"; | |
50 | compatible = "arm,cortex-a9"; | |
51 | next-level-cache = <&L2>; | |
52 | reg = <0x0>; | |
53 | }; | |
54 | }; | |
55 | ||
56 | /include/ "bcm-cygnus-clock.dtsi" | |
57 | ||
ef5b812a RJ |
58 | core { |
59 | compatible = "simple-bus"; | |
60 | ranges = <0x00000000 0x19000000 0x1000000>; | |
61 | #address-cells = <1>; | |
62 | #size-cells = <1>; | |
63 | ||
64 | timer@20200 { | |
65 | compatible = "arm,cortex-a9-global-timer"; | |
66 | reg = <0x20200 0x100>; | |
67 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
68 | clocks = <&periph_clk>; | |
69 | }; | |
70 | ||
71 | gic: interrupt-controller@21000 { | |
72 | compatible = "arm,cortex-a9-gic"; | |
73 | #interrupt-cells = <3>; | |
74 | #address-cells = <0>; | |
75 | interrupt-controller; | |
76 | reg = <0x21000 0x1000>, | |
77 | <0x20100 0x100>; | |
78 | }; | |
79 | ||
80 | L2: l2-cache { | |
81 | compatible = "arm,pl310-cache"; | |
82 | reg = <0x22000 0x1000>; | |
83 | cache-unified; | |
84 | cache-level = <2>; | |
85 | }; | |
86 | }; | |
87 | ||
0f0b21a8 RJ |
88 | axi { |
89 | compatible = "simple-bus"; | |
90 | ranges; | |
91 | #address-cells = <1>; | |
92 | #size-cells = <1>; | |
e6a4e5d5 | 93 | |
7fa8b51b JR |
94 | otp: otp@0301c800 { |
95 | compatible = "brcm,ocotp"; | |
96 | reg = <0x0301c800 0x2c>; | |
97 | brcm,ocotp-size = <2048>; | |
98 | status = "disabled"; | |
99 | }; | |
100 | ||
44a06fa4 RJ |
101 | pcie_phy: phy@0301d0a0 { |
102 | compatible = "brcm,cygnus-pcie-phy"; | |
103 | reg = <0x0301d0a0 0x14>; | |
104 | #address-cells = <1>; | |
105 | #size-cells = <0>; | |
106 | ||
107 | pcie0_phy: phy@0 { | |
108 | reg = <0>; | |
109 | #phy-cells = <0>; | |
110 | }; | |
111 | ||
112 | pcie1_phy: phy@1 { | |
113 | reg = <1>; | |
114 | #phy-cells = <0>; | |
115 | }; | |
116 | }; | |
117 | ||
b350e9dd | 118 | pinctrl: pinctrl@0301d0c8 { |
0f0b21a8 RJ |
119 | compatible = "brcm,cygnus-pinmux"; |
120 | reg = <0x0301d0c8 0x30>, | |
121 | <0x0301d24c 0x2c>; | |
122 | }; | |
5fa4b29c | 123 | |
77f923cb JR |
124 | mailbox: mailbox@03024024 { |
125 | compatible = "brcm,iproc-mailbox"; | |
126 | reg = <0x03024024 0x40>; | |
127 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; | |
128 | #interrupt-cells = <1>; | |
129 | interrupt-controller; | |
130 | #mbox-cells = <1>; | |
131 | }; | |
132 | ||
0f0b21a8 RJ |
133 | gpio_crmu: gpio@03024800 { |
134 | compatible = "brcm,cygnus-crmu-gpio"; | |
135 | reg = <0x03024800 0x50>, | |
136 | <0x03024008 0x18>; | |
3ad8ff0e | 137 | ngpios = <6>; |
0f0b21a8 RJ |
138 | #gpio-cells = <2>; |
139 | gpio-controller; | |
2c42d0f0 JR |
140 | interrupt-controller; |
141 | interrupt-parent = <&mailbox>; | |
142 | interrupts = <0>; | |
0f0b21a8 | 143 | }; |
5fa4b29c | 144 | |
9c5101f7 RJ |
145 | i2c0: i2c@18008000 { |
146 | compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; | |
147 | reg = <0x18008000 0x100>; | |
148 | #address-cells = <1>; | |
149 | #size-cells = <0>; | |
150 | interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; | |
151 | clock-frequency = <100000>; | |
152 | status = "disabled"; | |
0f0b21a8 | 153 | }; |
c9ad7bc5 | 154 | |
0f0b21a8 RJ |
155 | wdt0: wdt@18009000 { |
156 | compatible = "arm,sp805" , "arm,primecell"; | |
157 | reg = <0x18009000 0x1000>; | |
158 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
159 | clocks = <&axi81_clk>; | |
160 | clock-names = "apb_pclk"; | |
c9ad7bc5 | 161 | }; |
c9ad7bc5 | 162 | |
9c5101f7 RJ |
163 | gpio_ccm: gpio@1800a000 { |
164 | compatible = "brcm,cygnus-ccm-gpio"; | |
165 | reg = <0x1800a000 0x50>, | |
166 | <0x0301d164 0x20>; | |
3ad8ff0e | 167 | ngpios = <24>; |
9c5101f7 RJ |
168 | #gpio-cells = <2>; |
169 | gpio-controller; | |
170 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
171 | interrupt-controller; | |
0f0b21a8 | 172 | }; |
b51c05a3 | 173 | |
0f0b21a8 RJ |
174 | i2c1: i2c@1800b000 { |
175 | compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; | |
176 | reg = <0x1800b000 0x100>; | |
177 | #address-cells = <1>; | |
178 | #size-cells = <0>; | |
179 | interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; | |
180 | clock-frequency = <100000>; | |
181 | status = "disabled"; | |
182 | }; | |
b51c05a3 | 183 | |
0f0b21a8 RJ |
184 | pcie0: pcie@18012000 { |
185 | compatible = "brcm,iproc-pcie"; | |
186 | reg = <0x18012000 0x1000>; | |
cd590b50 | 187 | |
0f0b21a8 RJ |
188 | #interrupt-cells = <1>; |
189 | interrupt-map-mask = <0 0 0 0>; | |
190 | interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; | |
cd590b50 | 191 | |
0f0b21a8 | 192 | linux,pci-domain = <0>; |
cd590b50 | 193 | |
0f0b21a8 | 194 | bus-range = <0x00 0xff>; |
cd590b50 | 195 | |
0f0b21a8 RJ |
196 | #address-cells = <3>; |
197 | #size-cells = <2>; | |
198 | device_type = "pci"; | |
199 | ranges = <0x81000000 0 0 0x28000000 0 0x00010000 | |
200 | 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; | |
cd590b50 | 201 | |
44a06fa4 RJ |
202 | phys = <&pcie0_phy>; |
203 | phy-names = "pcie-phy"; | |
204 | ||
0f0b21a8 | 205 | status = "disabled"; |
f6b88935 RJ |
206 | |
207 | msi-parent = <&msi0>; | |
208 | msi0: msi@18012000 { | |
209 | compatible = "brcm,iproc-msi"; | |
210 | msi-controller; | |
211 | interrupt-parent = <&gic>; | |
212 | interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, | |
213 | <GIC_SPI 97 IRQ_TYPE_NONE>, | |
214 | <GIC_SPI 98 IRQ_TYPE_NONE>, | |
215 | <GIC_SPI 99 IRQ_TYPE_NONE>; | |
216 | }; | |
0f0b21a8 | 217 | }; |
cd590b50 | 218 | |
0f0b21a8 RJ |
219 | pcie1: pcie@18013000 { |
220 | compatible = "brcm,iproc-pcie"; | |
221 | reg = <0x18013000 0x1000>; | |
cd590b50 | 222 | |
0f0b21a8 RJ |
223 | #interrupt-cells = <1>; |
224 | interrupt-map-mask = <0 0 0 0>; | |
225 | interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; | |
cd590b50 | 226 | |
0f0b21a8 | 227 | linux,pci-domain = <1>; |
cd590b50 | 228 | |
0f0b21a8 | 229 | bus-range = <0x00 0xff>; |
cd590b50 | 230 | |
0f0b21a8 RJ |
231 | #address-cells = <3>; |
232 | #size-cells = <2>; | |
233 | device_type = "pci"; | |
234 | ranges = <0x81000000 0 0 0x48000000 0 0x00010000 | |
235 | 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; | |
cd590b50 | 236 | |
44a06fa4 RJ |
237 | phys = <&pcie1_phy>; |
238 | phy-names = "pcie-phy"; | |
239 | ||
0f0b21a8 | 240 | status = "disabled"; |
f6b88935 RJ |
241 | |
242 | msi-parent = <&msi1>; | |
243 | msi1: msi@18013000 { | |
244 | compatible = "brcm,iproc-msi"; | |
245 | msi-controller; | |
246 | interrupt-parent = <&gic>; | |
247 | interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>, | |
248 | <GIC_SPI 103 IRQ_TYPE_NONE>, | |
249 | <GIC_SPI 104 IRQ_TYPE_NONE>, | |
250 | <GIC_SPI 105 IRQ_TYPE_NONE>; | |
251 | }; | |
0f0b21a8 | 252 | }; |
cd590b50 | 253 | |
0f0b21a8 RJ |
254 | uart0: serial@18020000 { |
255 | compatible = "snps,dw-apb-uart"; | |
256 | reg = <0x18020000 0x100>; | |
257 | reg-shift = <2>; | |
258 | reg-io-width = <4>; | |
259 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
260 | clocks = <&axi81_clk>; | |
261 | clock-frequency = <100000000>; | |
262 | status = "disabled"; | |
263 | }; | |
c9ad7bc5 | 264 | |
0f0b21a8 RJ |
265 | uart1: serial@18021000 { |
266 | compatible = "snps,dw-apb-uart"; | |
267 | reg = <0x18021000 0x100>; | |
268 | reg-shift = <2>; | |
269 | reg-io-width = <4>; | |
270 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
271 | clocks = <&axi81_clk>; | |
272 | clock-frequency = <100000000>; | |
273 | status = "disabled"; | |
274 | }; | |
c9ad7bc5 | 275 | |
0f0b21a8 RJ |
276 | uart2: serial@18022000 { |
277 | compatible = "snps,dw-apb-uart"; | |
278 | reg = <0x18020000 0x100>; | |
279 | reg-shift = <2>; | |
280 | reg-io-width = <4>; | |
281 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
282 | clocks = <&axi81_clk>; | |
283 | clock-frequency = <100000000>; | |
284 | status = "disabled"; | |
285 | }; | |
c9ad7bc5 | 286 | |
0f0b21a8 RJ |
287 | uart3: serial@18023000 { |
288 | compatible = "snps,dw-apb-uart"; | |
289 | reg = <0x18023000 0x100>; | |
290 | reg-shift = <2>; | |
291 | reg-io-width = <4>; | |
292 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
293 | clocks = <&axi81_clk>; | |
294 | clock-frequency = <100000000>; | |
295 | status = "disabled"; | |
296 | }; | |
c9ad7bc5 | 297 | |
0f0b21a8 | 298 | nand: nand@18046000 { |
08668d9d | 299 | compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; |
0f0b21a8 RJ |
300 | reg = <0x18046000 0x600>, <0xf8105408 0x600>, |
301 | <0x18046f00 0x20>; | |
302 | reg-names = "nand", "iproc-idm", "iproc-ext"; | |
303 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
874d5f1b | 304 | |
0f0b21a8 RJ |
305 | #address-cells = <1>; |
306 | #size-cells = <0>; | |
874d5f1b | 307 | |
0f0b21a8 RJ |
308 | brcm,nand-has-wp; |
309 | }; | |
9c5101f7 RJ |
310 | |
311 | gpio_asiu: gpio@180a5000 { | |
312 | compatible = "brcm,cygnus-asiu-gpio"; | |
313 | reg = <0x180a5000 0x668>; | |
3ad8ff0e | 314 | ngpios = <146>; |
9c5101f7 RJ |
315 | #gpio-cells = <2>; |
316 | gpio-controller; | |
317 | ||
9c5101f7 RJ |
318 | interrupt-controller; |
319 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; | |
3890ab2b PK |
320 | gpio-ranges = <&pinctrl 0 42 1>, |
321 | <&pinctrl 1 44 3>, | |
322 | <&pinctrl 4 48 1>, | |
323 | <&pinctrl 5 50 3>, | |
324 | <&pinctrl 8 126 1>, | |
325 | <&pinctrl 9 155 1>, | |
326 | <&pinctrl 10 152 1>, | |
327 | <&pinctrl 11 154 1>, | |
328 | <&pinctrl 12 153 1>, | |
329 | <&pinctrl 13 127 3>, | |
330 | <&pinctrl 16 140 1>, | |
331 | <&pinctrl 17 145 7>, | |
332 | <&pinctrl 24 130 10>, | |
333 | <&pinctrl 34 141 4>, | |
334 | <&pinctrl 38 54 1>, | |
335 | <&pinctrl 39 56 3>, | |
336 | <&pinctrl 42 60 3>, | |
337 | <&pinctrl 45 64 3>, | |
338 | <&pinctrl 48 68 2>, | |
339 | <&pinctrl 50 84 6>, | |
340 | <&pinctrl 56 94 6>, | |
341 | <&pinctrl 62 72 1>, | |
342 | <&pinctrl 63 70 1>, | |
343 | <&pinctrl 64 80 1>, | |
344 | <&pinctrl 65 74 3>, | |
345 | <&pinctrl 68 78 1>, | |
346 | <&pinctrl 69 82 1>, | |
347 | <&pinctrl 70 156 17>, | |
348 | <&pinctrl 87 104 12>, | |
349 | <&pinctrl 99 102 2>, | |
350 | <&pinctrl 101 90 4>, | |
351 | <&pinctrl 105 116 6>, | |
352 | <&pinctrl 111 100 2>, | |
353 | <&pinctrl 113 122 4>, | |
354 | <&pinctrl 123 11 1>, | |
355 | <&pinctrl 124 38 4>, | |
356 | <&pinctrl 128 43 1>, | |
357 | <&pinctrl 129 47 1>, | |
358 | <&pinctrl 130 49 1>, | |
359 | <&pinctrl 131 53 1>, | |
360 | <&pinctrl 132 55 1>, | |
361 | <&pinctrl 133 59 1>, | |
362 | <&pinctrl 134 63 1>, | |
363 | <&pinctrl 135 67 1>, | |
364 | <&pinctrl 136 71 1>, | |
365 | <&pinctrl 137 73 1>, | |
366 | <&pinctrl 138 77 1>, | |
367 | <&pinctrl 139 79 1>, | |
368 | <&pinctrl 140 81 1>, | |
369 | <&pinctrl 141 83 1>, | |
370 | <&pinctrl 142 10 1>; | |
9c5101f7 | 371 | }; |
35e372a3 | 372 | |
74813ceb RP |
373 | ts_adc_syscon: ts_adc_syscon@180a6000 { |
374 | compatible = "brcm,iproc-ts-adc-syscon", "syscon"; | |
375 | reg = <0x180a6000 0xc30>; | |
376 | }; | |
377 | ||
378 | touchscreen: touchscreen@180a6000 { | |
35e372a3 | 379 | compatible = "brcm,iproc-touchscreen"; |
74813ceb RP |
380 | #address-cells = <1>; |
381 | #size-cells = <1>; | |
382 | ts_syscon = <&ts_adc_syscon>; | |
35e372a3 RJ |
383 | clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; |
384 | clock-names = "tsc_clk"; | |
385 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
386 | status = "disabled"; | |
387 | }; | |
fd048c6b RP |
388 | |
389 | adc: adc@180a6000 { | |
390 | compatible = "brcm,iproc-static-adc"; | |
391 | #io-channel-cells = <1>; | |
392 | io-channel-ranges; | |
393 | adc-syscon = <&ts_adc_syscon>; | |
394 | clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; | |
395 | clock-names = "tsc_clk"; | |
396 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
397 | status = "disabled"; | |
398 | }; | |
874d5f1b | 399 | }; |
c9ad7bc5 | 400 | }; |