]>
Commit | Line | Data |
---|---|---|
c9ad7bc5 SB |
1 | /* |
2 | * BSD LICENSE | |
3 | * | |
4 | * Copyright(c) 2014 Broadcom Corporation. All rights reserved. | |
5 | * | |
6 | * Redistribution and use in source and binary forms, with or without | |
7 | * modification, are permitted provided that the following conditions | |
8 | * are met: | |
9 | * | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in | |
14 | * the documentation and/or other materials provided with the | |
15 | * distribution. | |
16 | * * Neither the name of Broadcom Corporation nor the names of its | |
17 | * contributors may be used to endorse or promote products derived | |
18 | * from this software without specific prior written permission. | |
19 | * | |
20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
23 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
24 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
25 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
26 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
31 | */ | |
32 | ||
33 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
34 | #include <dt-bindings/interrupt-controller/irq.h> | |
35 | ||
36 | #include "skeleton.dtsi" | |
37 | ||
38 | / { | |
39 | compatible = "brcm,cygnus"; | |
40 | model = "Broadcom Cygnus SoC"; | |
41 | interrupt-parent = <&gic>; | |
42 | ||
43 | cpus { | |
44 | #address-cells = <1>; | |
45 | #size-cells = <0>; | |
46 | ||
47 | cpu@0 { | |
48 | device_type = "cpu"; | |
49 | compatible = "arm,cortex-a9"; | |
50 | next-level-cache = <&L2>; | |
51 | reg = <0x0>; | |
52 | }; | |
53 | }; | |
54 | ||
55 | /include/ "bcm-cygnus-clock.dtsi" | |
56 | ||
e6a4e5d5 RJ |
57 | pinctrl: pinctrl@0x0301d0c8 { |
58 | compatible = "brcm,cygnus-pinmux"; | |
59 | reg = <0x0301d0c8 0x30>, | |
60 | <0x0301d24c 0x2c>; | |
61 | }; | |
62 | ||
c9ad7bc5 SB |
63 | amba { |
64 | #address-cells = <1>; | |
65 | #size-cells = <1>; | |
66 | compatible = "arm,amba-bus", "simple-bus"; | |
67 | interrupt-parent = <&gic>; | |
68 | ranges; | |
69 | ||
70 | wdt@18009000 { | |
71 | compatible = "arm,sp805" , "arm,primecell"; | |
72 | reg = <0x18009000 0x1000>; | |
73 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
74 | clocks = <&axi81_clk>; | |
75 | clock-names = "apb_pclk"; | |
76 | }; | |
77 | }; | |
78 | ||
b51c05a3 RJ |
79 | i2c0: i2c@18008000 { |
80 | compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; | |
81 | reg = <0x18008000 0x100>; | |
82 | #address-cells = <1>; | |
83 | #size-cells = <0>; | |
84 | interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; | |
85 | clock-frequency = <100000>; | |
86 | status = "disabled"; | |
87 | }; | |
88 | ||
89 | i2c1: i2c@1800b000 { | |
90 | compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; | |
91 | reg = <0x1800b000 0x100>; | |
92 | #address-cells = <1>; | |
93 | #size-cells = <0>; | |
94 | interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; | |
95 | clock-frequency = <100000>; | |
96 | status = "disabled"; | |
97 | }; | |
98 | ||
c9ad7bc5 SB |
99 | uart0: serial@18020000 { |
100 | compatible = "snps,dw-apb-uart"; | |
101 | reg = <0x18020000 0x100>; | |
102 | reg-shift = <2>; | |
103 | reg-io-width = <4>; | |
104 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
105 | clocks = <&axi81_clk>; | |
106 | clock-frequency = <100000000>; | |
107 | status = "disabled"; | |
108 | }; | |
109 | ||
110 | uart1: serial@18021000 { | |
111 | compatible = "snps,dw-apb-uart"; | |
112 | reg = <0x18021000 0x100>; | |
113 | reg-shift = <2>; | |
114 | reg-io-width = <4>; | |
115 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
116 | clocks = <&axi81_clk>; | |
117 | clock-frequency = <100000000>; | |
118 | status = "disabled"; | |
119 | }; | |
120 | ||
121 | uart2: serial@18022000 { | |
122 | compatible = "snps,dw-apb-uart"; | |
123 | reg = <0x18020000 0x100>; | |
124 | reg-shift = <2>; | |
125 | reg-io-width = <4>; | |
126 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
127 | clocks = <&axi81_clk>; | |
128 | clock-frequency = <100000000>; | |
129 | status = "disabled"; | |
130 | }; | |
131 | ||
132 | uart3: serial@18023000 { | |
133 | compatible = "snps,dw-apb-uart"; | |
134 | reg = <0x18023000 0x100>; | |
135 | reg-shift = <2>; | |
136 | reg-io-width = <4>; | |
137 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
138 | clocks = <&axi81_clk>; | |
139 | clock-frequency = <100000000>; | |
140 | status = "disabled"; | |
141 | }; | |
142 | ||
143 | gic: interrupt-controller@19021000 { | |
144 | compatible = "arm,cortex-a9-gic"; | |
145 | #interrupt-cells = <3>; | |
146 | #address-cells = <0>; | |
147 | interrupt-controller; | |
148 | reg = <0x19021000 0x1000>, | |
149 | <0x19020100 0x100>; | |
150 | }; | |
151 | ||
152 | L2: l2-cache { | |
153 | compatible = "arm,pl310-cache"; | |
154 | reg = <0x19022000 0x1000>; | |
155 | cache-unified; | |
156 | cache-level = <2>; | |
157 | }; | |
158 | ||
159 | timer@19020200 { | |
160 | compatible = "arm,cortex-a9-global-timer"; | |
161 | reg = <0x19020200 0x100>; | |
162 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
163 | clocks = <&periph_clk>; | |
164 | }; | |
165 | ||
166 | }; |