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8ac49e04 CD |
1 | /* |
2 | * Copyright (C) 2012 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation version 2. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
74375653 | 14 | #include "skeleton.dtsi" |
8ac49e04 CD |
15 | |
16 | / { | |
17 | model = "BCM11351 SoC"; | |
18 | compatible = "bcm,bcm11351"; | |
19 | interrupt-parent = <&gic>; | |
20 | ||
21 | chosen { | |
22 | bootargs = "console=ttyS0,115200n8"; | |
23 | }; | |
24 | ||
25 | gic: interrupt-controller@3ff00100 { | |
26 | compatible = "arm,cortex-a9-gic"; | |
27 | #interrupt-cells = <3>; | |
28 | #address-cells = <0>; | |
29 | interrupt-controller; | |
30 | reg = <0x3ff01000 0x1000>, | |
31 | <0x3ff00100 0x100>; | |
32 | }; | |
33 | ||
7f6c62e2 CD |
34 | smc@0x3404c000 { |
35 | compatible = "bcm,bcm11351-smc", "bcm,kona-smc"; | |
36 | reg = <0x3404c000 0x400>; //1 KiB in SRAM | |
37 | }; | |
38 | ||
8ac49e04 CD |
39 | uart@3e000000 { |
40 | compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; | |
41 | status = "disabled"; | |
42 | reg = <0x3e000000 0x1000>; | |
43 | clock-frequency = <13000000>; | |
44 | interrupts = <0x0 67 0x4>; | |
45 | reg-shift = <2>; | |
46 | reg-io-width = <4>; | |
47 | }; | |
48 | ||
49 | L2: l2-cache { | |
50 | compatible = "arm,pl310-cache"; | |
51 | reg = <0x3ff20000 0x1000>; | |
52 | cache-unified; | |
53 | cache-level = <2>; | |
54 | }; | |
5f03dc20 CD |
55 | |
56 | timer@35006000 { | |
57 | compatible = "bcm,kona-timer"; | |
58 | reg = <0x35006000 0x1000>; | |
59 | interrupts = <0x0 7 0x4>; | |
60 | clock-frequency = <32768>; | |
61 | }; | |
62 | ||
8ac49e04 | 63 | }; |