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Commit | Line | Data |
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12091112 SW |
1 | #include <dt-bindings/pinctrl/bcm2835.h> |
2 | #include "skeleton.dtsi" | |
ec9653b8 SA |
3 | |
4 | / { | |
5 | compatible = "brcm,bcm2835"; | |
6 | model = "BCM2835"; | |
89214f00 | 7 | interrupt-parent = <&intc>; |
ec9653b8 SA |
8 | |
9 | chosen { | |
407f9be4 | 10 | bootargs = "earlyprintk console=ttyAMA0"; |
ec9653b8 SA |
11 | }; |
12 | ||
13 | soc { | |
14 | compatible = "simple-bus"; | |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | ranges = <0x7e000000 0x20000000 0x02000000>; | |
89214f00 | 18 | |
25b2f1bd | 19 | timer@7e003000 { |
ee4af569 SA |
20 | compatible = "brcm,bcm2835-system-timer"; |
21 | reg = <0x7e003000 0x1000>; | |
22 | interrupts = <1 0>, <1 1>, <1 2>, <1 3>; | |
23 | clock-frequency = <1000000>; | |
24 | }; | |
25 | ||
89072339 FM |
26 | dma: dma@7e007000 { |
27 | compatible = "brcm,bcm2835-dma"; | |
28 | reg = <0x7e007000 0xf00>; | |
29 | interrupts = <1 16>, | |
30 | <1 17>, | |
31 | <1 18>, | |
32 | <1 19>, | |
33 | <1 20>, | |
34 | <1 21>, | |
35 | <1 22>, | |
36 | <1 23>, | |
37 | <1 24>, | |
38 | <1 25>, | |
39 | <1 26>, | |
40 | <1 27>, | |
41 | <1 28>; | |
42 | ||
43 | #dma-cells = <1>; | |
44 | brcm,dma-channel-mask = <0x7f35>; | |
45 | }; | |
46 | ||
25b2f1bd | 47 | intc: interrupt-controller@7e00b200 { |
89214f00 SA |
48 | compatible = "brcm,bcm2835-armctrl-ic"; |
49 | reg = <0x7e00b200 0x200>; | |
50 | interrupt-controller; | |
51 | #interrupt-cells = <2>; | |
52 | }; | |
407f9be4 | 53 | |
25b2f1bd | 54 | watchdog@7e100000 { |
d0f1c7ff SW |
55 | compatible = "brcm,bcm2835-pm-wdt"; |
56 | reg = <0x7e100000 0x28>; | |
57 | }; | |
58 | ||
25b2f1bd | 59 | rng@7e104000 { |
a1bf7082 LR |
60 | compatible = "brcm,bcm2835-rng"; |
61 | reg = <0x7e104000 0x10>; | |
62 | }; | |
63 | ||
25b2f1bd | 64 | gpio: gpio@7e200000 { |
805504ab SW |
65 | compatible = "brcm,bcm2835-gpio"; |
66 | reg = <0x7e200000 0xb4>; | |
67 | /* | |
68 | * The GPIO IP block is designed for 3 banks of GPIOs. | |
69 | * Each bank has a GPIO interrupt for itself. | |
70 | * There is an overall "any bank" interrupt. | |
71 | * In order, these are GIC interrupts 17, 18, 19, 20. | |
72 | * Since the BCM2835 only has 2 banks, the 2nd bank | |
73 | * interrupt output appears to be mirrored onto the | |
74 | * 3rd bank's interrupt signal. | |
75 | * So, a bank0 interrupt shows up on 17, 20, and | |
76 | * a bank1 interrupt shows up on 18, 19, 20! | |
77 | */ | |
78 | interrupts = <2 17>, <2 18>, <2 19>, <2 20>; | |
79 | ||
80 | gpio-controller; | |
81 | #gpio-cells = <2>; | |
82 | ||
83 | interrupt-controller; | |
84 | #interrupt-cells = <2>; | |
85 | }; | |
5186bf28 | 86 | |
25b2f1bd | 87 | uart@7e201000 { |
ef3c690c SW |
88 | compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; |
89 | reg = <0x7e201000 0x1000>; | |
90 | interrupts = <2 25>; | |
91 | clock-frequency = <3000000>; | |
92 | arm,primecell-periphid = <0x00241011>; | |
93 | }; | |
94 | ||
9511cc4d FM |
95 | i2s: i2s@7e203000 { |
96 | compatible = "brcm,bcm2835-i2s"; | |
97 | reg = <0x7e203000 0x20>, | |
98 | <0x7e101098 0x02>; | |
99 | ||
100 | dmas = <&dma 2>, | |
101 | <&dma 3>; | |
102 | dma-names = "tx", "rx"; | |
667bbd53 | 103 | status = "disabled"; |
9511cc4d FM |
104 | }; |
105 | ||
25b2f1bd | 106 | spi: spi@7e204000 { |
6ce5f02e SW |
107 | compatible = "brcm,bcm2835-spi"; |
108 | reg = <0x7e204000 0x1000>; | |
109 | interrupts = <2 22>; | |
110 | clocks = <&clk_spi>; | |
111 | #address-cells = <1>; | |
112 | #size-cells = <0>; | |
113 | status = "disabled"; | |
114 | }; | |
115 | ||
64146f20 | 116 | i2c0: i2c@7e205000 { |
232fed48 SW |
117 | compatible = "brcm,bcm2835-i2c"; |
118 | reg = <0x7e205000 0x1000>; | |
119 | interrupts = <2 21>; | |
120 | clocks = <&clk_i2c>; | |
a31ab44e SW |
121 | #address-cells = <1>; |
122 | #size-cells = <0>; | |
232fed48 SW |
123 | status = "disabled"; |
124 | }; | |
125 | ||
25b2f1bd | 126 | sdhci: sdhci@7e300000 { |
ef3c690c SW |
127 | compatible = "brcm,bcm2835-sdhci"; |
128 | reg = <0x7e300000 0x100>; | |
129 | interrupts = <2 30>; | |
130 | clocks = <&clk_mmc>; | |
131 | status = "disabled"; | |
132 | }; | |
133 | ||
25b2f1bd | 134 | i2c1: i2c@7e804000 { |
232fed48 SW |
135 | compatible = "brcm,bcm2835-i2c"; |
136 | reg = <0x7e804000 0x1000>; | |
137 | interrupts = <2 21>; | |
138 | clocks = <&clk_i2c>; | |
a31ab44e SW |
139 | #address-cells = <1>; |
140 | #size-cells = <0>; | |
232fed48 SW |
141 | status = "disabled"; |
142 | }; | |
143 | ||
25b2f1bd | 144 | usb@7e980000 { |
5631e7f4 SW |
145 | compatible = "brcm,bcm2835-usb"; |
146 | reg = <0x7e980000 0x10000>; | |
147 | interrupts = <1 9>; | |
148 | }; | |
14ac652b VW |
149 | |
150 | arm-pmu { | |
151 | compatible = "arm,arm1176-pmu"; | |
152 | }; | |
5186bf28 SW |
153 | }; |
154 | ||
9692c191 SW |
155 | clocks { |
156 | compatible = "simple-bus"; | |
157 | #address-cells = <1>; | |
158 | #size-cells = <0>; | |
232fed48 | 159 | |
b7c6c176 | 160 | clk_mmc: clock@0 { |
9692c191 SW |
161 | compatible = "fixed-clock"; |
162 | reg = <0>; | |
163 | #clock-cells = <0>; | |
b7c6c176 | 164 | clock-output-names = "mmc"; |
9692c191 SW |
165 | clock-frequency = <100000000>; |
166 | }; | |
167 | ||
b7c6c176 | 168 | clk_i2c: clock@1 { |
9692c191 SW |
169 | compatible = "fixed-clock"; |
170 | reg = <1>; | |
171 | #clock-cells = <0>; | |
b7c6c176 | 172 | clock-output-names = "i2c"; |
2837a1d4 | 173 | clock-frequency = <250000000>; |
9692c191 | 174 | }; |
6ce5f02e | 175 | |
b7c6c176 | 176 | clk_spi: clock@2 { |
6ce5f02e SW |
177 | compatible = "fixed-clock"; |
178 | reg = <2>; | |
179 | #clock-cells = <0>; | |
b7c6c176 | 180 | clock-output-names = "spi"; |
6ce5f02e SW |
181 | clock-frequency = <250000000>; |
182 | }; | |
ec9653b8 SA |
183 | }; |
184 | }; |