]>
Commit | Line | Data |
---|---|---|
ec9653b8 SA |
1 | /include/ "skeleton.dtsi" |
2 | ||
3 | / { | |
4 | compatible = "brcm,bcm2835"; | |
5 | model = "BCM2835"; | |
89214f00 | 6 | interrupt-parent = <&intc>; |
ec9653b8 SA |
7 | |
8 | chosen { | |
407f9be4 | 9 | bootargs = "earlyprintk console=ttyAMA0"; |
ec9653b8 SA |
10 | }; |
11 | ||
12 | soc { | |
13 | compatible = "simple-bus"; | |
14 | #address-cells = <1>; | |
15 | #size-cells = <1>; | |
16 | ranges = <0x7e000000 0x20000000 0x02000000>; | |
89214f00 | 17 | |
ee4af569 SA |
18 | timer { |
19 | compatible = "brcm,bcm2835-system-timer"; | |
20 | reg = <0x7e003000 0x1000>; | |
21 | interrupts = <1 0>, <1 1>, <1 2>, <1 3>; | |
22 | clock-frequency = <1000000>; | |
23 | }; | |
24 | ||
89214f00 SA |
25 | intc: interrupt-controller { |
26 | compatible = "brcm,bcm2835-armctrl-ic"; | |
27 | reg = <0x7e00b200 0x200>; | |
28 | interrupt-controller; | |
29 | #interrupt-cells = <2>; | |
30 | }; | |
407f9be4 | 31 | |
d0f1c7ff SW |
32 | watchdog { |
33 | compatible = "brcm,bcm2835-pm-wdt"; | |
34 | reg = <0x7e100000 0x28>; | |
35 | }; | |
36 | ||
407f9be4 SA |
37 | uart@20201000 { |
38 | compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; | |
39 | reg = <0x7e201000 0x1000>; | |
40 | interrupts = <2 25>; | |
41 | clock-frequency = <3000000>; | |
42 | }; | |
805504ab SW |
43 | |
44 | gpio: gpio { | |
45 | compatible = "brcm,bcm2835-gpio"; | |
46 | reg = <0x7e200000 0xb4>; | |
47 | /* | |
48 | * The GPIO IP block is designed for 3 banks of GPIOs. | |
49 | * Each bank has a GPIO interrupt for itself. | |
50 | * There is an overall "any bank" interrupt. | |
51 | * In order, these are GIC interrupts 17, 18, 19, 20. | |
52 | * Since the BCM2835 only has 2 banks, the 2nd bank | |
53 | * interrupt output appears to be mirrored onto the | |
54 | * 3rd bank's interrupt signal. | |
55 | * So, a bank0 interrupt shows up on 17, 20, and | |
56 | * a bank1 interrupt shows up on 18, 19, 20! | |
57 | */ | |
58 | interrupts = <2 17>, <2 18>, <2 19>, <2 20>; | |
59 | ||
60 | gpio-controller; | |
61 | #gpio-cells = <2>; | |
62 | ||
63 | interrupt-controller; | |
64 | #interrupt-cells = <2>; | |
65 | }; | |
5186bf28 | 66 | |
6ce5f02e SW |
67 | spi: spi@20204000 { |
68 | compatible = "brcm,bcm2835-spi"; | |
69 | reg = <0x7e204000 0x1000>; | |
70 | interrupts = <2 22>; | |
71 | clocks = <&clk_spi>; | |
72 | #address-cells = <1>; | |
73 | #size-cells = <0>; | |
74 | status = "disabled"; | |
75 | }; | |
76 | ||
232fed48 SW |
77 | i2c0: i2c@20205000 { |
78 | compatible = "brcm,bcm2835-i2c"; | |
79 | reg = <0x7e205000 0x1000>; | |
80 | interrupts = <2 21>; | |
81 | clocks = <&clk_i2c>; | |
82 | status = "disabled"; | |
83 | }; | |
84 | ||
85 | i2c1: i2c@20804000 { | |
86 | compatible = "brcm,bcm2835-i2c"; | |
87 | reg = <0x7e804000 0x1000>; | |
88 | interrupts = <2 21>; | |
89 | clocks = <&clk_i2c>; | |
90 | status = "disabled"; | |
91 | }; | |
92 | ||
5186bf28 SW |
93 | sdhci: sdhci { |
94 | compatible = "brcm,bcm2835-sdhci"; | |
95 | reg = <0x7e300000 0x100>; | |
96 | interrupts = <2 30>; | |
97 | clocks = <&clk_mmc>; | |
98 | status = "disabled"; | |
99 | }; | |
100 | }; | |
101 | ||
9692c191 SW |
102 | clocks { |
103 | compatible = "simple-bus"; | |
104 | #address-cells = <1>; | |
105 | #size-cells = <0>; | |
232fed48 | 106 | |
9692c191 SW |
107 | clk_mmc: mmc { |
108 | compatible = "fixed-clock"; | |
109 | reg = <0>; | |
110 | #clock-cells = <0>; | |
111 | clock-frequency = <100000000>; | |
112 | }; | |
113 | ||
114 | clk_i2c: i2c { | |
115 | compatible = "fixed-clock"; | |
116 | reg = <1>; | |
117 | #clock-cells = <0>; | |
118 | clock-frequency = <150000000>; | |
119 | }; | |
6ce5f02e SW |
120 | |
121 | clk_spi: spi { | |
122 | compatible = "fixed-clock"; | |
123 | reg = <2>; | |
124 | #clock-cells = <0>; | |
125 | clock-frequency = <250000000>; | |
126 | }; | |
ec9653b8 SA |
127 | }; |
128 | }; |