[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / bcm283x.dtsi

#include <dt-bindings/pinctrl/bcm2835.h>
#include <dt-bindings/clock/bcm2835.h>
#include <dt-bindings/clock/bcm2835-aux.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/* firmware-provided startup stubs live here, where the secondary CPUs are
 * spinning.
 */
/memreserve/ 0x00000000 0x00001000;

/* This include file covers the common peripherals and configuration between
 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
 * bcm2835.dtsi and bcm2836.dtsi.
 */

/ {
	compatible = "brcm,bcm2835";
	model = "BCM2835";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;

			thermal-sensors = <&thermal>;

			trips {
				cpu-crit {
					temperature	= <80000>;
					hysteresis	= <0>;
					type		= "critical";
				};
			};

			cooling-maps {
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		timer@7e003000 {
			compatible = "brcm,bcm2835-system-timer";
			reg = <0x7e003000 0x1000>;
			interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
			/* This could be a reference to BCM2835_CLOCK_TIMER,
			 * but we don't have the driver using the common clock
			 * support yet.
			 */
			clock-frequency = <1000000>;
		};

		txp@7e004000 {
			compatible = "brcm,bcm2835-txp";
			reg = <0x7e004000 0x20>;
			interrupts = <1 11>;
		};

		dma: dma@7e007000 {
			compatible = "brcm,bcm2835-dma";
			reg = <0x7e007000 0xf00>;
			interrupts = <1 16>,
				     <1 17>,
				     <1 18>,
				     <1 19>,
				     <1 20>,
				     <1 21>,
				     <1 22>,
				     <1 23>,
				     <1 24>,
				     <1 25>,
				     <1 26>,
				     /* dma channel 11-14 share one irq */
				     <1 27>,
				     <1 27>,
				     <1 27>,
				     <1 27>,
				     /* unused shared irq for all channels */
				     <1 28>;
			interrupt-names = "dma0",
					  "dma1",
					  "dma2",
					  "dma3",
					  "dma4",
					  "dma5",
					  "dma6",
					  "dma7",
					  "dma8",
					  "dma9",
					  "dma10",
					  "dma11",
					  "dma12",
					  "dma13",
					  "dma14",
					  "dma-shared-all";
			#dma-cells = <1>;
			brcm,dma-channel-mask = <0x7f35>;
		};

		intc: interrupt-controller@7e00b200 {
			compatible = "brcm,bcm2835-armctrl-ic";
			reg = <0x7e00b200 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		watchdog@7e100000 {
			compatible = "brcm,bcm2835-pm-wdt";
			reg = <0x7e100000 0x28>;
		};

		clocks: cprman@7e101000 {
			compatible = "brcm,bcm2835-cprman";
			#clock-cells = <1>;
			reg = <0x7e101000 0x2000>;

			/* CPRMAN derives almost everything from the
			 * platform's oscillator.  However, the DSI
			 * pixel clocks come from the DSI analog PHY.
			 */
			clocks = <&clk_osc>,
				<&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
				<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
		};

		rng@7e104000 {
			compatible = "brcm,bcm2835-rng";
			reg = <0x7e104000 0x10>;
			interrupts = <2 29>;
		};

		mailbox: mailbox@7e00b880 {
			compatible = "brcm,bcm2835-mbox";
			reg = <0x7e00b880 0x40>;
			interrupts = <0 1>;
			#mbox-cells = <0>;
		};

		gpio: gpio@7e200000 {
			compatible = "brcm,bcm2835-gpio";
			reg = <0x7e200000 0xb4>;
			/*
			 * The GPIO IP block is designed for 3 banks of GPIOs.
			 * Each bank has a GPIO interrupt for itself.
			 * There is an overall "any bank" interrupt.
			 * In order, these are GIC interrupts 17, 18, 19, 20.
			 * Since the BCM2835 only has 2 banks, the 2nd bank
			 * interrupt output appears to be mirrored onto the
			 * 3rd bank's interrupt signal.
			 * So, a bank0 interrupt shows up on 17, 20, and
			 * a bank1 interrupt shows up on 18, 19, 20!
			 */
			interrupts = <2 17>, <2 18>, <2 19>, <2 20>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;

			/* Defines pin muxing groups according to
			 * BCM2835-ARM-Peripherals.pdf page 102.
			 *
			 * While each pin can have its mux selected
			 * for various functions individually, some
			 * groups only make sense to switch to a
			 * particular function together.
			 */
			dpi_gpio0: dpi_gpio0 {
				brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
					     12 13 14 15 16 17 18 19
					     20 21 22 23 24 25 26 27>;
				brcm,function = <BCM2835_FSEL_ALT2>;
			};
			emmc_gpio22: emmc_gpio22 {
				brcm,pins = <22 23 24 25 26 27>;
				brcm,function = <BCM2835_FSEL_ALT3>;
			};
			emmc_gpio34: emmc_gpio34 {
				brcm,pins = <34 35 36 37 38 39>;
				brcm,function = <BCM2835_FSEL_ALT3>;
				brcm,pull = <BCM2835_PUD_OFF
					     BCM2835_PUD_UP
					     BCM2835_PUD_UP
					     BCM2835_PUD_UP
					     BCM2835_PUD_UP
					     BCM2835_PUD_UP>;
			};
			emmc_gpio48: emmc_gpio48 {
				brcm,pins = <48 49 50 51 52 53>;
				brcm,function = <BCM2835_FSEL_ALT3>;
			};

			gpclk0_gpio4: gpclk0_gpio4 {
				brcm,pins = <4>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			gpclk1_gpio5: gpclk1_gpio5 {
				brcm,pins = <5>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			gpclk1_gpio42: gpclk1_gpio42 {
				brcm,pins = <42>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			gpclk1_gpio44: gpclk1_gpio44 {
				brcm,pins = <44>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			gpclk2_gpio6: gpclk2_gpio6 {
				brcm,pins = <6>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			gpclk2_gpio43: gpclk2_gpio43 {
				brcm,pins = <43>;
				brcm,function = <BCM2835_FSEL_ALT0>;
				brcm,pull = <BCM2835_PUD_OFF>;
			};

			i2c0_gpio0: i2c0_gpio0 {
				brcm,pins = <0 1>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			i2c0_gpio28: i2c0_gpio28 {
				brcm,pins = <28 29>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			i2c0_gpio44: i2c0_gpio44 {
				brcm,pins = <44 45>;
				brcm,function = <BCM2835_FSEL_ALT1>;
			};
			i2c1_gpio2: i2c1_gpio2 {
				brcm,pins = <2 3>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			i2c1_gpio44: i2c1_gpio44 {
				brcm,pins = <44 45>;
				brcm,function = <BCM2835_FSEL_ALT2>;
			};
			i2c_slave_gpio18: i2c_slave_gpio18 {
				brcm,pins = <18 19 20 21>;
				brcm,function = <BCM2835_FSEL_ALT3>;
			};

			jtag_gpio4: jtag_gpio4 {
				brcm,pins = <4 5 6 12 13>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			jtag_gpio22: jtag_gpio22 {
				brcm,pins = <22 23 24 25 26 27>;
				brcm,function = <BCM2835_FSEL_ALT4>;
			};

			pcm_gpio18: pcm_gpio18 {
				brcm,pins = <18 19 20 21>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			pcm_gpio28: pcm_gpio28 {
				brcm,pins = <28 29 30 31>;
				brcm,function = <BCM2835_FSEL_ALT2>;
			};

			pwm0_gpio12: pwm0_gpio12 {
				brcm,pins = <12>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			pwm0_gpio18: pwm0_gpio18 {
				brcm,pins = <18>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			pwm0_gpio40: pwm0_gpio40 {
				brcm,pins = <40>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			pwm1_gpio13: pwm1_gpio13 {
				brcm,pins = <13>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			pwm1_gpio19: pwm1_gpio19 {
				brcm,pins = <19>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			pwm1_gpio41: pwm1_gpio41 {
				brcm,pins = <41>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			pwm1_gpio45: pwm1_gpio45 {
				brcm,pins = <45>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};

			sdhost_gpio48: sdhost_gpio48 {
				brcm,pins = <48 49 50 51 52 53>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};

			spi0_gpio7: spi0_gpio7 {
				brcm,pins = <7 8 9 10 11>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			spi0_gpio35: spi0_gpio35 {
				brcm,pins = <35 36 37 38 39>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			spi1_gpio16: spi1_gpio16 {
				brcm,pins = <16 17 18 19 20 21>;
				brcm,function = <BCM2835_FSEL_ALT4>;
			};
			spi2_gpio40: spi2_gpio40 {
				brcm,pins = <40 41 42 43 44 45>;
				brcm,function = <BCM2835_FSEL_ALT4>;
			};

			uart0_gpio14: uart0_gpio14 {
				brcm,pins = <14 15>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			/* Separate from the uart0_gpio14 group
			 * because it conflicts with spi1_gpio16, and
			 * people often run uart0 on the two pins
			 * without flow control.
			 */
			uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
				brcm,pins = <16 17>;
				brcm,function = <BCM2835_FSEL_ALT3>;
			};
			uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
				brcm,pins = <30 31>;
				brcm,function = <BCM2835_FSEL_ALT3>;
				brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
			};
			uart0_gpio32: uart0_gpio32 {
				brcm,pins = <32 33>;
				brcm,function = <BCM2835_FSEL_ALT3>;
				brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
			};
			uart0_gpio36: uart0_gpio36 {
				brcm,pins = <36 37>;
				brcm,function = <BCM2835_FSEL_ALT2>;
			};
			uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
				brcm,pins = <38 39>;
				brcm,function = <BCM2835_FSEL_ALT2>;
			};

			uart1_gpio14: uart1_gpio14 {
				brcm,pins = <14 15>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
				brcm,pins = <16 17>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			uart1_gpio32: uart1_gpio32 {
				brcm,pins = <32 33>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
				brcm,pins = <30 31>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			uart1_gpio40: uart1_gpio40 {
				brcm,pins = <40 41>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
				brcm,pins = <42 43>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
		};

		uart0: serial@7e201000 {
			compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
			reg = <0x7e201000 0x1000>;
			interrupts = <2 25>;
			clocks = <&clocks BCM2835_CLOCK_UART>,
				 <&clocks BCM2835_CLOCK_VPU>;
			clock-names = "uartclk", "apb_pclk";
			arm,primecell-periphid = <0x00241011>;
		};

		sdhost: mmc@7e202000 {
			compatible = "brcm,bcm2835-sdhost";
			reg = <0x7e202000 0x100>;
			interrupts = <2 24>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
			dmas = <&dma 13>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		i2s: i2s@7e203000 {
			compatible = "brcm,bcm2835-i2s";
			reg = <0x7e203000 0x24>;
			clocks = <&clocks BCM2835_CLOCK_PCM>;

			dmas = <&dma 2>,
			       <&dma 3>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		spi: spi@7e204000 {
			compatible = "brcm,bcm2835-spi";
			reg = <0x7e204000 0x1000>;
			interrupts = <2 22>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c0: i2c@7e205000 {
			compatible = "brcm,bcm2835-i2c";
			reg = <0x7e205000 0x1000>;
			interrupts = <2 21>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		pixelvalve@7e206000 {
			compatible = "brcm,bcm2835-pixelvalve0";
			reg = <0x7e206000 0x100>;
			interrupts = <2 13>; /* pwa0 */
		};

		pixelvalve@7e207000 {
			compatible = "brcm,bcm2835-pixelvalve1";
			reg = <0x7e207000 0x100>;
			interrupts = <2 14>; /* pwa1 */
		};

		dpi: dpi@7e208000 {
			compatible = "brcm,bcm2835-dpi";
			reg = <0x7e208000 0x8c>;
			clocks = <&clocks BCM2835_CLOCK_VPU>,
				 <&clocks BCM2835_CLOCK_DPI>;
			clock-names = "core", "pixel";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		dsi0: dsi@7e209000 {
			compatible = "brcm,bcm2835-dsi0";
			reg = <0x7e209000 0x78>;
			interrupts = <2 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;

			clocks = <&clocks BCM2835_PLLA_DSI0>,
				 <&clocks BCM2835_CLOCK_DSI0E>,
				 <&clocks BCM2835_CLOCK_DSI0P>;
			clock-names = "phy", "escape", "pixel";

			clock-output-names = "dsi0_byte",
					     "dsi0_ddr2",
					     "dsi0_ddr";

		};

		thermal: thermal@7e212000 {
			compatible = "brcm,bcm2835-thermal";
			reg = <0x7e212000 0x8>;
			clocks = <&clocks BCM2835_CLOCK_TSENS>;
			#thermal-sensor-cells = <0>;
			status = "disabled";
		};

		aux: aux@7e215000 {
			compatible = "brcm,bcm2835-aux";
			#clock-cells = <1>;
			reg = <0x7e215000 0x8>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
		};

		uart1: serial@7e215040 {
			compatible = "brcm,bcm2835-aux-uart";
			reg = <0x7e215040 0x40>;
			interrupts = <1 29>;
			clocks = <&aux BCM2835_AUX_CLOCK_UART>;
			status = "disabled";
		};

		spi1: spi@7e215080 {
			compatible = "brcm,bcm2835-aux-spi";
			reg = <0x7e215080 0x40>;
			interrupts = <1 29>;
			clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@7e2150c0 {
			compatible = "brcm,bcm2835-aux-spi";
			reg = <0x7e2150c0 0x40>;
			interrupts = <1 29>;
			clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		pwm: pwm@7e20c000 {
			compatible = "brcm,bcm2835-pwm";
			reg = <0x7e20c000 0x28>;
			clocks = <&clocks BCM2835_CLOCK_PWM>;
			assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
			assigned-clock-rates = <10000000>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		sdhci: sdhci@7e300000 {
			compatible = "brcm,bcm2835-sdhci";
			reg = <0x7e300000 0x100>;
			interrupts = <2 30>;
			clocks = <&clocks BCM2835_CLOCK_EMMC>;
			status = "disabled";
		};

		hvs@7e400000 {
			compatible = "brcm,bcm2835-hvs";
			reg = <0x7e400000 0x6000>;
			interrupts = <2 1>;
		};

		dsi1: dsi@7e700000 {
			compatible = "brcm,bcm2835-dsi1";
			reg = <0x7e700000 0x8c>;
			interrupts = <2 12>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;

			clocks = <&clocks BCM2835_PLLD_DSI1>,
				 <&clocks BCM2835_CLOCK_DSI1E>,
				 <&clocks BCM2835_CLOCK_DSI1P>;
			clock-names = "phy", "escape", "pixel";

			clock-output-names = "dsi1_byte",
					     "dsi1_ddr2",
					     "dsi1_ddr";

			status = "disabled";
		};

		i2c1: i2c@7e804000 {
			compatible = "brcm,bcm2835-i2c";
			reg = <0x7e804000 0x1000>;
			interrupts = <2 21>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@7e805000 {
			compatible = "brcm,bcm2835-i2c";
			reg = <0x7e805000 0x1000>;
			interrupts = <2 21>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		vec: vec@7e806000 {
			compatible = "brcm,bcm2835-vec";
			reg = <0x7e806000 0x1000>;
			clocks = <&clocks BCM2835_CLOCK_VEC>;
			interrupts = <2 27>;
			status = "disabled";
		};

		pixelvalve@7e807000 {
			compatible = "brcm,bcm2835-pixelvalve2";
			reg = <0x7e807000 0x100>;
			interrupts = <2 10>; /* pixelvalve */
		};

		hdmi: hdmi@7e902000 {
			compatible = "brcm,bcm2835-hdmi";
			reg = <0x7e902000 0x600>,
			      <0x7e808000 0x100>;
			interrupts = <2 8>, <2 9>;
			ddc = <&i2c2>;
			clocks = <&clocks BCM2835_PLLH_PIX>,
				 <&clocks BCM2835_CLOCK_HSM>;
			clock-names = "pixel", "hdmi";
			dmas = <&dma 17>;
			dma-names = "audio-rx";
			status = "disabled";
		};

		usb: usb@7e980000 {
			compatible = "brcm,bcm2835-usb";
			reg = <0x7e980000 0x10000>;
			interrupts = <1 9>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clk_usb>;
			clock-names = "otg";
			phys = <&usbphy>;
			phy-names = "usb2-phy";
		};

		v3d: v3d@7ec00000 {
			compatible = "brcm,bcm2835-v3d";
			reg = <0x7ec00000 0x1000>;
			interrupts = <1 10>;
		};

		vc4: gpu {
			compatible = "brcm,bcm2835-vc4";
		};
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		/* The oscillator is the root of the clock tree. */
		clk_osc: clock@3 {
			compatible = "fixed-clock";
			reg = <3>;
			#clock-cells = <0>;
			clock-output-names = "osc";
			clock-frequency = <19200000>;
		};

		clk_usb: clock@4 {
			compatible = "fixed-clock";
			reg = <4>;
			#clock-cells = <0>;
			clock-output-names = "otg";
			clock-frequency = <480000000>;
		};
	};

	usbphy: phy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};
Commit	Line	Data
548c3a39 EA	1	#include <dt-bindings/pinctrl/bcm2835.h>
548c3a39 EA	2	#include <dt-bindings/clock/bcm2835.h>
f974d685	3	#include <dt-bindings/clock/bcm2835-aux.h>
49ac67e0	4	#include <dt-bindings/gpio/gpio.h>
b12f5d0f	5	#include <dt-bindings/interrupt-controller/irq.h>
548c3a39	6
b0804ed0 PE	7	/* firmware-provided startup stubs live here, where the secondary CPUs are
	8	* spinning.
	9	*/
	10	/memreserve/ 0x00000000 0x00001000;
	11
548c3a39 EA	12	/* This include file covers the common peripherals and configuration between
	13	* bcm2835 and bcm2836 implementations, leaving the CPU configuration to
	14	* bcm2835.dtsi and bcm2836.dtsi.
	15	*/
	16
	17	/ {
	18	compatible = "brcm,bcm2835";
	19	model = "BCM2835";
	20	interrupt-parent = <&intc>;
6b7b554d IC	21	#address-cells = <1>;
6b7b554d IC	22	#size-cells = <1>;
548c3a39	23
f08f58a2 LP	24	aliases {
	25	serial0 = &uart0;
	26	serial1 = &uart1;
	27	};
	28
548c3a39	29	chosen {
f08f58a2	30	stdout-path = "serial0:115200n8";
548c3a39 EA	31	};
548c3a39 EA	32
0fe4d218 SW	33	thermal-zones {
	34	cpu_thermal: cpu-thermal {
	35	polling-delay-passive = <0>;
	36	polling-delay = <1000>;
	37
	38	thermal-sensors = <&thermal>;
	39
	40	trips {
	41	cpu-crit {
	42	temperature = <80000>;
	43	hysteresis = <0>;
	44	type = "critical";
	45	};
	46	};
	47
	48	cooling-maps {
	49	};
	50	};
	51	};
	52
548c3a39 EA	53	soc {
	54	compatible = "simple-bus";
	55	#address-cells = <1>;
	56	#size-cells = <1>;
	57
	58	timer@7e003000 {
	59	compatible = "brcm,bcm2835-system-timer";
	60	reg = <0x7e003000 0x1000>;
	61	interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
	62	/* This could be a reference to BCM2835_CLOCK_TIMER,
	63	* but we don't have the driver using the common clock
	64	* support yet.
	65	*/
	66	clock-frequency = <1000000>;
	67	};
	68
b7dd29b4 BB	69	txp@7e004000 {
	70	compatible = "brcm,bcm2835-txp";
	71	reg = <0x7e004000 0x20>;
	72	interrupts = <1 11>;
	73	};
	74
548c3a39 EA	75	dma: dma@7e007000 {
	76	compatible = "brcm,bcm2835-dma";
	77	reg = <0x7e007000 0xf00>;
	78	interrupts = <1 16>,
	79	<1 17>,
	80	<1 18>,
	81	<1 19>,
	82	<1 20>,
	83	<1 21>,
	84	<1 22>,
	85	<1 23>,
	86	<1 24>,
	87	<1 25>,
	88	<1 26>,
9bc0fa53	89	/* dma channel 11-14 share one irq */
548c3a39	90	<1 27>,
9bc0fa53 MS	91	<1 27>,
	92	<1 27>,
	93	<1 27>,
	94	/* unused shared irq for all channels */
548c3a39	95	<1 28>;
9bc0fa53 MS	96	interrupt-names = "dma0",
	97	"dma1",
	98	"dma2",
	99	"dma3",
	100	"dma4",
	101	"dma5",
	102	"dma6",
	103	"dma7",
	104	"dma8",
	105	"dma9",
	106	"dma10",
	107	"dma11",
	108	"dma12",
	109	"dma13",
	110	"dma14",
	111	"dma-shared-all";
548c3a39 EA	112	#dma-cells = <1>;
	113	brcm,dma-channel-mask = <0x7f35>;
	114	};
	115
	116	intc: interrupt-controller@7e00b200 {
	117	compatible = "brcm,bcm2835-armctrl-ic";
	118	reg = <0x7e00b200 0x200>;
	119	interrupt-controller;
	120	#interrupt-cells = <2>;
	121	};
	122
	123	watchdog@7e100000 {
	124	compatible = "brcm,bcm2835-pm-wdt";
	125	reg = <0x7e100000 0x28>;
	126	};
	127
	128	clocks: cprman@7e101000 {
	129	compatible = "brcm,bcm2835-cprman";
	130	#clock-cells = <1>;
	131	reg = <0x7e101000 0x2000>;
	132
4aba4cf8 EA	133	/* CPRMAN derives almost everything from the
	134	* platform's oscillator. However, the DSI
	135	* pixel clocks come from the DSI analog PHY.
548c3a39	136	*/
4aba4cf8 EA	137	clocks = <&clk_osc>,
	138	<&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
	139	<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
548c3a39 EA	140	};
	141
	142	rng@7e104000 {
	143	compatible = "brcm,bcm2835-rng";
	144	reg = <0x7e104000 0x10>;
4034600e	145	interrupts = <2 29>;
548c3a39 EA	146	};
548c3a39 EA	147
7d891a68	148	mailbox: mailbox@7e00b880 {
548c3a39 EA	149	compatible = "brcm,bcm2835-mbox";
	150	reg = <0x7e00b880 0x40>;
	151	interrupts = <0 1>;
	152	#mbox-cells = <0>;
	153	};
	154
	155	gpio: gpio@7e200000 {
	156	compatible = "brcm,bcm2835-gpio";
	157	reg = <0x7e200000 0xb4>;
	158	/*
	159	* The GPIO IP block is designed for 3 banks of GPIOs.
	160	* Each bank has a GPIO interrupt for itself.
	161	* There is an overall "any bank" interrupt.
	162	* In order, these are GIC interrupts 17, 18, 19, 20.
	163	* Since the BCM2835 only has 2 banks, the 2nd bank
	164	* interrupt output appears to be mirrored onto the
	165	* 3rd bank's interrupt signal.
	166	* So, a bank0 interrupt shows up on 17, 20, and
	167	* a bank1 interrupt shows up on 18, 19, 20!
	168	*/
	169	interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
	170
	171	gpio-controller;
	172	#gpio-cells = <2>;
	173
	174	interrupt-controller;
	175	#interrupt-cells = <2>;
21ff8439 EA	176
	177	/* Defines pin muxing groups according to
	178	* BCM2835-ARM-Peripherals.pdf page 102.
	179	*
	180	* While each pin can have its mux selected
	181	* for various functions individually, some
	182	* groups only make sense to switch to a
	183	* particular function together.
	184	*/
	185	dpi_gpio0: dpi_gpio0 {
	186	brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
	187	12 13 14 15 16 17 18 19
	188	20 21 22 23 24 25 26 27>;
	189	brcm,function = <BCM2835_FSEL_ALT2>;
	190	};
	191	emmc_gpio22: emmc_gpio22 {
	192	brcm,pins = <22 23 24 25 26 27>;
	193	brcm,function = <BCM2835_FSEL_ALT3>;
	194	};
	195	emmc_gpio34: emmc_gpio34 {
	196	brcm,pins = <34 35 36 37 38 39>;
	197	brcm,function = <BCM2835_FSEL_ALT3>;
	198	brcm,pull = <BCM2835_PUD_OFF
	199	BCM2835_PUD_UP
	200	BCM2835_PUD_UP
	201	BCM2835_PUD_UP
	202	BCM2835_PUD_UP
	203	BCM2835_PUD_UP>;
	204	};
	205	emmc_gpio48: emmc_gpio48 {
	206	brcm,pins = <48 49 50 51 52 53>;
	207	brcm,function = <BCM2835_FSEL_ALT3>;
	208	};
	209
	210	gpclk0_gpio4: gpclk0_gpio4 {
	211	brcm,pins = <4>;
	212	brcm,function = <BCM2835_FSEL_ALT0>;
	213	};
	214	gpclk1_gpio5: gpclk1_gpio5 {
	215	brcm,pins = <5>;
	216	brcm,function = <BCM2835_FSEL_ALT0>;
	217	};
	218	gpclk1_gpio42: gpclk1_gpio42 {
	219	brcm,pins = <42>;
	220	brcm,function = <BCM2835_FSEL_ALT0>;
	221	};
	222	gpclk1_gpio44: gpclk1_gpio44 {
	223	brcm,pins = <44>;
	224	brcm,function = <BCM2835_FSEL_ALT0>;
	225	};
	226	gpclk2_gpio6: gpclk2_gpio6 {
	227	brcm,pins = <6>;
	228	brcm,function = <BCM2835_FSEL_ALT0>;
	229	};
	230	gpclk2_gpio43: gpclk2_gpio43 {
	231	brcm,pins = <43>;
	232	brcm,function = <BCM2835_FSEL_ALT0>;
a166ae40	233	brcm,pull = <BCM2835_PUD_OFF>;
21ff8439 EA	234	};
	235
	236	i2c0_gpio0: i2c0_gpio0 {
	237	brcm,pins = <0 1>;
	238	brcm,function = <BCM2835_FSEL_ALT0>;
	239	};
843b2287 BS	240	i2c0_gpio28: i2c0_gpio28 {
843b2287 BS	241	brcm,pins = <28 29>;
21ff8439 EA	242	brcm,function = <BCM2835_FSEL_ALT0>;
	243	};
	244	i2c0_gpio44: i2c0_gpio44 {
	245	brcm,pins = <44 45>;
	246	brcm,function = <BCM2835_FSEL_ALT1>;
	247	};
	248	i2c1_gpio2: i2c1_gpio2 {
	249	brcm,pins = <2 3>;
	250	brcm,function = <BCM2835_FSEL_ALT0>;
	251	};
	252	i2c1_gpio44: i2c1_gpio44 {
	253	brcm,pins = <44 45>;
	254	brcm,function = <BCM2835_FSEL_ALT2>;
	255	};
	256	i2c_slave_gpio18: i2c_slave_gpio18 {
	257	brcm,pins = <18 19 20 21>;
	258	brcm,function = <BCM2835_FSEL_ALT3>;
	259	};
	260
	261	jtag_gpio4: jtag_gpio4 {
	262	brcm,pins = <4 5 6 12 13>;
1a012cb2	263	brcm,function = <BCM2835_FSEL_ALT5>;
21ff8439 EA	264	};
	265	jtag_gpio22: jtag_gpio22 {
	266	brcm,pins = <22 23 24 25 26 27>;
	267	brcm,function = <BCM2835_FSEL_ALT4>;
	268	};
	269
	270	pcm_gpio18: pcm_gpio18 {
	271	brcm,pins = <18 19 20 21>;
	272	brcm,function = <BCM2835_FSEL_ALT0>;
	273	};
	274	pcm_gpio28: pcm_gpio28 {
	275	brcm,pins = <28 29 30 31>;
	276	brcm,function = <BCM2835_FSEL_ALT2>;
	277	};
	278
	279	pwm0_gpio12: pwm0_gpio12 {
	280	brcm,pins = <12>;
	281	brcm,function = <BCM2835_FSEL_ALT0>;
	282	};
	283	pwm0_gpio18: pwm0_gpio18 {
	284	brcm,pins = <18>;
	285	brcm,function = <BCM2835_FSEL_ALT5>;
	286	};
	287	pwm0_gpio40: pwm0_gpio40 {
	288	brcm,pins = <40>;
	289	brcm,function = <BCM2835_FSEL_ALT0>;
	290	};
	291	pwm1_gpio13: pwm1_gpio13 {
	292	brcm,pins = <13>;
	293	brcm,function = <BCM2835_FSEL_ALT0>;
	294	};
	295	pwm1_gpio19: pwm1_gpio19 {
	296	brcm,pins = <19>;
	297	brcm,function = <BCM2835_FSEL_ALT5>;
	298	};
	299	pwm1_gpio41: pwm1_gpio41 {
	300	brcm,pins = <41>;
	301	brcm,function = <BCM2835_FSEL_ALT0>;
	302	};
	303	pwm1_gpio45: pwm1_gpio45 {
	304	brcm,pins = <45>;
	305	brcm,function = <BCM2835_FSEL_ALT0>;
	306	};
	307
	308	sdhost_gpio48: sdhost_gpio48 {
	309	brcm,pins = <48 49 50 51 52 53>;
	310	brcm,function = <BCM2835_FSEL_ALT0>;
	311	};
	312
	313	spi0_gpio7: spi0_gpio7 {
	314	brcm,pins = <7 8 9 10 11>;
	315	brcm,function = <BCM2835_FSEL_ALT0>;
	316	};
	317	spi0_gpio35: spi0_gpio35 {
	318	brcm,pins = <35 36 37 38 39>;
	319	brcm,function = <BCM2835_FSEL_ALT0>;
	320	};
	321	spi1_gpio16: spi1_gpio16 {
	322	brcm,pins = <16 17 18 19 20 21>;
	323	brcm,function = <BCM2835_FSEL_ALT4>;
	324	};
	325	spi2_gpio40: spi2_gpio40 {
	326	brcm,pins = <40 41 42 43 44 45>;
	327	brcm,function = <BCM2835_FSEL_ALT4>;
328	};
329
330	uart0_gpio14: uart0_gpio14 {
331	brcm,pins = <14 15>;
332	brcm,function = <BCM2835_FSEL_ALT0>;
333	};
334	/* Separate from the uart0_gpio14 group
335	* because it conflicts with spi1_gpio16, and
336	* people often run uart0 on the two pins
ec8542cb	337	* without flow control.
21ff8439 EA	338	*/
	339	uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
	340	brcm,pins = <16 17>;
	341	brcm,function = <BCM2835_FSEL_ALT3>;
	342	};
ec8542cb	343	uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
21ff8439 EA	344	brcm,pins = <30 31>;
21ff8439 EA	345	brcm,function = <BCM2835_FSEL_ALT3>;
a166ae40	346	brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
21ff8439	347	};
ec8542cb	348	uart0_gpio32: uart0_gpio32 {
21ff8439 EA	349	brcm,pins = <32 33>;
21ff8439 EA	350	brcm,function = <BCM2835_FSEL_ALT3>;
a166ae40	351	brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
21ff8439	352	};
e1be65a5 BS	353	uart0_gpio36: uart0_gpio36 {
	354	brcm,pins = <36 37>;
	355	brcm,function = <BCM2835_FSEL_ALT2>;
	356	};
	357	uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
	358	brcm,pins = <38 39>;
	359	brcm,function = <BCM2835_FSEL_ALT2>;
	360	};
21ff8439 EA	361
	362	uart1_gpio14: uart1_gpio14 {
	363	brcm,pins = <14 15>;
	364	brcm,function = <BCM2835_FSEL_ALT5>;
	365	};
	366	uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
	367	brcm,pins = <16 17>;
	368	brcm,function = <BCM2835_FSEL_ALT5>;
	369	};
	370	uart1_gpio32: uart1_gpio32 {
	371	brcm,pins = <32 33>;
	372	brcm,function = <BCM2835_FSEL_ALT5>;
	373	};
	374	uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
	375	brcm,pins = <30 31>;
	376	brcm,function = <BCM2835_FSEL_ALT5>;
	377	};
21ff8439 EA	378	uart1_gpio40: uart1_gpio40 {
	379	brcm,pins = <40 41>;
	380	brcm,function = <BCM2835_FSEL_ALT5>;
	381	};
	382	uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
	383	brcm,pins = <42 43>;
	384	brcm,function = <BCM2835_FSEL_ALT5>;
	385	};
548c3a39 EA	386	};
548c3a39 EA	387
68e2ef17	388	uart0: serial@7e201000 {
548c3a39 EA	389	compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
	390	reg = <0x7e201000 0x1000>;
	391	interrupts = <2 25>;
	392	clocks = <&clocks BCM2835_CLOCK_UART>,
	393	<&clocks BCM2835_CLOCK_VPU>;
	394	clock-names = "uartclk", "apb_pclk";
	395	arm,primecell-periphid = <0x00241011>;
	396	};
	397
7f31a955 GH	398	sdhost: mmc@7e202000 {
	399	compatible = "brcm,bcm2835-sdhost";
	400	reg = <0x7e202000 0x100>;
	401	interrupts = <2 24>;
	402	clocks = <&clocks BCM2835_CLOCK_VPU>;
	403	dmas = <&dma 13>;
	404	dma-names = "rx-tx";
	405	status = "disabled";
	406	};
	407
548c3a39 EA	408	i2s: i2s@7e203000 {
548c3a39 EA	409	compatible = "brcm,bcm2835-i2s";
79c81fac SW	410	reg = <0x7e203000 0x24>;
79c81fac SW	411	clocks = <&clocks BCM2835_CLOCK_PCM>;
548c3a39 EA	412
	413	dmas = <&dma 2>,
	414	<&dma 3>;
	415	dma-names = "tx", "rx";
	416	status = "disabled";
	417	};
	418
	419	spi: spi@7e204000 {
	420	compatible = "brcm,bcm2835-spi";
	421	reg = <0x7e204000 0x1000>;
	422	interrupts = <2 22>;
	423	clocks = <&clocks BCM2835_CLOCK_VPU>;
	424	#address-cells = <1>;
	425	#size-cells = <0>;
	426	status = "disabled";
	427	};
	428
	429	i2c0: i2c@7e205000 {
	430	compatible = "brcm,bcm2835-i2c";
	431	reg = <0x7e205000 0x1000>;
	432	interrupts = <2 21>;
	433	clocks = <&clocks BCM2835_CLOCK_VPU>;
	434	#address-cells = <1>;
	435	#size-cells = <0>;
	436	status = "disabled";
	437	};
	438
49ac67e0 EA	439	pixelvalve@7e206000 {
	440	compatible = "brcm,bcm2835-pixelvalve0";
	441	reg = <0x7e206000 0x100>;
	442	interrupts = <2 13>; /* pwa0 */
	443	};
	444
	445	pixelvalve@7e207000 {
	446	compatible = "brcm,bcm2835-pixelvalve1";
	447	reg = <0x7e207000 0x100>;
	448	interrupts = <2 14>; /* pwa1 */
	449	};
	450
ae67cfc4 EA	451	dpi: dpi@7e208000 {
	452	compatible = "brcm,bcm2835-dpi";
	453	reg = <0x7e208000 0x8c>;
	454	clocks = <&clocks BCM2835_CLOCK_VPU>,
	455	<&clocks BCM2835_CLOCK_DPI>;
	456	clock-names = "core", "pixel";
	457	#address-cells = <1>;
	458	#size-cells = <0>;
	459	status = "disabled";
	460	};
	461
4aba4cf8 EA	462	dsi0: dsi@7e209000 {
	463	compatible = "brcm,bcm2835-dsi0";
	464	reg = <0x7e209000 0x78>;
	465	interrupts = <2 4>;
	466	#address-cells = <1>;
	467	#size-cells = <0>;
	468	#clock-cells = <1>;
	469
	470	clocks = <&clocks BCM2835_PLLA_DSI0>,
	471	<&clocks BCM2835_CLOCK_DSI0E>,
	472	<&clocks BCM2835_CLOCK_DSI0P>;
	473	clock-names = "phy", "escape", "pixel";
	474
	475	clock-output-names = "dsi0_byte",
	476	"dsi0_ddr2",
	477	"dsi0_ddr";
	478
	479	};
	480
43bac413 MS	481	thermal: thermal@7e212000 {
	482	compatible = "brcm,bcm2835-thermal";
	483	reg = <0x7e212000 0x8>;
	484	clocks = <&clocks BCM2835_CLOCK_TSENS>;
0fe4d218	485	#thermal-sensor-cells = <0>;
43bac413 MS	486	status = "disabled";
	487	};
	488
77ee2e1b	489	aux: aux@7e215000 {
ddc5c39a EA	490	compatible = "brcm,bcm2835-aux";
	491	#clock-cells = <1>;
	492	reg = <0x7e215000 0x8>;
	493	clocks = <&clocks BCM2835_CLOCK_VPU>;
	494	};
	495
1305141d MS	496	uart1: serial@7e215040 {
	497	compatible = "brcm,bcm2835-aux-uart";
	498	reg = <0x7e215040 0x40>;
	499	interrupts = <1 29>;
	500	clocks = <&aux BCM2835_AUX_CLOCK_UART>;
	501	status = "disabled";
	502	};
	503
f974d685 MS	504	spi1: spi@7e215080 {
	505	compatible = "brcm,bcm2835-aux-spi";
	506	reg = <0x7e215080 0x40>;
	507	interrupts = <1 29>;
	508	clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
	509	#address-cells = <1>;
	510	#size-cells = <0>;
	511	status = "disabled";
	512	};
	513
	514	spi2: spi@7e2150c0 {
	515	compatible = "brcm,bcm2835-aux-spi";
	516	reg = <0x7e2150c0 0x40>;
	517	interrupts = <1 29>;
	518	clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
	519	#address-cells = <1>;
	520	#size-cells = <0>;
	521	status = "disabled";
	522	};
	523
40ad4499 RP	524	pwm: pwm@7e20c000 {
	525	compatible = "brcm,bcm2835-pwm";
	526	reg = <0x7e20c000 0x28>;
	527	clocks = <&clocks BCM2835_CLOCK_PWM>;
	528	assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
	529	assigned-clock-rates = <10000000>;
	530	#pwm-cells = <2>;
	531	status = "disabled";
	532	};
	533
548c3a39 EA	534	sdhci: sdhci@7e300000 {
	535	compatible = "brcm,bcm2835-sdhci";
	536	reg = <0x7e300000 0x100>;
	537	interrupts = <2 30>;
	538	clocks = <&clocks BCM2835_CLOCK_EMMC>;
	539	status = "disabled";
	540	};
	541
49ac67e0 EA	542	hvs@7e400000 {
	543	compatible = "brcm,bcm2835-hvs";
	544	reg = <0x7e400000 0x6000>;
	545	interrupts = <2 1>;
	546	};
	547
4aba4cf8 EA	548	dsi1: dsi@7e700000 {
	549	compatible = "brcm,bcm2835-dsi1";
	550	reg = <0x7e700000 0x8c>;
	551	interrupts = <2 12>;
	552	#address-cells = <1>;
	553	#size-cells = <0>;
	554	#clock-cells = <1>;
	555
	556	clocks = <&clocks BCM2835_PLLD_DSI1>,
	557	<&clocks BCM2835_CLOCK_DSI1E>,
	558	<&clocks BCM2835_CLOCK_DSI1P>;
	559	clock-names = "phy", "escape", "pixel";
	560
	561	clock-output-names = "dsi1_byte",
	562	"dsi1_ddr2",
	563	"dsi1_ddr";
	564
	565	status = "disabled";
	566	};
	567
548c3a39 EA	568	i2c1: i2c@7e804000 {
	569	compatible = "brcm,bcm2835-i2c";
	570	reg = <0x7e804000 0x1000>;
	571	interrupts = <2 21>;
	572	clocks = <&clocks BCM2835_CLOCK_VPU>;
	573	#address-cells = <1>;
	574	#size-cells = <0>;
	575	status = "disabled";
	576	};
	577
	578	i2c2: i2c@7e805000 {
	579	compatible = "brcm,bcm2835-i2c";
	580	reg = <0x7e805000 0x1000>;
	581	interrupts = <2 21>;
	582	clocks = <&clocks BCM2835_CLOCK_VPU>;
	583	#address-cells = <1>;
	584	#size-cells = <0>;
	585	status = "disabled";
	586	};
	587
b899c452 BB	588	vec: vec@7e806000 {
	589	compatible = "brcm,bcm2835-vec";
	590	reg = <0x7e806000 0x1000>;
	591	clocks = <&clocks BCM2835_CLOCK_VEC>;
	592	interrupts = <2 27>;
	593	status = "disabled";
	594	};
	595
49ac67e0 EA	596	pixelvalve@7e807000 {
	597	compatible = "brcm,bcm2835-pixelvalve2";
	598	reg = <0x7e807000 0x100>;
	599	interrupts = <2 10>; /* pixelvalve */
	600	};
	601
	602	hdmi: hdmi@7e902000 {
	603	compatible = "brcm,bcm2835-hdmi";
	604	reg = <0x7e902000 0x600>,
	605	<0x7e808000 0x100>;
	606	interrupts = <2 8>, <2 9>;
	607	ddc = <&i2c2>;
	608	clocks = <&clocks BCM2835_PLLH_PIX>,
	609	<&clocks BCM2835_CLOCK_HSM>;
	610	clock-names = "pixel", "hdmi";
d46d2c63 BB	611	dmas = <&dma 17>;
d46d2c63 BB	612	dma-names = "audio-rx";
49ac67e0 EA	613	status = "disabled";
	614	};
	615
5ec6f2cd	616	usb: usb@7e980000 {
548c3a39 EA	617	compatible = "brcm,bcm2835-usb";
	618	reg = <0x7e980000 0x10000>;
	619	interrupts = <1 9>;
6a937927 LR	620	#address-cells = <1>;
6a937927 LR	621	#size-cells = <0>;
33145fac SW	622	clocks = <&clk_usb>;
33145fac SW	623	clock-names = "otg";
860a5d0b SW	624	phys = <&usbphy>;
860a5d0b SW	625	phy-names = "usb2-phy";
548c3a39	626	};
49ac67e0 EA	627
	628	v3d: v3d@7ec00000 {
	629	compatible = "brcm,bcm2835-v3d";
	630	reg = <0x7ec00000 0x1000>;
	631	interrupts = <1 10>;
	632	};
	633
	634	vc4: gpu {
	635	compatible = "brcm,bcm2835-vc4";
	636	};
548c3a39 EA	637	};
	638
	639	clocks {
	640	compatible = "simple-bus";
	641	#address-cells = <1>;
	642	#size-cells = <0>;
	643
	644	/* The oscillator is the root of the clock tree. */
	645	clk_osc: clock@3 {
	646	compatible = "fixed-clock";
	647	reg = <3>;
	648	#clock-cells = <0>;
	649	clock-output-names = "osc";
	650	clock-frequency = <19200000>;
	651	};
	652
33145fac SW	653	clk_usb: clock@4 {
	654	compatible = "fixed-clock";
	655	reg = <4>;
	656	#clock-cells = <0>;
	657	clock-output-names = "otg";
	658	clock-frequency = <480000000>;
	659	};
548c3a39	660	};
860a5d0b SW	661
	662	usbphy: phy {
	663	compatible = "usb-nop-xceiv";
014d6da6	664	#phy-cells = <0>;
860a5d0b	665	};
548c3a39	666	};