[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / bcm283x.dtsi

#include <dt-bindings/pinctrl/bcm2835.h>
#include <dt-bindings/clock/bcm2835.h>
#include <dt-bindings/clock/bcm2835-aux.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/soc/bcm2835-pm.h>

/* firmware-provided startup stubs live here, where the secondary CPUs are
 * spinning.
 */
/memreserve/ 0x00000000 0x00001000;

/* This include file covers the common peripherals and configuration between
 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
 * bcm2835.dtsi and bcm2836.dtsi.
 */

/ {
	compatible = "brcm,bcm2835";
	model = "BCM2835";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;

			thermal-sensors = <&thermal>;

			trips {
				cpu-crit {
					temperature	= <80000>;
					hysteresis	= <0>;
					type		= "critical";
				};
			};

			cooling-maps {
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		timer@7e003000 {
			compatible = "brcm,bcm2835-system-timer";
			reg = <0x7e003000 0x1000>;
			interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
			/* This could be a reference to BCM2835_CLOCK_TIMER,
			 * but we don't have the driver using the common clock
			 * support yet.
			 */
			clock-frequency = <1000000>;
		};

		txp@7e004000 {
			compatible = "brcm,bcm2835-txp";
			reg = <0x7e004000 0x20>;
			interrupts = <1 11>;
		};

		dma: dma@7e007000 {
			compatible = "brcm,bcm2835-dma";
			reg = <0x7e007000 0xf00>;
			interrupts = <1 16>,
				     <1 17>,
				     <1 18>,
				     <1 19>,
				     <1 20>,
				     <1 21>,
				     <1 22>,
				     <1 23>,
				     <1 24>,
				     <1 25>,
				     <1 26>,
				     /* dma channel 11-14 share one irq */
				     <1 27>,
				     <1 27>,
				     <1 27>,
				     <1 27>,
				     /* unused shared irq for all channels */
				     <1 28>;
			interrupt-names = "dma0",
					  "dma1",
					  "dma2",
					  "dma3",
					  "dma4",
					  "dma5",
					  "dma6",
					  "dma7",
					  "dma8",
					  "dma9",
					  "dma10",
					  "dma11",
					  "dma12",
					  "dma13",
					  "dma14",
					  "dma-shared-all";
			#dma-cells = <1>;
			brcm,dma-channel-mask = <0x7f35>;
		};

		intc: interrupt-controller@7e00b200 {
			compatible = "brcm,bcm2835-armctrl-ic";
			reg = <0x7e00b200 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pm: watchdog@7e100000 {
			compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
			#power-domain-cells = <1>;
			#reset-cells = <1>;
			reg = <0x7e100000 0x114>,
			      <0x7e00a000 0x24>;
			clocks = <&clocks BCM2835_CLOCK_V3D>,
				 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
				 <&clocks BCM2835_CLOCK_H264>,
				 <&clocks BCM2835_CLOCK_ISP>;
			clock-names = "v3d", "peri_image", "h264", "isp";
			system-power-controller;
		};

		clocks: cprman@7e101000 {
			compatible = "brcm,bcm2835-cprman";
			#clock-cells = <1>;
			reg = <0x7e101000 0x2000>;

			/* CPRMAN derives almost everything from the
			 * platform's oscillator.  However, the DSI
			 * pixel clocks come from the DSI analog PHY.
			 */
			clocks = <&clk_osc>,
				<&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
				<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
		};

		rng@7e104000 {
			compatible = "brcm,bcm2835-rng";
			reg = <0x7e104000 0x10>;
			interrupts = <2 29>;
		};

		mailbox: mailbox@7e00b880 {
			compatible = "brcm,bcm2835-mbox";
			reg = <0x7e00b880 0x40>;
			interrupts = <0 1>;
			#mbox-cells = <0>;
		};

		gpio: gpio@7e200000 {
			compatible = "brcm,bcm2835-gpio";
			reg = <0x7e200000 0xb4>;
			/*
			 * The GPIO IP block is designed for 3 banks of GPIOs.
			 * Each bank has a GPIO interrupt for itself.
			 * There is an overall "any bank" interrupt.
			 * In order, these are GIC interrupts 17, 18, 19, 20.
			 * Since the BCM2835 only has 2 banks, the 2nd bank
			 * interrupt output appears to be mirrored onto the
			 * 3rd bank's interrupt signal.
			 * So, a bank0 interrupt shows up on 17, 20, and
			 * a bank1 interrupt shows up on 18, 19, 20!
			 */
			interrupts = <2 17>, <2 18>, <2 19>, <2 20>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;

			/* Defines pin muxing groups according to
			 * BCM2835-ARM-Peripherals.pdf page 102.
			 *
			 * While each pin can have its mux selected
			 * for various functions individually, some
			 * groups only make sense to switch to a
			 * particular function together.
			 */
			dpi_gpio0: dpi_gpio0 {
				brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
					     12 13 14 15 16 17 18 19
					     20 21 22 23 24 25 26 27>;
				brcm,function = <BCM2835_FSEL_ALT2>;
			};
			emmc_gpio22: emmc_gpio22 {
				brcm,pins = <22 23 24 25 26 27>;
				brcm,function = <BCM2835_FSEL_ALT3>;
			};
			emmc_gpio34: emmc_gpio34 {
				brcm,pins = <34 35 36 37 38 39>;
				brcm,function = <BCM2835_FSEL_ALT3>;
				brcm,pull = <BCM2835_PUD_OFF
					     BCM2835_PUD_UP
					     BCM2835_PUD_UP
					     BCM2835_PUD_UP
					     BCM2835_PUD_UP
					     BCM2835_PUD_UP>;
			};
			emmc_gpio48: emmc_gpio48 {
				brcm,pins = <48 49 50 51 52 53>;
				brcm,function = <BCM2835_FSEL_ALT3>;
			};

			gpclk0_gpio4: gpclk0_gpio4 {
				brcm,pins = <4>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			gpclk1_gpio5: gpclk1_gpio5 {
				brcm,pins = <5>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			gpclk1_gpio42: gpclk1_gpio42 {
				brcm,pins = <42>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			gpclk1_gpio44: gpclk1_gpio44 {
				brcm,pins = <44>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			gpclk2_gpio6: gpclk2_gpio6 {
				brcm,pins = <6>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			gpclk2_gpio43: gpclk2_gpio43 {
				brcm,pins = <43>;
				brcm,function = <BCM2835_FSEL_ALT0>;
				brcm,pull = <BCM2835_PUD_OFF>;
			};

			i2c0_gpio0: i2c0_gpio0 {
				brcm,pins = <0 1>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			i2c0_gpio28: i2c0_gpio28 {
				brcm,pins = <28 29>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			i2c0_gpio44: i2c0_gpio44 {
				brcm,pins = <44 45>;
				brcm,function = <BCM2835_FSEL_ALT1>;
			};
			i2c1_gpio2: i2c1_gpio2 {
				brcm,pins = <2 3>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			i2c1_gpio44: i2c1_gpio44 {
				brcm,pins = <44 45>;
				brcm,function = <BCM2835_FSEL_ALT2>;
			};
			i2c_slave_gpio18: i2c_slave_gpio18 {
				brcm,pins = <18 19 20 21>;
				brcm,function = <BCM2835_FSEL_ALT3>;
			};

			jtag_gpio4: jtag_gpio4 {
				brcm,pins = <4 5 6 12 13>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			jtag_gpio22: jtag_gpio22 {
				brcm,pins = <22 23 24 25 26 27>;
				brcm,function = <BCM2835_FSEL_ALT4>;
			};

			pcm_gpio18: pcm_gpio18 {
				brcm,pins = <18 19 20 21>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			pcm_gpio28: pcm_gpio28 {
				brcm,pins = <28 29 30 31>;
				brcm,function = <BCM2835_FSEL_ALT2>;
			};

			pwm0_gpio12: pwm0_gpio12 {
				brcm,pins = <12>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			pwm0_gpio18: pwm0_gpio18 {
				brcm,pins = <18>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			pwm0_gpio40: pwm0_gpio40 {
				brcm,pins = <40>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			pwm1_gpio13: pwm1_gpio13 {
				brcm,pins = <13>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			pwm1_gpio19: pwm1_gpio19 {
				brcm,pins = <19>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			pwm1_gpio41: pwm1_gpio41 {
				brcm,pins = <41>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			pwm1_gpio45: pwm1_gpio45 {
				brcm,pins = <45>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};

			sdhost_gpio48: sdhost_gpio48 {
				brcm,pins = <48 49 50 51 52 53>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};

			spi0_gpio7: spi0_gpio7 {
				brcm,pins = <7 8 9 10 11>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			spi0_gpio35: spi0_gpio35 {
				brcm,pins = <35 36 37 38 39>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			spi1_gpio16: spi1_gpio16 {
				brcm,pins = <16 17 18 19 20 21>;
				brcm,function = <BCM2835_FSEL_ALT4>;
			};
			spi2_gpio40: spi2_gpio40 {
				brcm,pins = <40 41 42 43 44 45>;
				brcm,function = <BCM2835_FSEL_ALT4>;
			};

			uart0_gpio14: uart0_gpio14 {
				brcm,pins = <14 15>;
				brcm,function = <BCM2835_FSEL_ALT0>;
			};
			/* Separate from the uart0_gpio14 group
			 * because it conflicts with spi1_gpio16, and
			 * people often run uart0 on the two pins
			 * without flow control.
			 */
			uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
				brcm,pins = <16 17>;
				brcm,function = <BCM2835_FSEL_ALT3>;
			};
			uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
				brcm,pins = <30 31>;
				brcm,function = <BCM2835_FSEL_ALT3>;
				brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
			};
			uart0_gpio32: uart0_gpio32 {
				brcm,pins = <32 33>;
				brcm,function = <BCM2835_FSEL_ALT3>;
				brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
			};
			uart0_gpio36: uart0_gpio36 {
				brcm,pins = <36 37>;
				brcm,function = <BCM2835_FSEL_ALT2>;
			};
			uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
				brcm,pins = <38 39>;
				brcm,function = <BCM2835_FSEL_ALT2>;
			};

			uart1_gpio14: uart1_gpio14 {
				brcm,pins = <14 15>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
				brcm,pins = <16 17>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			uart1_gpio32: uart1_gpio32 {
				brcm,pins = <32 33>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
				brcm,pins = <30 31>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			uart1_gpio40: uart1_gpio40 {
				brcm,pins = <40 41>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
			uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
				brcm,pins = <42 43>;
				brcm,function = <BCM2835_FSEL_ALT5>;
			};
		};

		uart0: serial@7e201000 {
			compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
			reg = <0x7e201000 0x1000>;
			interrupts = <2 25>;
			clocks = <&clocks BCM2835_CLOCK_UART>,
				 <&clocks BCM2835_CLOCK_VPU>;
			clock-names = "uartclk", "apb_pclk";
			arm,primecell-periphid = <0x00241011>;
		};

		sdhost: mmc@7e202000 {
			compatible = "brcm,bcm2835-sdhost";
			reg = <0x7e202000 0x100>;
			interrupts = <2 24>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
			dmas = <&dma 13>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		i2s: i2s@7e203000 {
			compatible = "brcm,bcm2835-i2s";
			reg = <0x7e203000 0x24>;
			clocks = <&clocks BCM2835_CLOCK_PCM>;

			dmas = <&dma 2>,
			       <&dma 3>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		spi: spi@7e204000 {
			compatible = "brcm,bcm2835-spi";
			reg = <0x7e204000 0x1000>;
			interrupts = <2 22>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c0: i2c@7e205000 {
			compatible = "brcm,bcm2835-i2c";
			reg = <0x7e205000 0x1000>;
			interrupts = <2 21>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		pixelvalve@7e206000 {
			compatible = "brcm,bcm2835-pixelvalve0";
			reg = <0x7e206000 0x100>;
			interrupts = <2 13>; /* pwa0 */
		};

		pixelvalve@7e207000 {
			compatible = "brcm,bcm2835-pixelvalve1";
			reg = <0x7e207000 0x100>;
			interrupts = <2 14>; /* pwa1 */
		};

		dpi: dpi@7e208000 {
			compatible = "brcm,bcm2835-dpi";
			reg = <0x7e208000 0x8c>;
			clocks = <&clocks BCM2835_CLOCK_VPU>,
				 <&clocks BCM2835_CLOCK_DPI>;
			clock-names = "core", "pixel";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		dsi0: dsi@7e209000 {
			compatible = "brcm,bcm2835-dsi0";
			reg = <0x7e209000 0x78>;
			interrupts = <2 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;

			clocks = <&clocks BCM2835_PLLA_DSI0>,
				 <&clocks BCM2835_CLOCK_DSI0E>,
				 <&clocks BCM2835_CLOCK_DSI0P>;
			clock-names = "phy", "escape", "pixel";

			clock-output-names = "dsi0_byte",
					     "dsi0_ddr2",
					     "dsi0_ddr";

		};

		thermal: thermal@7e212000 {
			compatible = "brcm,bcm2835-thermal";
			reg = <0x7e212000 0x8>;
			clocks = <&clocks BCM2835_CLOCK_TSENS>;
			#thermal-sensor-cells = <0>;
			status = "disabled";
		};

		aux: aux@7e215000 {
			compatible = "brcm,bcm2835-aux";
			#clock-cells = <1>;
			reg = <0x7e215000 0x8>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
		};

		uart1: serial@7e215040 {
			compatible = "brcm,bcm2835-aux-uart";
			reg = <0x7e215040 0x40>;
			interrupts = <1 29>;
			clocks = <&aux BCM2835_AUX_CLOCK_UART>;
			status = "disabled";
		};

		spi1: spi@7e215080 {
			compatible = "brcm,bcm2835-aux-spi";
			reg = <0x7e215080 0x40>;
			interrupts = <1 29>;
			clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@7e2150c0 {
			compatible = "brcm,bcm2835-aux-spi";
			reg = <0x7e2150c0 0x40>;
			interrupts = <1 29>;
			clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		pwm: pwm@7e20c000 {
			compatible = "brcm,bcm2835-pwm";
			reg = <0x7e20c000 0x28>;
			clocks = <&clocks BCM2835_CLOCK_PWM>;
			assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
			assigned-clock-rates = <10000000>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		sdhci: sdhci@7e300000 {
			compatible = "brcm,bcm2835-sdhci";
			reg = <0x7e300000 0x100>;
			interrupts = <2 30>;
			clocks = <&clocks BCM2835_CLOCK_EMMC>;
			status = "disabled";
		};

		hvs@7e400000 {
			compatible = "brcm,bcm2835-hvs";
			reg = <0x7e400000 0x6000>;
			interrupts = <2 1>;
		};

		dsi1: dsi@7e700000 {
			compatible = "brcm,bcm2835-dsi1";
			reg = <0x7e700000 0x8c>;
			interrupts = <2 12>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;

			clocks = <&clocks BCM2835_PLLD_DSI1>,
				 <&clocks BCM2835_CLOCK_DSI1E>,
				 <&clocks BCM2835_CLOCK_DSI1P>;
			clock-names = "phy", "escape", "pixel";

			clock-output-names = "dsi1_byte",
					     "dsi1_ddr2",
					     "dsi1_ddr";

			status = "disabled";
		};

		i2c1: i2c@7e804000 {
			compatible = "brcm,bcm2835-i2c";
			reg = <0x7e804000 0x1000>;
			interrupts = <2 21>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@7e805000 {
			compatible = "brcm,bcm2835-i2c";
			reg = <0x7e805000 0x1000>;
			interrupts = <2 21>;
			clocks = <&clocks BCM2835_CLOCK_VPU>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		vec: vec@7e806000 {
			compatible = "brcm,bcm2835-vec";
			reg = <0x7e806000 0x1000>;
			clocks = <&clocks BCM2835_CLOCK_VEC>;
			interrupts = <2 27>;
			status = "disabled";
		};

		pixelvalve@7e807000 {
			compatible = "brcm,bcm2835-pixelvalve2";
			reg = <0x7e807000 0x100>;
			interrupts = <2 10>; /* pixelvalve */
		};

		hdmi: hdmi@7e902000 {
			compatible = "brcm,bcm2835-hdmi";
			reg = <0x7e902000 0x600>,
			      <0x7e808000 0x100>;
			interrupts = <2 8>, <2 9>;
			ddc = <&i2c2>;
			clocks = <&clocks BCM2835_PLLH_PIX>,
				 <&clocks BCM2835_CLOCK_HSM>;
			clock-names = "pixel", "hdmi";
			dmas = <&dma 17>;
			dma-names = "audio-rx";
			status = "disabled";
		};

		usb: usb@7e980000 {
			compatible = "brcm,bcm2835-usb";
			reg = <0x7e980000 0x10000>;
			interrupts = <1 9>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clk_usb>;
			clock-names = "otg";
			phys = <&usbphy>;
			phy-names = "usb2-phy";
		};

		v3d: v3d@7ec00000 {
			compatible = "brcm,bcm2835-v3d";
			reg = <0x7ec00000 0x1000>;
			interrupts = <1 10>;
			power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
		};

		vc4: gpu {
			compatible = "brcm,bcm2835-vc4";
		};
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		/* The oscillator is the root of the clock tree. */
		clk_osc: clock@3 {
			compatible = "fixed-clock";
			reg = <3>;
			#clock-cells = <0>;
			clock-output-names = "osc";
			clock-frequency = <19200000>;
		};

		clk_usb: clock@4 {
			compatible = "fixed-clock";
			reg = <4>;
			#clock-cells = <0>;
			clock-output-names = "otg";
			clock-frequency = <480000000>;
		};
	};

	usbphy: phy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};
Commit	Line	Data
548c3a39 EA	1	#include <dt-bindings/pinctrl/bcm2835.h>
548c3a39 EA	2	#include <dt-bindings/clock/bcm2835.h>
f974d685	3	#include <dt-bindings/clock/bcm2835-aux.h>
49ac67e0	4	#include <dt-bindings/gpio/gpio.h>
b12f5d0f	5	#include <dt-bindings/interrupt-controller/irq.h>
e1dc2b2e	6	#include <dt-bindings/soc/bcm2835-pm.h>
548c3a39	7
b0804ed0 PE	8	/* firmware-provided startup stubs live here, where the secondary CPUs are
	9	* spinning.
	10	*/
	11	/memreserve/ 0x00000000 0x00001000;
	12
548c3a39 EA	13	/* This include file covers the common peripherals and configuration between
	14	* bcm2835 and bcm2836 implementations, leaving the CPU configuration to
	15	* bcm2835.dtsi and bcm2836.dtsi.
	16	*/
	17
	18	/ {
	19	compatible = "brcm,bcm2835";
	20	model = "BCM2835";
	21	interrupt-parent = <&intc>;
6b7b554d IC	22	#address-cells = <1>;
6b7b554d IC	23	#size-cells = <1>;
548c3a39	24
f08f58a2 LP	25	aliases {
	26	serial0 = &uart0;
	27	serial1 = &uart1;
	28	};
	29
548c3a39	30	chosen {
f08f58a2	31	stdout-path = "serial0:115200n8";
548c3a39 EA	32	};
548c3a39 EA	33
0fe4d218 SW	34	thermal-zones {
	35	cpu_thermal: cpu-thermal {
	36	polling-delay-passive = <0>;
	37	polling-delay = <1000>;
	38
	39	thermal-sensors = <&thermal>;
	40
	41	trips {
	42	cpu-crit {
	43	temperature = <80000>;
	44	hysteresis = <0>;
	45	type = "critical";
	46	};
	47	};
	48
	49	cooling-maps {
	50	};
	51	};
	52	};
	53
548c3a39 EA	54	soc {
	55	compatible = "simple-bus";
	56	#address-cells = <1>;
	57	#size-cells = <1>;
	58
	59	timer@7e003000 {
	60	compatible = "brcm,bcm2835-system-timer";
	61	reg = <0x7e003000 0x1000>;
	62	interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
	63	/* This could be a reference to BCM2835_CLOCK_TIMER,
	64	* but we don't have the driver using the common clock
	65	* support yet.
	66	*/
	67	clock-frequency = <1000000>;
	68	};
	69
b7dd29b4 BB	70	txp@7e004000 {
	71	compatible = "brcm,bcm2835-txp";
	72	reg = <0x7e004000 0x20>;
	73	interrupts = <1 11>;
	74	};
	75
548c3a39 EA	76	dma: dma@7e007000 {
	77	compatible = "brcm,bcm2835-dma";
	78	reg = <0x7e007000 0xf00>;
	79	interrupts = <1 16>,
	80	<1 17>,
	81	<1 18>,
	82	<1 19>,
	83	<1 20>,
	84	<1 21>,
	85	<1 22>,
	86	<1 23>,
	87	<1 24>,
	88	<1 25>,
	89	<1 26>,
9bc0fa53	90	/* dma channel 11-14 share one irq */
548c3a39	91	<1 27>,
9bc0fa53 MS	92	<1 27>,
	93	<1 27>,
	94	<1 27>,
	95	/* unused shared irq for all channels */
548c3a39	96	<1 28>;
9bc0fa53 MS	97	interrupt-names = "dma0",
	98	"dma1",
	99	"dma2",
	100	"dma3",
	101	"dma4",
	102	"dma5",
	103	"dma6",
	104	"dma7",
	105	"dma8",
	106	"dma9",
	107	"dma10",
	108	"dma11",
	109	"dma12",
	110	"dma13",
	111	"dma14",
	112	"dma-shared-all";
548c3a39 EA	113	#dma-cells = <1>;
	114	brcm,dma-channel-mask = <0x7f35>;
	115	};
	116
	117	intc: interrupt-controller@7e00b200 {
	118	compatible = "brcm,bcm2835-armctrl-ic";
	119	reg = <0x7e00b200 0x200>;
	120	interrupt-controller;
	121	#interrupt-cells = <2>;
	122	};
	123
e1dc2b2e	124	pm: watchdog@7e100000 {
81fc035f EA	125	compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
	126	#power-domain-cells = <1>;
	127	#reset-cells = <1>;
	128	reg = <0x7e100000 0x114>,
	129	<0x7e00a000 0x24>;
	130	clocks = <&clocks BCM2835_CLOCK_V3D>,
	131	<&clocks BCM2835_CLOCK_PERI_IMAGE>,
	132	<&clocks BCM2835_CLOCK_H264>,
	133	<&clocks BCM2835_CLOCK_ISP>;
	134	clock-names = "v3d", "peri_image", "h264", "isp";
	135	system-power-controller;
548c3a39 EA	136	};
	137
	138	clocks: cprman@7e101000 {
	139	compatible = "brcm,bcm2835-cprman";
	140	#clock-cells = <1>;
	141	reg = <0x7e101000 0x2000>;
	142
4aba4cf8 EA	143	/* CPRMAN derives almost everything from the
	144	* platform's oscillator. However, the DSI
	145	* pixel clocks come from the DSI analog PHY.
548c3a39	146	*/
4aba4cf8 EA	147	clocks = <&clk_osc>,
	148	<&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
	149	<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
548c3a39 EA	150	};
	151
	152	rng@7e104000 {
	153	compatible = "brcm,bcm2835-rng";
	154	reg = <0x7e104000 0x10>;
4034600e	155	interrupts = <2 29>;
548c3a39 EA	156	};
548c3a39 EA	157
7d891a68	158	mailbox: mailbox@7e00b880 {
548c3a39 EA	159	compatible = "brcm,bcm2835-mbox";
	160	reg = <0x7e00b880 0x40>;
	161	interrupts = <0 1>;
	162	#mbox-cells = <0>;
	163	};
	164
	165	gpio: gpio@7e200000 {
	166	compatible = "brcm,bcm2835-gpio";
	167	reg = <0x7e200000 0xb4>;
	168	/*
	169	* The GPIO IP block is designed for 3 banks of GPIOs.
	170	* Each bank has a GPIO interrupt for itself.
	171	* There is an overall "any bank" interrupt.
	172	* In order, these are GIC interrupts 17, 18, 19, 20.
	173	* Since the BCM2835 only has 2 banks, the 2nd bank
	174	* interrupt output appears to be mirrored onto the
	175	* 3rd bank's interrupt signal.
	176	* So, a bank0 interrupt shows up on 17, 20, and
	177	* a bank1 interrupt shows up on 18, 19, 20!
	178	*/
	179	interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
	180
	181	gpio-controller;
	182	#gpio-cells = <2>;
	183
	184	interrupt-controller;
	185	#interrupt-cells = <2>;
21ff8439 EA	186
	187	/* Defines pin muxing groups according to
	188	* BCM2835-ARM-Peripherals.pdf page 102.
	189	*
	190	* While each pin can have its mux selected
	191	* for various functions individually, some
	192	* groups only make sense to switch to a
	193	* particular function together.
	194	*/
	195	dpi_gpio0: dpi_gpio0 {
	196	brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
	197	12 13 14 15 16 17 18 19
	198	20 21 22 23 24 25 26 27>;
	199	brcm,function = <BCM2835_FSEL_ALT2>;
	200	};
	201	emmc_gpio22: emmc_gpio22 {
	202	brcm,pins = <22 23 24 25 26 27>;
	203	brcm,function = <BCM2835_FSEL_ALT3>;
	204	};
	205	emmc_gpio34: emmc_gpio34 {
	206	brcm,pins = <34 35 36 37 38 39>;
	207	brcm,function = <BCM2835_FSEL_ALT3>;
	208	brcm,pull = <BCM2835_PUD_OFF
	209	BCM2835_PUD_UP
	210	BCM2835_PUD_UP
	211	BCM2835_PUD_UP
	212	BCM2835_PUD_UP
	213	BCM2835_PUD_UP>;
	214	};
	215	emmc_gpio48: emmc_gpio48 {
	216	brcm,pins = <48 49 50 51 52 53>;
	217	brcm,function = <BCM2835_FSEL_ALT3>;
	218	};
	219
	220	gpclk0_gpio4: gpclk0_gpio4 {
	221	brcm,pins = <4>;
	222	brcm,function = <BCM2835_FSEL_ALT0>;
	223	};
	224	gpclk1_gpio5: gpclk1_gpio5 {
	225	brcm,pins = <5>;
	226	brcm,function = <BCM2835_FSEL_ALT0>;
	227	};
	228	gpclk1_gpio42: gpclk1_gpio42 {
	229	brcm,pins = <42>;
	230	brcm,function = <BCM2835_FSEL_ALT0>;
	231	};
	232	gpclk1_gpio44: gpclk1_gpio44 {
	233	brcm,pins = <44>;
	234	brcm,function = <BCM2835_FSEL_ALT0>;
	235	};
	236	gpclk2_gpio6: gpclk2_gpio6 {
	237	brcm,pins = <6>;
	238	brcm,function = <BCM2835_FSEL_ALT0>;
	239	};
	240	gpclk2_gpio43: gpclk2_gpio43 {
	241	brcm,pins = <43>;
	242	brcm,function = <BCM2835_FSEL_ALT0>;
a166ae40	243	brcm,pull = <BCM2835_PUD_OFF>;
21ff8439 EA	244	};
	245
	246	i2c0_gpio0: i2c0_gpio0 {
	247	brcm,pins = <0 1>;
	248	brcm,function = <BCM2835_FSEL_ALT0>;
	249	};
843b2287 BS	250	i2c0_gpio28: i2c0_gpio28 {
843b2287 BS	251	brcm,pins = <28 29>;
21ff8439 EA	252	brcm,function = <BCM2835_FSEL_ALT0>;
	253	};
	254	i2c0_gpio44: i2c0_gpio44 {
	255	brcm,pins = <44 45>;
	256	brcm,function = <BCM2835_FSEL_ALT1>;
	257	};
	258	i2c1_gpio2: i2c1_gpio2 {
	259	brcm,pins = <2 3>;
	260	brcm,function = <BCM2835_FSEL_ALT0>;
	261	};
	262	i2c1_gpio44: i2c1_gpio44 {
	263	brcm,pins = <44 45>;
	264	brcm,function = <BCM2835_FSEL_ALT2>;
	265	};
	266	i2c_slave_gpio18: i2c_slave_gpio18 {
	267	brcm,pins = <18 19 20 21>;
	268	brcm,function = <BCM2835_FSEL_ALT3>;
	269	};
	270
	271	jtag_gpio4: jtag_gpio4 {
	272	brcm,pins = <4 5 6 12 13>;
1a012cb2	273	brcm,function = <BCM2835_FSEL_ALT5>;
21ff8439 EA	274	};
	275	jtag_gpio22: jtag_gpio22 {
	276	brcm,pins = <22 23 24 25 26 27>;
	277	brcm,function = <BCM2835_FSEL_ALT4>;
	278	};
	279
	280	pcm_gpio18: pcm_gpio18 {
	281	brcm,pins = <18 19 20 21>;
	282	brcm,function = <BCM2835_FSEL_ALT0>;
	283	};
	284	pcm_gpio28: pcm_gpio28 {
	285	brcm,pins = <28 29 30 31>;
	286	brcm,function = <BCM2835_FSEL_ALT2>;
	287	};
	288
	289	pwm0_gpio12: pwm0_gpio12 {
	290	brcm,pins = <12>;
	291	brcm,function = <BCM2835_FSEL_ALT0>;
	292	};
	293	pwm0_gpio18: pwm0_gpio18 {
	294	brcm,pins = <18>;
	295	brcm,function = <BCM2835_FSEL_ALT5>;
	296	};
	297	pwm0_gpio40: pwm0_gpio40 {
	298	brcm,pins = <40>;
	299	brcm,function = <BCM2835_FSEL_ALT0>;
	300	};
	301	pwm1_gpio13: pwm1_gpio13 {
	302	brcm,pins = <13>;
	303	brcm,function = <BCM2835_FSEL_ALT0>;
	304	};
	305	pwm1_gpio19: pwm1_gpio19 {
	306	brcm,pins = <19>;
	307	brcm,function = <BCM2835_FSEL_ALT5>;
	308	};
	309	pwm1_gpio41: pwm1_gpio41 {
	310	brcm,pins = <41>;
	311	brcm,function = <BCM2835_FSEL_ALT0>;
	312	};
	313	pwm1_gpio45: pwm1_gpio45 {
	314	brcm,pins = <45>;
	315	brcm,function = <BCM2835_FSEL_ALT0>;
	316	};
	317
	318	sdhost_gpio48: sdhost_gpio48 {
	319	brcm,pins = <48 49 50 51 52 53>;
	320	brcm,function = <BCM2835_FSEL_ALT0>;
	321	};
	322
	323	spi0_gpio7: spi0_gpio7 {
	324	brcm,pins = <7 8 9 10 11>;
	325	brcm,function = <BCM2835_FSEL_ALT0>;
	326	};
	327	spi0_gpio35: spi0_gpio35 {
	328	brcm,pins = <35 36 37 38 39>;
	329	brcm,function = <BCM2835_FSEL_ALT0>;
	330	};
	331	spi1_gpio16: spi1_gpio16 {
	332	brcm,pins = <16 17 18 19 20 21>;
	333	brcm,function = <BCM2835_FSEL_ALT4>;
	334	};
	335	spi2_gpio40: spi2_gpio40 {
	336	brcm,pins = <40 41 42 43 44 45>;
	337	brcm,function = <BCM2835_FSEL_ALT4>;
338	};
339
340	uart0_gpio14: uart0_gpio14 {
341	brcm,pins = <14 15>;
342	brcm,function = <BCM2835_FSEL_ALT0>;
343	};
344	/* Separate from the uart0_gpio14 group
345	* because it conflicts with spi1_gpio16, and
346	* people often run uart0 on the two pins
ec8542cb	347	* without flow control.
21ff8439 EA	348	*/
	349	uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
	350	brcm,pins = <16 17>;
	351	brcm,function = <BCM2835_FSEL_ALT3>;
	352	};
ec8542cb	353	uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
21ff8439 EA	354	brcm,pins = <30 31>;
21ff8439 EA	355	brcm,function = <BCM2835_FSEL_ALT3>;
a166ae40	356	brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
21ff8439	357	};
ec8542cb	358	uart0_gpio32: uart0_gpio32 {
21ff8439 EA	359	brcm,pins = <32 33>;
21ff8439 EA	360	brcm,function = <BCM2835_FSEL_ALT3>;
a166ae40	361	brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
21ff8439	362	};
e1be65a5 BS	363	uart0_gpio36: uart0_gpio36 {
	364	brcm,pins = <36 37>;
	365	brcm,function = <BCM2835_FSEL_ALT2>;
	366	};
	367	uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
	368	brcm,pins = <38 39>;
	369	brcm,function = <BCM2835_FSEL_ALT2>;
	370	};
21ff8439 EA	371
	372	uart1_gpio14: uart1_gpio14 {
	373	brcm,pins = <14 15>;
	374	brcm,function = <BCM2835_FSEL_ALT5>;
	375	};
	376	uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
	377	brcm,pins = <16 17>;
	378	brcm,function = <BCM2835_FSEL_ALT5>;
	379	};
	380	uart1_gpio32: uart1_gpio32 {
	381	brcm,pins = <32 33>;
	382	brcm,function = <BCM2835_FSEL_ALT5>;
	383	};
	384	uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
	385	brcm,pins = <30 31>;
	386	brcm,function = <BCM2835_FSEL_ALT5>;
	387	};
21ff8439 EA	388	uart1_gpio40: uart1_gpio40 {
	389	brcm,pins = <40 41>;
	390	brcm,function = <BCM2835_FSEL_ALT5>;
	391	};
	392	uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
	393	brcm,pins = <42 43>;
	394	brcm,function = <BCM2835_FSEL_ALT5>;
	395	};
548c3a39 EA	396	};
548c3a39 EA	397
68e2ef17	398	uart0: serial@7e201000 {
548c3a39 EA	399	compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
	400	reg = <0x7e201000 0x1000>;
	401	interrupts = <2 25>;
	402	clocks = <&clocks BCM2835_CLOCK_UART>,
	403	<&clocks BCM2835_CLOCK_VPU>;
	404	clock-names = "uartclk", "apb_pclk";
	405	arm,primecell-periphid = <0x00241011>;
	406	};
	407
7f31a955 GH	408	sdhost: mmc@7e202000 {
	409	compatible = "brcm,bcm2835-sdhost";
	410	reg = <0x7e202000 0x100>;
	411	interrupts = <2 24>;
	412	clocks = <&clocks BCM2835_CLOCK_VPU>;
	413	dmas = <&dma 13>;
	414	dma-names = "rx-tx";
	415	status = "disabled";
	416	};
	417
548c3a39 EA	418	i2s: i2s@7e203000 {
548c3a39 EA	419	compatible = "brcm,bcm2835-i2s";
79c81fac SW	420	reg = <0x7e203000 0x24>;
79c81fac SW	421	clocks = <&clocks BCM2835_CLOCK_PCM>;
548c3a39 EA	422
	423	dmas = <&dma 2>,
	424	<&dma 3>;
	425	dma-names = "tx", "rx";
	426	status = "disabled";
	427	};
	428
	429	spi: spi@7e204000 {
	430	compatible = "brcm,bcm2835-spi";
	431	reg = <0x7e204000 0x1000>;
	432	interrupts = <2 22>;
	433	clocks = <&clocks BCM2835_CLOCK_VPU>;
	434	#address-cells = <1>;
	435	#size-cells = <0>;
	436	status = "disabled";
	437	};
	438
	439	i2c0: i2c@7e205000 {
	440	compatible = "brcm,bcm2835-i2c";
	441	reg = <0x7e205000 0x1000>;
	442	interrupts = <2 21>;
	443	clocks = <&clocks BCM2835_CLOCK_VPU>;
	444	#address-cells = <1>;
	445	#size-cells = <0>;
	446	status = "disabled";
	447	};
	448
49ac67e0 EA	449	pixelvalve@7e206000 {
	450	compatible = "brcm,bcm2835-pixelvalve0";
	451	reg = <0x7e206000 0x100>;
	452	interrupts = <2 13>; /* pwa0 */
	453	};
	454
	455	pixelvalve@7e207000 {
	456	compatible = "brcm,bcm2835-pixelvalve1";
	457	reg = <0x7e207000 0x100>;
	458	interrupts = <2 14>; /* pwa1 */
	459	};
	460
ae67cfc4 EA	461	dpi: dpi@7e208000 {
	462	compatible = "brcm,bcm2835-dpi";
	463	reg = <0x7e208000 0x8c>;
	464	clocks = <&clocks BCM2835_CLOCK_VPU>,
	465	<&clocks BCM2835_CLOCK_DPI>;
	466	clock-names = "core", "pixel";
	467	#address-cells = <1>;
	468	#size-cells = <0>;
	469	status = "disabled";
	470	};
	471
4aba4cf8 EA	472	dsi0: dsi@7e209000 {
	473	compatible = "brcm,bcm2835-dsi0";
	474	reg = <0x7e209000 0x78>;
	475	interrupts = <2 4>;
	476	#address-cells = <1>;
	477	#size-cells = <0>;
	478	#clock-cells = <1>;
	479
	480	clocks = <&clocks BCM2835_PLLA_DSI0>,
	481	<&clocks BCM2835_CLOCK_DSI0E>,
	482	<&clocks BCM2835_CLOCK_DSI0P>;
	483	clock-names = "phy", "escape", "pixel";
	484
	485	clock-output-names = "dsi0_byte",
	486	"dsi0_ddr2",
	487	"dsi0_ddr";
	488
	489	};
	490
43bac413 MS	491	thermal: thermal@7e212000 {
	492	compatible = "brcm,bcm2835-thermal";
	493	reg = <0x7e212000 0x8>;
	494	clocks = <&clocks BCM2835_CLOCK_TSENS>;
0fe4d218	495	#thermal-sensor-cells = <0>;
43bac413 MS	496	status = "disabled";
	497	};
	498
77ee2e1b	499	aux: aux@7e215000 {
ddc5c39a EA	500	compatible = "brcm,bcm2835-aux";
	501	#clock-cells = <1>;
	502	reg = <0x7e215000 0x8>;
	503	clocks = <&clocks BCM2835_CLOCK_VPU>;
	504	};
	505
1305141d MS	506	uart1: serial@7e215040 {
	507	compatible = "brcm,bcm2835-aux-uart";
	508	reg = <0x7e215040 0x40>;
	509	interrupts = <1 29>;
	510	clocks = <&aux BCM2835_AUX_CLOCK_UART>;
	511	status = "disabled";
	512	};
	513
f974d685 MS	514	spi1: spi@7e215080 {
	515	compatible = "brcm,bcm2835-aux-spi";
	516	reg = <0x7e215080 0x40>;
	517	interrupts = <1 29>;
	518	clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
	519	#address-cells = <1>;
	520	#size-cells = <0>;
	521	status = "disabled";
	522	};
	523
	524	spi2: spi@7e2150c0 {
	525	compatible = "brcm,bcm2835-aux-spi";
	526	reg = <0x7e2150c0 0x40>;
	527	interrupts = <1 29>;
	528	clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
	529	#address-cells = <1>;
	530	#size-cells = <0>;
	531	status = "disabled";
	532	};
	533
40ad4499 RP	534	pwm: pwm@7e20c000 {
	535	compatible = "brcm,bcm2835-pwm";
	536	reg = <0x7e20c000 0x28>;
	537	clocks = <&clocks BCM2835_CLOCK_PWM>;
	538	assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
	539	assigned-clock-rates = <10000000>;
	540	#pwm-cells = <2>;
	541	status = "disabled";
	542	};
	543
548c3a39 EA	544	sdhci: sdhci@7e300000 {
	545	compatible = "brcm,bcm2835-sdhci";
	546	reg = <0x7e300000 0x100>;
	547	interrupts = <2 30>;
	548	clocks = <&clocks BCM2835_CLOCK_EMMC>;
	549	status = "disabled";
	550	};
	551
49ac67e0 EA	552	hvs@7e400000 {
	553	compatible = "brcm,bcm2835-hvs";
	554	reg = <0x7e400000 0x6000>;
	555	interrupts = <2 1>;
	556	};
	557
4aba4cf8 EA	558	dsi1: dsi@7e700000 {
	559	compatible = "brcm,bcm2835-dsi1";
	560	reg = <0x7e700000 0x8c>;
	561	interrupts = <2 12>;
	562	#address-cells = <1>;
	563	#size-cells = <0>;
	564	#clock-cells = <1>;
	565
	566	clocks = <&clocks BCM2835_PLLD_DSI1>,
	567	<&clocks BCM2835_CLOCK_DSI1E>,
	568	<&clocks BCM2835_CLOCK_DSI1P>;
	569	clock-names = "phy", "escape", "pixel";
	570
	571	clock-output-names = "dsi1_byte",
	572	"dsi1_ddr2",
	573	"dsi1_ddr";
	574
	575	status = "disabled";
	576	};
	577
548c3a39 EA	578	i2c1: i2c@7e804000 {
	579	compatible = "brcm,bcm2835-i2c";
	580	reg = <0x7e804000 0x1000>;
	581	interrupts = <2 21>;
	582	clocks = <&clocks BCM2835_CLOCK_VPU>;
	583	#address-cells = <1>;
	584	#size-cells = <0>;
	585	status = "disabled";
	586	};
	587
	588	i2c2: i2c@7e805000 {
	589	compatible = "brcm,bcm2835-i2c";
	590	reg = <0x7e805000 0x1000>;
	591	interrupts = <2 21>;
	592	clocks = <&clocks BCM2835_CLOCK_VPU>;
	593	#address-cells = <1>;
	594	#size-cells = <0>;
	595	status = "disabled";
	596	};
	597
b899c452 BB	598	vec: vec@7e806000 {
	599	compatible = "brcm,bcm2835-vec";
	600	reg = <0x7e806000 0x1000>;
	601	clocks = <&clocks BCM2835_CLOCK_VEC>;
	602	interrupts = <2 27>;
	603	status = "disabled";
	604	};
	605
49ac67e0 EA	606	pixelvalve@7e807000 {
	607	compatible = "brcm,bcm2835-pixelvalve2";
	608	reg = <0x7e807000 0x100>;
	609	interrupts = <2 10>; /* pixelvalve */
	610	};
	611
	612	hdmi: hdmi@7e902000 {
	613	compatible = "brcm,bcm2835-hdmi";
	614	reg = <0x7e902000 0x600>,
	615	<0x7e808000 0x100>;
	616	interrupts = <2 8>, <2 9>;
	617	ddc = <&i2c2>;
	618	clocks = <&clocks BCM2835_PLLH_PIX>,
	619	<&clocks BCM2835_CLOCK_HSM>;
	620	clock-names = "pixel", "hdmi";
d46d2c63 BB	621	dmas = <&dma 17>;
d46d2c63 BB	622	dma-names = "audio-rx";
49ac67e0 EA	623	status = "disabled";
	624	};
	625
5ec6f2cd	626	usb: usb@7e980000 {
548c3a39 EA	627	compatible = "brcm,bcm2835-usb";
	628	reg = <0x7e980000 0x10000>;
	629	interrupts = <1 9>;
6a937927 LR	630	#address-cells = <1>;
6a937927 LR	631	#size-cells = <0>;
33145fac SW	632	clocks = <&clk_usb>;
33145fac SW	633	clock-names = "otg";
860a5d0b SW	634	phys = <&usbphy>;
860a5d0b SW	635	phy-names = "usb2-phy";
548c3a39	636	};
49ac67e0 EA	637
	638	v3d: v3d@7ec00000 {
	639	compatible = "brcm,bcm2835-v3d";
	640	reg = <0x7ec00000 0x1000>;
	641	interrupts = <1 10>;
e1dc2b2e	642	power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
49ac67e0 EA	643	};
	644
	645	vc4: gpu {
	646	compatible = "brcm,bcm2835-vc4";
	647	};
548c3a39 EA	648	};
	649
	650	clocks {
	651	compatible = "simple-bus";
	652	#address-cells = <1>;
	653	#size-cells = <0>;
	654
	655	/* The oscillator is the root of the clock tree. */
	656	clk_osc: clock@3 {
	657	compatible = "fixed-clock";
	658	reg = <3>;
	659	#clock-cells = <0>;
	660	clock-output-names = "osc";
	661	clock-frequency = <19200000>;
	662	};
	663
33145fac SW	664	clk_usb: clock@4 {
	665	compatible = "fixed-clock";
	666	reg = <4>;
	667	#clock-cells = <0>;
	668	clock-output-names = "otg";
	669	clock-frequency = <480000000>;
	670	};
548c3a39	671	};
860a5d0b SW	672
	673	usbphy: phy {
	674	compatible = "usb-nop-xceiv";
014d6da6	675	#phy-cells = <0>;
860a5d0b	676	};
548c3a39	677	};