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548c3a39 EA |
1 | #include <dt-bindings/pinctrl/bcm2835.h> |
2 | #include <dt-bindings/clock/bcm2835.h> | |
f974d685 | 3 | #include <dt-bindings/clock/bcm2835-aux.h> |
49ac67e0 | 4 | #include <dt-bindings/gpio/gpio.h> |
548c3a39 EA |
5 | |
6 | /* This include file covers the common peripherals and configuration between | |
7 | * bcm2835 and bcm2836 implementations, leaving the CPU configuration to | |
8 | * bcm2835.dtsi and bcm2836.dtsi. | |
9 | */ | |
10 | ||
11 | / { | |
12 | compatible = "brcm,bcm2835"; | |
13 | model = "BCM2835"; | |
14 | interrupt-parent = <&intc>; | |
6b7b554d IC |
15 | #address-cells = <1>; |
16 | #size-cells = <1>; | |
548c3a39 EA |
17 | |
18 | chosen { | |
19 | bootargs = "earlyprintk console=ttyAMA0"; | |
20 | }; | |
21 | ||
22 | soc { | |
23 | compatible = "simple-bus"; | |
24 | #address-cells = <1>; | |
25 | #size-cells = <1>; | |
26 | ||
27 | timer@7e003000 { | |
28 | compatible = "brcm,bcm2835-system-timer"; | |
29 | reg = <0x7e003000 0x1000>; | |
30 | interrupts = <1 0>, <1 1>, <1 2>, <1 3>; | |
31 | /* This could be a reference to BCM2835_CLOCK_TIMER, | |
32 | * but we don't have the driver using the common clock | |
33 | * support yet. | |
34 | */ | |
35 | clock-frequency = <1000000>; | |
36 | }; | |
37 | ||
38 | dma: dma@7e007000 { | |
39 | compatible = "brcm,bcm2835-dma"; | |
40 | reg = <0x7e007000 0xf00>; | |
41 | interrupts = <1 16>, | |
42 | <1 17>, | |
43 | <1 18>, | |
44 | <1 19>, | |
45 | <1 20>, | |
46 | <1 21>, | |
47 | <1 22>, | |
48 | <1 23>, | |
49 | <1 24>, | |
50 | <1 25>, | |
51 | <1 26>, | |
9bc0fa53 | 52 | /* dma channel 11-14 share one irq */ |
548c3a39 | 53 | <1 27>, |
9bc0fa53 MS |
54 | <1 27>, |
55 | <1 27>, | |
56 | <1 27>, | |
57 | /* unused shared irq for all channels */ | |
548c3a39 | 58 | <1 28>; |
9bc0fa53 MS |
59 | interrupt-names = "dma0", |
60 | "dma1", | |
61 | "dma2", | |
62 | "dma3", | |
63 | "dma4", | |
64 | "dma5", | |
65 | "dma6", | |
66 | "dma7", | |
67 | "dma8", | |
68 | "dma9", | |
69 | "dma10", | |
70 | "dma11", | |
71 | "dma12", | |
72 | "dma13", | |
73 | "dma14", | |
74 | "dma-shared-all"; | |
548c3a39 EA |
75 | #dma-cells = <1>; |
76 | brcm,dma-channel-mask = <0x7f35>; | |
77 | }; | |
78 | ||
79 | intc: interrupt-controller@7e00b200 { | |
80 | compatible = "brcm,bcm2835-armctrl-ic"; | |
81 | reg = <0x7e00b200 0x200>; | |
82 | interrupt-controller; | |
83 | #interrupt-cells = <2>; | |
84 | }; | |
85 | ||
86 | watchdog@7e100000 { | |
87 | compatible = "brcm,bcm2835-pm-wdt"; | |
88 | reg = <0x7e100000 0x28>; | |
89 | }; | |
90 | ||
91 | clocks: cprman@7e101000 { | |
92 | compatible = "brcm,bcm2835-cprman"; | |
93 | #clock-cells = <1>; | |
94 | reg = <0x7e101000 0x2000>; | |
95 | ||
99b7dabf EA |
96 | /* CPRMAN derives almost everything from the |
97 | * platform's oscillator. However, the DSI | |
98 | * pixel clocks come from the DSI analog PHY. | |
548c3a39 | 99 | */ |
99b7dabf EA |
100 | clocks = <&clk_osc>, |
101 | <&dsi0 0>, <&dsi0 1>, <&dsi0 2>, | |
102 | <&dsi1 0>, <&dsi1 1>, <&dsi1 2>; | |
548c3a39 EA |
103 | }; |
104 | ||
105 | rng@7e104000 { | |
106 | compatible = "brcm,bcm2835-rng"; | |
107 | reg = <0x7e104000 0x10>; | |
108 | }; | |
109 | ||
7d891a68 | 110 | mailbox: mailbox@7e00b880 { |
548c3a39 EA |
111 | compatible = "brcm,bcm2835-mbox"; |
112 | reg = <0x7e00b880 0x40>; | |
113 | interrupts = <0 1>; | |
114 | #mbox-cells = <0>; | |
115 | }; | |
116 | ||
117 | gpio: gpio@7e200000 { | |
118 | compatible = "brcm,bcm2835-gpio"; | |
119 | reg = <0x7e200000 0xb4>; | |
120 | /* | |
121 | * The GPIO IP block is designed for 3 banks of GPIOs. | |
122 | * Each bank has a GPIO interrupt for itself. | |
123 | * There is an overall "any bank" interrupt. | |
124 | * In order, these are GIC interrupts 17, 18, 19, 20. | |
125 | * Since the BCM2835 only has 2 banks, the 2nd bank | |
126 | * interrupt output appears to be mirrored onto the | |
127 | * 3rd bank's interrupt signal. | |
128 | * So, a bank0 interrupt shows up on 17, 20, and | |
129 | * a bank1 interrupt shows up on 18, 19, 20! | |
130 | */ | |
131 | interrupts = <2 17>, <2 18>, <2 19>, <2 20>; | |
132 | ||
133 | gpio-controller; | |
134 | #gpio-cells = <2>; | |
135 | ||
136 | interrupt-controller; | |
137 | #interrupt-cells = <2>; | |
21ff8439 EA |
138 | |
139 | /* Defines pin muxing groups according to | |
140 | * BCM2835-ARM-Peripherals.pdf page 102. | |
141 | * | |
142 | * While each pin can have its mux selected | |
143 | * for various functions individually, some | |
144 | * groups only make sense to switch to a | |
145 | * particular function together. | |
146 | */ | |
147 | dpi_gpio0: dpi_gpio0 { | |
148 | brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 | |
149 | 12 13 14 15 16 17 18 19 | |
150 | 20 21 22 23 24 25 26 27>; | |
151 | brcm,function = <BCM2835_FSEL_ALT2>; | |
152 | }; | |
153 | emmc_gpio22: emmc_gpio22 { | |
154 | brcm,pins = <22 23 24 25 26 27>; | |
155 | brcm,function = <BCM2835_FSEL_ALT3>; | |
156 | }; | |
157 | emmc_gpio34: emmc_gpio34 { | |
158 | brcm,pins = <34 35 36 37 38 39>; | |
159 | brcm,function = <BCM2835_FSEL_ALT3>; | |
160 | brcm,pull = <BCM2835_PUD_OFF | |
161 | BCM2835_PUD_UP | |
162 | BCM2835_PUD_UP | |
163 | BCM2835_PUD_UP | |
164 | BCM2835_PUD_UP | |
165 | BCM2835_PUD_UP>; | |
166 | }; | |
167 | emmc_gpio48: emmc_gpio48 { | |
168 | brcm,pins = <48 49 50 51 52 53>; | |
169 | brcm,function = <BCM2835_FSEL_ALT3>; | |
170 | }; | |
171 | ||
172 | gpclk0_gpio4: gpclk0_gpio4 { | |
173 | brcm,pins = <4>; | |
174 | brcm,function = <BCM2835_FSEL_ALT0>; | |
175 | }; | |
176 | gpclk1_gpio5: gpclk1_gpio5 { | |
177 | brcm,pins = <5>; | |
178 | brcm,function = <BCM2835_FSEL_ALT0>; | |
179 | }; | |
180 | gpclk1_gpio42: gpclk1_gpio42 { | |
181 | brcm,pins = <42>; | |
182 | brcm,function = <BCM2835_FSEL_ALT0>; | |
183 | }; | |
184 | gpclk1_gpio44: gpclk1_gpio44 { | |
185 | brcm,pins = <44>; | |
186 | brcm,function = <BCM2835_FSEL_ALT0>; | |
187 | }; | |
188 | gpclk2_gpio6: gpclk2_gpio6 { | |
189 | brcm,pins = <6>; | |
190 | brcm,function = <BCM2835_FSEL_ALT0>; | |
191 | }; | |
192 | gpclk2_gpio43: gpclk2_gpio43 { | |
193 | brcm,pins = <43>; | |
194 | brcm,function = <BCM2835_FSEL_ALT0>; | |
195 | }; | |
196 | ||
197 | i2c0_gpio0: i2c0_gpio0 { | |
198 | brcm,pins = <0 1>; | |
199 | brcm,function = <BCM2835_FSEL_ALT0>; | |
200 | }; | |
201 | i2c0_gpio32: i2c0_gpio32 { | |
202 | brcm,pins = <32 34>; | |
203 | brcm,function = <BCM2835_FSEL_ALT0>; | |
204 | }; | |
205 | i2c0_gpio44: i2c0_gpio44 { | |
206 | brcm,pins = <44 45>; | |
207 | brcm,function = <BCM2835_FSEL_ALT1>; | |
208 | }; | |
209 | i2c1_gpio2: i2c1_gpio2 { | |
210 | brcm,pins = <2 3>; | |
211 | brcm,function = <BCM2835_FSEL_ALT0>; | |
212 | }; | |
213 | i2c1_gpio44: i2c1_gpio44 { | |
214 | brcm,pins = <44 45>; | |
215 | brcm,function = <BCM2835_FSEL_ALT2>; | |
216 | }; | |
217 | i2c_slave_gpio18: i2c_slave_gpio18 { | |
218 | brcm,pins = <18 19 20 21>; | |
219 | brcm,function = <BCM2835_FSEL_ALT3>; | |
220 | }; | |
221 | ||
222 | jtag_gpio4: jtag_gpio4 { | |
223 | brcm,pins = <4 5 6 12 13>; | |
224 | brcm,function = <BCM2835_FSEL_ALT4>; | |
225 | }; | |
226 | jtag_gpio22: jtag_gpio22 { | |
227 | brcm,pins = <22 23 24 25 26 27>; | |
228 | brcm,function = <BCM2835_FSEL_ALT4>; | |
229 | }; | |
230 | ||
231 | pcm_gpio18: pcm_gpio18 { | |
232 | brcm,pins = <18 19 20 21>; | |
233 | brcm,function = <BCM2835_FSEL_ALT0>; | |
234 | }; | |
235 | pcm_gpio28: pcm_gpio28 { | |
236 | brcm,pins = <28 29 30 31>; | |
237 | brcm,function = <BCM2835_FSEL_ALT2>; | |
238 | }; | |
239 | ||
240 | pwm0_gpio12: pwm0_gpio12 { | |
241 | brcm,pins = <12>; | |
242 | brcm,function = <BCM2835_FSEL_ALT0>; | |
243 | }; | |
244 | pwm0_gpio18: pwm0_gpio18 { | |
245 | brcm,pins = <18>; | |
246 | brcm,function = <BCM2835_FSEL_ALT5>; | |
247 | }; | |
248 | pwm0_gpio40: pwm0_gpio40 { | |
249 | brcm,pins = <40>; | |
250 | brcm,function = <BCM2835_FSEL_ALT0>; | |
251 | }; | |
252 | pwm1_gpio13: pwm1_gpio13 { | |
253 | brcm,pins = <13>; | |
254 | brcm,function = <BCM2835_FSEL_ALT0>; | |
255 | }; | |
256 | pwm1_gpio19: pwm1_gpio19 { | |
257 | brcm,pins = <19>; | |
258 | brcm,function = <BCM2835_FSEL_ALT5>; | |
259 | }; | |
260 | pwm1_gpio41: pwm1_gpio41 { | |
261 | brcm,pins = <41>; | |
262 | brcm,function = <BCM2835_FSEL_ALT0>; | |
263 | }; | |
264 | pwm1_gpio45: pwm1_gpio45 { | |
265 | brcm,pins = <45>; | |
266 | brcm,function = <BCM2835_FSEL_ALT0>; | |
267 | }; | |
268 | ||
269 | sdhost_gpio48: sdhost_gpio48 { | |
270 | brcm,pins = <48 49 50 51 52 53>; | |
271 | brcm,function = <BCM2835_FSEL_ALT0>; | |
272 | }; | |
273 | ||
274 | spi0_gpio7: spi0_gpio7 { | |
275 | brcm,pins = <7 8 9 10 11>; | |
276 | brcm,function = <BCM2835_FSEL_ALT0>; | |
277 | }; | |
278 | spi0_gpio35: spi0_gpio35 { | |
279 | brcm,pins = <35 36 37 38 39>; | |
280 | brcm,function = <BCM2835_FSEL_ALT0>; | |
281 | }; | |
282 | spi1_gpio16: spi1_gpio16 { | |
283 | brcm,pins = <16 17 18 19 20 21>; | |
284 | brcm,function = <BCM2835_FSEL_ALT4>; | |
285 | }; | |
286 | spi2_gpio40: spi2_gpio40 { | |
287 | brcm,pins = <40 41 42 43 44 45>; | |
288 | brcm,function = <BCM2835_FSEL_ALT4>; | |
289 | }; | |
290 | ||
291 | uart0_gpio14: uart0_gpio14 { | |
292 | brcm,pins = <14 15>; | |
293 | brcm,function = <BCM2835_FSEL_ALT0>; | |
294 | }; | |
295 | /* Separate from the uart0_gpio14 group | |
296 | * because it conflicts with spi1_gpio16, and | |
297 | * people often run uart0 on the two pins | |
298 | * without flow contrl. | |
299 | */ | |
300 | uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 { | |
301 | brcm,pins = <16 17>; | |
302 | brcm,function = <BCM2835_FSEL_ALT3>; | |
303 | }; | |
304 | uart0_gpio30: uart0_gpio30 { | |
305 | brcm,pins = <30 31>; | |
306 | brcm,function = <BCM2835_FSEL_ALT3>; | |
307 | }; | |
308 | uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 { | |
309 | brcm,pins = <32 33>; | |
310 | brcm,function = <BCM2835_FSEL_ALT3>; | |
311 | }; | |
312 | ||
313 | uart1_gpio14: uart1_gpio14 { | |
314 | brcm,pins = <14 15>; | |
315 | brcm,function = <BCM2835_FSEL_ALT5>; | |
316 | }; | |
317 | uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 { | |
318 | brcm,pins = <16 17>; | |
319 | brcm,function = <BCM2835_FSEL_ALT5>; | |
320 | }; | |
321 | uart1_gpio32: uart1_gpio32 { | |
322 | brcm,pins = <32 33>; | |
323 | brcm,function = <BCM2835_FSEL_ALT5>; | |
324 | }; | |
325 | uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 { | |
326 | brcm,pins = <30 31>; | |
327 | brcm,function = <BCM2835_FSEL_ALT5>; | |
328 | }; | |
329 | uart1_gpio36: uart1_gpio36 { | |
330 | brcm,pins = <36 37 38 39>; | |
331 | brcm,function = <BCM2835_FSEL_ALT2>; | |
332 | }; | |
333 | uart1_gpio40: uart1_gpio40 { | |
334 | brcm,pins = <40 41>; | |
335 | brcm,function = <BCM2835_FSEL_ALT5>; | |
336 | }; | |
337 | uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 { | |
338 | brcm,pins = <42 43>; | |
339 | brcm,function = <BCM2835_FSEL_ALT5>; | |
340 | }; | |
548c3a39 EA |
341 | }; |
342 | ||
68e2ef17 | 343 | uart0: serial@7e201000 { |
548c3a39 EA |
344 | compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; |
345 | reg = <0x7e201000 0x1000>; | |
346 | interrupts = <2 25>; | |
347 | clocks = <&clocks BCM2835_CLOCK_UART>, | |
348 | <&clocks BCM2835_CLOCK_VPU>; | |
349 | clock-names = "uartclk", "apb_pclk"; | |
350 | arm,primecell-periphid = <0x00241011>; | |
351 | }; | |
352 | ||
353 | i2s: i2s@7e203000 { | |
354 | compatible = "brcm,bcm2835-i2s"; | |
355 | reg = <0x7e203000 0x20>, | |
356 | <0x7e101098 0x02>; | |
357 | ||
358 | dmas = <&dma 2>, | |
359 | <&dma 3>; | |
360 | dma-names = "tx", "rx"; | |
361 | status = "disabled"; | |
362 | }; | |
363 | ||
364 | spi: spi@7e204000 { | |
365 | compatible = "brcm,bcm2835-spi"; | |
366 | reg = <0x7e204000 0x1000>; | |
367 | interrupts = <2 22>; | |
368 | clocks = <&clocks BCM2835_CLOCK_VPU>; | |
369 | #address-cells = <1>; | |
370 | #size-cells = <0>; | |
371 | status = "disabled"; | |
bc94cc30 | 372 | cs-gpios = <&gpio 8 1>, <&gpio 7 1>; |
548c3a39 EA |
373 | }; |
374 | ||
375 | i2c0: i2c@7e205000 { | |
376 | compatible = "brcm,bcm2835-i2c"; | |
377 | reg = <0x7e205000 0x1000>; | |
378 | interrupts = <2 21>; | |
379 | clocks = <&clocks BCM2835_CLOCK_VPU>; | |
380 | #address-cells = <1>; | |
381 | #size-cells = <0>; | |
382 | status = "disabled"; | |
383 | }; | |
384 | ||
49ac67e0 EA |
385 | pixelvalve@7e206000 { |
386 | compatible = "brcm,bcm2835-pixelvalve0"; | |
387 | reg = <0x7e206000 0x100>; | |
388 | interrupts = <2 13>; /* pwa0 */ | |
389 | }; | |
390 | ||
391 | pixelvalve@7e207000 { | |
392 | compatible = "brcm,bcm2835-pixelvalve1"; | |
393 | reg = <0x7e207000 0x100>; | |
394 | interrupts = <2 14>; /* pwa1 */ | |
395 | }; | |
396 | ||
99b7dabf EA |
397 | dsi0: dsi@7e209000 { |
398 | compatible = "brcm,bcm2835-dsi0"; | |
399 | reg = <0x7e209000 0x78>; | |
400 | interrupts = <2 4>; | |
401 | #address-cells = <1>; | |
402 | #size-cells = <0>; | |
403 | #clock-cells = <1>; | |
404 | ||
405 | clocks = <&clocks BCM2835_PLLA_DSI0>, | |
406 | <&clocks BCM2835_CLOCK_DSI0E>, | |
407 | <&clocks BCM2835_CLOCK_DSI0P>; | |
408 | clock-names = "phy", "escape", "pixel"; | |
409 | ||
410 | clock-output-names = "dsi0_byte", | |
411 | "dsi0_ddr2", | |
412 | "dsi0_ddr"; | |
413 | ||
414 | status = "disabled"; | |
415 | }; | |
416 | ||
43bac413 MS |
417 | thermal: thermal@7e212000 { |
418 | compatible = "brcm,bcm2835-thermal"; | |
419 | reg = <0x7e212000 0x8>; | |
420 | clocks = <&clocks BCM2835_CLOCK_TSENS>; | |
421 | status = "disabled"; | |
422 | }; | |
423 | ||
ddc5c39a EA |
424 | aux: aux@0x7e215000 { |
425 | compatible = "brcm,bcm2835-aux"; | |
426 | #clock-cells = <1>; | |
427 | reg = <0x7e215000 0x8>; | |
428 | clocks = <&clocks BCM2835_CLOCK_VPU>; | |
429 | }; | |
430 | ||
1305141d MS |
431 | uart1: serial@7e215040 { |
432 | compatible = "brcm,bcm2835-aux-uart"; | |
433 | reg = <0x7e215040 0x40>; | |
434 | interrupts = <1 29>; | |
435 | clocks = <&aux BCM2835_AUX_CLOCK_UART>; | |
436 | status = "disabled"; | |
437 | }; | |
438 | ||
f974d685 MS |
439 | spi1: spi@7e215080 { |
440 | compatible = "brcm,bcm2835-aux-spi"; | |
441 | reg = <0x7e215080 0x40>; | |
442 | interrupts = <1 29>; | |
443 | clocks = <&aux BCM2835_AUX_CLOCK_SPI1>; | |
444 | #address-cells = <1>; | |
445 | #size-cells = <0>; | |
446 | status = "disabled"; | |
447 | }; | |
448 | ||
449 | spi2: spi@7e2150c0 { | |
450 | compatible = "brcm,bcm2835-aux-spi"; | |
451 | reg = <0x7e2150c0 0x40>; | |
452 | interrupts = <1 29>; | |
453 | clocks = <&aux BCM2835_AUX_CLOCK_SPI2>; | |
454 | #address-cells = <1>; | |
455 | #size-cells = <0>; | |
456 | status = "disabled"; | |
457 | }; | |
458 | ||
40ad4499 RP |
459 | pwm: pwm@7e20c000 { |
460 | compatible = "brcm,bcm2835-pwm"; | |
461 | reg = <0x7e20c000 0x28>; | |
462 | clocks = <&clocks BCM2835_CLOCK_PWM>; | |
463 | assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; | |
464 | assigned-clock-rates = <10000000>; | |
465 | #pwm-cells = <2>; | |
466 | status = "disabled"; | |
467 | }; | |
468 | ||
548c3a39 EA |
469 | sdhci: sdhci@7e300000 { |
470 | compatible = "brcm,bcm2835-sdhci"; | |
471 | reg = <0x7e300000 0x100>; | |
472 | interrupts = <2 30>; | |
473 | clocks = <&clocks BCM2835_CLOCK_EMMC>; | |
474 | status = "disabled"; | |
475 | }; | |
476 | ||
49ac67e0 EA |
477 | hvs@7e400000 { |
478 | compatible = "brcm,bcm2835-hvs"; | |
479 | reg = <0x7e400000 0x6000>; | |
480 | interrupts = <2 1>; | |
481 | }; | |
482 | ||
99b7dabf EA |
483 | dsi1: dsi@7e700000 { |
484 | compatible = "brcm,bcm2835-dsi1"; | |
485 | reg = <0x7e700000 0x8c>; | |
486 | interrupts = <2 12>; | |
487 | #address-cells = <1>; | |
488 | #size-cells = <0>; | |
489 | #clock-cells = <1>; | |
490 | ||
491 | clocks = <&clocks BCM2835_PLLD_DSI1>, | |
492 | <&clocks BCM2835_CLOCK_DSI1E>, | |
493 | <&clocks BCM2835_CLOCK_DSI1P>; | |
494 | clock-names = "phy", "escape", "pixel"; | |
495 | ||
496 | clock-output-names = "dsi1_byte", | |
497 | "dsi1_ddr2", | |
498 | "dsi1_ddr"; | |
499 | ||
500 | status = "disabled"; | |
501 | }; | |
502 | ||
548c3a39 EA |
503 | i2c1: i2c@7e804000 { |
504 | compatible = "brcm,bcm2835-i2c"; | |
505 | reg = <0x7e804000 0x1000>; | |
506 | interrupts = <2 21>; | |
507 | clocks = <&clocks BCM2835_CLOCK_VPU>; | |
508 | #address-cells = <1>; | |
509 | #size-cells = <0>; | |
510 | status = "disabled"; | |
511 | }; | |
512 | ||
513 | i2c2: i2c@7e805000 { | |
514 | compatible = "brcm,bcm2835-i2c"; | |
515 | reg = <0x7e805000 0x1000>; | |
516 | interrupts = <2 21>; | |
517 | clocks = <&clocks BCM2835_CLOCK_VPU>; | |
518 | #address-cells = <1>; | |
519 | #size-cells = <0>; | |
520 | status = "disabled"; | |
521 | }; | |
522 | ||
f9661d15 BB |
523 | vec: vec@7e806000 { |
524 | compatible = "brcm,bcm2835-vec"; | |
525 | reg = <0x7e806000 0x1000>; | |
526 | clocks = <&clocks BCM2835_CLOCK_VEC>; | |
527 | interrupts = <2 27>; | |
528 | status = "disabled"; | |
529 | }; | |
530 | ||
49ac67e0 EA |
531 | pixelvalve@7e807000 { |
532 | compatible = "brcm,bcm2835-pixelvalve2"; | |
533 | reg = <0x7e807000 0x100>; | |
534 | interrupts = <2 10>; /* pixelvalve */ | |
535 | }; | |
536 | ||
537 | hdmi: hdmi@7e902000 { | |
538 | compatible = "brcm,bcm2835-hdmi"; | |
539 | reg = <0x7e902000 0x600>, | |
540 | <0x7e808000 0x100>; | |
541 | interrupts = <2 8>, <2 9>; | |
542 | ddc = <&i2c2>; | |
543 | clocks = <&clocks BCM2835_PLLH_PIX>, | |
544 | <&clocks BCM2835_CLOCK_HSM>; | |
545 | clock-names = "pixel", "hdmi"; | |
546 | status = "disabled"; | |
547 | }; | |
548 | ||
5ec6f2cd | 549 | usb: usb@7e980000 { |
548c3a39 EA |
550 | compatible = "brcm,bcm2835-usb"; |
551 | reg = <0x7e980000 0x10000>; | |
552 | interrupts = <1 9>; | |
6a937927 LR |
553 | #address-cells = <1>; |
554 | #size-cells = <0>; | |
33145fac SW |
555 | clocks = <&clk_usb>; |
556 | clock-names = "otg"; | |
548c3a39 | 557 | }; |
49ac67e0 EA |
558 | |
559 | v3d: v3d@7ec00000 { | |
560 | compatible = "brcm,bcm2835-v3d"; | |
561 | reg = <0x7ec00000 0x1000>; | |
562 | interrupts = <1 10>; | |
563 | }; | |
564 | ||
565 | vc4: gpu { | |
566 | compatible = "brcm,bcm2835-vc4"; | |
567 | }; | |
548c3a39 EA |
568 | }; |
569 | ||
570 | clocks { | |
571 | compatible = "simple-bus"; | |
572 | #address-cells = <1>; | |
573 | #size-cells = <0>; | |
574 | ||
575 | /* The oscillator is the root of the clock tree. */ | |
576 | clk_osc: clock@3 { | |
577 | compatible = "fixed-clock"; | |
578 | reg = <3>; | |
579 | #clock-cells = <0>; | |
580 | clock-output-names = "osc"; | |
581 | clock-frequency = <19200000>; | |
582 | }; | |
583 | ||
33145fac SW |
584 | clk_usb: clock@4 { |
585 | compatible = "fixed-clock"; | |
586 | reg = <4>; | |
587 | #clock-cells = <0>; | |
588 | clock-output-names = "otg"; | |
589 | clock-frequency = <480000000>; | |
590 | }; | |
548c3a39 EA |
591 | }; |
592 | }; |