[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / bcm5301x.dtsi

/*
 * Broadcom BCM470X / BCM5301X ARM platform code.
 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
 *
 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <dt-bindings/clock/bcm-nsp.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	chipcommonA {
		compatible = "simple-bus";
		ranges = <0x00000000 0x18000000 0x00001000>;
		#address-cells = <1>;
		#size-cells = <1>;

		uart0: serial@300 {
			compatible = "ns16550";
			reg = <0x0300 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>;
			status = "disabled";
		};

		uart1: serial@400 {
			compatible = "ns16550";
			reg = <0x0400 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinmux_uart1>;
			status = "disabled";
		};
	};

	mpcore {
		compatible = "simple-bus";
		ranges = <0x00000000 0x19000000 0x00023000>;
		#address-cells = <1>;
		#size-cells = <1>;

		a9pll: arm_clk@0 {
			#clock-cells = <0>;
			compatible = "brcm,nsp-armpll";
			clocks = <&osc>;
			reg = <0x00000 0x1000>;
		};

		scu@20000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0x20000 0x100>;
		};

		timer@20200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20200 0x100>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
			clocks = <&periph_clk>;
		};

		timer@20600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x20600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_EDGE_RISING)>;
			clocks = <&periph_clk>;
		};

		watchdog@20620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x20620 0x20>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_EDGE_RISING)>;
			clocks = <&periph_clk>;
		};

		gic: interrupt-controller@21000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x21000 0x1000>,
			      <0x20100 0x100>;
		};

		L2: cache-controller@22000 {
			compatible = "arm,pl310-cache";
			reg = <0x22000 0x1000>;
			cache-unified;
			arm,shared-override;
			prefetch-data = <1>;
			prefetch-instr = <1>;
			cache-level = <2>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts =
			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc: oscillator {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
		};

		iprocmed: iprocmed {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		iprocslow: iprocslow {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
			clock-div = <4>;
			clock-mult = <1>;
		};

		periph_clk: periph_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&a9pll>;
			clock-div = <2>;
			clock-mult = <1>;
		};
	};

	usb2_phy: usb2-phy {
		compatible = "brcm,ns-usb2-phy";
		reg = <0x1800c000 0x1000>;
		reg-names = "dmu";
		#phy-cells = <0>;
		clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
		clock-names = "phy-ref-clk";
	};

	axi@18000000 {
		compatible = "brcm,bus-axi";
		reg = <0x18000000 0x1000>;
		ranges = <0x00000000 0x18000000 0x00100000>;
		#address-cells = <1>;
		#size-cells = <1>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0x000fffff 0xffff>;
		interrupt-map = 
			/* ChipCommon */
			<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,

			/* Switch Register Access Block */
			<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

			/* PCIe Controller 0 */
			<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

			/* PCIe Controller 1 */
			<0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
			<0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			<0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
			<0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
			<0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			<0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

			/* PCIe Controller 2 */
			<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

			/* USB 2.0 Controller */
			<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,

			/* USB 3.0 Controller */
			<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 0 */
			<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 1 */
			<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 2 */
			<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 3 */
			<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,

			/* NAND Controller */
			<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

		chipcommon: chipcommon@0 {
			reg = <0x00000000 0x1000>;

			gpio-controller;
			#gpio-cells = <2>;
		};

		pcie0: pcie@12000 {
			reg = <0x00012000 0x1000>;
		};

		pcie1: pcie@13000 {
			reg = <0x00013000 0x1000>;
		};

		usb2: usb2@21000 {
			reg = <0x00021000 0x1000>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			interrupt-parent = <&gic>;

			ehci: ehci@21000 {
				#usb-cells = <0>;

				compatible = "generic-ehci";
				reg = <0x00021000 0x1000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb2_phy>;

				#address-cells = <1>;
				#size-cells = <0>;

				ehci_port1: port@1 {
					reg = <1>;
					#trigger-source-cells = <0>;
				};

				ehci_port2: port@2 {
					reg = <2>;
					#trigger-source-cells = <0>;
				};
			};

			ohci: ohci@22000 {
				#usb-cells = <0>;

				compatible = "generic-ohci";
				reg = <0x00022000 0x1000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;
				#size-cells = <0>;

				ohci_port1: port@1 {
					reg = <1>;
					#trigger-source-cells = <0>;
				};

				ohci_port2: port@2 {
					reg = <2>;
					#trigger-source-cells = <0>;
				};
			};
		};

		usb3: usb3@23000 {
			reg = <0x00023000 0x1000>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			interrupt-parent = <&gic>;

			xhci: xhci@23000 {
				#usb-cells = <0>;

				compatible = "generic-xhci";
				reg = <0x00023000 0x1000>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb3_phy>;
				phy-names = "usb";

				#address-cells = <1>;
				#size-cells = <0>;

				xhci_port1: port@1 {
					reg = <1>;
					#trigger-source-cells = <0>;
				};
			};
		};

		gmac0: ethernet@24000 {
			reg = <0x24000 0x800>;
		};

		gmac1: ethernet@25000 {
			reg = <0x25000 0x800>;
		};

		gmac2: ethernet@26000 {
			reg = <0x26000 0x800>;
		};

		gmac3: ethernet@27000 {
			reg = <0x27000 0x800>;
		};
	};

	mdio: mdio@18003000 {
		compatible = "brcm,iproc-mdio";
		reg = <0x18003000 0x8>;
		#size-cells = <1>;
		#address-cells = <0>;
	};

	mdio-bus-mux {
		compatible = "mdio-mux-mmioreg";
		mdio-parent-bus = <&mdio>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x18003000 0x4>;
		mux-mask = <0x200>;

		mdio@0 {
			reg = <0x0>;
			#address-cells = <1>;
			#size-cells = <0>;

			usb3_phy: usb3-phy@10 {
				compatible = "brcm,ns-ax-usb3-phy";
				reg = <0x10>;
				usb3-dmp-syscon = <&usb3_dmp>;
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	usb3_dmp: syscon@18105000 {
		reg = <0x18105000 0x1000>;
	};

	i2c0: i2c@18009000 {
		compatible = "brcm,iproc-i2c";
		reg = <0x18009000 0x50>;
		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <100000>;
		status = "disabled";
	};

	dmu@1800c000 {
		compatible = "simple-bus";
		ranges = <0 0x1800c000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		cru@100 {
			compatible = "simple-bus";
			reg = <0x100 0x1a4>;
			ranges;
			#address-cells = <1>;
			#size-cells = <1>;

			pin-controller@1c0 {
				compatible = "brcm,bcm4708-pinmux";
				reg = <0x1c0 0x24>;
				reg-names = "cru_gpio_control";

				spi-pins {
					groups = "spi_grp";
					function = "spi";
				};

				i2c {
					groups = "i2c_grp";
					function = "i2c";
				};

				pwm {
					groups = "pwm0_grp", "pwm1_grp",
						 "pwm2_grp", "pwm3_grp";
					function = "pwm";
				};

				pinmux_uart1: uart1 {
					groups = "uart1_grp";
					function = "uart1";
				};
			};
		};
	};

	lcpll0: lcpll0@1800c100 {
		#clock-cells = <1>;
		compatible = "brcm,nsp-lcpll0";
		reg = <0x1800c100 0x14>;
		clocks = <&osc>;
		clock-output-names = "lcpll0", "pcie_phy", "sdio",
				     "ddr_phy";
	};

	genpll: genpll@1800c140 {
		#clock-cells = <1>;
		compatible = "brcm,nsp-genpll";
		reg = <0x1800c140 0x24>;
		clocks = <&osc>;
		clock-output-names = "genpll", "phy", "ethernetclk",
				     "usbclk", "iprocfast", "sata1",
				     "sata2";
	};

	thermal: thermal@1800c2c0 {
		compatible = "brcm,ns-thermal";
		reg = <0x1800c2c0 0x10>;
		#thermal-sensor-cells = <0>;
	};

	srab: srab@18007000 {
		compatible = "brcm,bcm5301x-srab";
		reg = <0x18007000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;

		status = "disabled";

		/* ports are defined in board DTS */
	};

	rng: rng@18004000 {
		compatible = "brcm,bcm5301x-rng";
		reg = <0x18004000 0x14>;
	};

	nand: nand@18028000 {
		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
		reg-names = "nand", "iproc-idm", "iproc-ext";
		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;
		#size-cells = <0>;

		brcm,nand-has-wp;
	};

	spi@18029200 {
		compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
		reg = <0x18029200 0x184>,
		      <0x18029000 0x124>,
		      <0x1811b408 0x004>,
		      <0x180293a0 0x01c>;
		reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "spi_lr_fullness_reached",
				  "spi_lr_session_aborted",
				  "spi_lr_impatient",
				  "spi_lr_session_done",
				  "spi_lr_overhead",
				  "mspi_done",
				  "mspi_halted";
		clocks = <&iprocmed>;
		clock-names = "iprocmed";
		num-cs = <2>;
		#address-cells = <1>;
		#size-cells = <0>;

		spi_nor: spi-nor@0 {
			compatible = "jedec,spi-nor";
			reg = <0>;
			spi-max-frequency = <20000000>;
			status = "disabled";

			partitions {
				compatible = "brcm,bcm947xx-cfe-partitions";
			};
		};
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			coefficients = <(-556) 418000>;
			thermal-sensors = <&thermal>;

			trips {
				cpu-crit {
					temperature	= <125000>;
					hysteresis	= <0>;
					type		= "critical";
				};
			};

			cooling-maps {
			};
		};
	};
};
Commit	Line	Data
d27509f1 HM	1	/*
	2	* Broadcom BCM470X / BCM5301X ARM platform code.
	3	* Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
	4	* BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
	5	*
	6	* Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
	7	*
	8	* Licensed under the GNU/GPL. See COPYING for details.
	9	*/
	10
cdc36b22	11	#include <dt-bindings/clock/bcm-nsp.h>
fb026d3d	12	#include <dt-bindings/gpio/gpio.h>
f6f82344	13	#include <dt-bindings/input/input.h>
d27509f1 HM	14	#include <dt-bindings/interrupt-controller/irq.h>
d27509f1 HM	15	#include <dt-bindings/interrupt-controller/arm-gic.h>
d27509f1 HM	16
d27509f1 HM	17	/ {
abe60a3a RH	18	#address-cells = <1>;
abe60a3a RH	19	#size-cells = <1>;
d27509f1 HM	20	interrupt-parent = <&gic>;
	21
	22	chipcommonA {
	23	compatible = "simple-bus";
	24	ranges = <0x00000000 0x18000000 0x00001000>;
	25	#address-cells = <1>;
	26	#size-cells = <1>;
	27
8dccafaa	28	uart0: serial@300 {
d27509f1 HM	29	compatible = "ns16550";
	30	reg = <0x0300 0x100>;
	31	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
cdc36b22	32	clocks = <&iprocslow>;
d27509f1 HM	33	status = "disabled";
	34	};
	35
8dccafaa	36	uart1: serial@400 {
d27509f1 HM	37	compatible = "ns16550";
	38	reg = <0x0400 0x100>;
	39	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
cdc36b22	40	clocks = <&iprocslow>;
9994241a RM	41	pinctrl-names = "default";
9994241a RM	42	pinctrl-0 = <&pinmux_uart1>;
d27509f1 HM	43	status = "disabled";
	44	};
	45	};
	46
	47	mpcore {
	48	compatible = "simple-bus";
cdc36b22	49	ranges = <0x00000000 0x19000000 0x00023000>;
d27509f1 HM	50	#address-cells = <1>;
	51	#size-cells = <1>;
	52
8dccafaa	53	a9pll: arm_clk@0 {
cdc36b22 JM	54	#clock-cells = <0>;
	55	compatible = "brcm,nsp-armpll";
	56	clocks = <&osc>;
	57	reg = <0x00000 0x1000>;
	58	};
	59
	60	scu@20000 {
d27509f1	61	compatible = "arm,cortex-a9-scu";
cdc36b22	62	reg = <0x20000 0x100>;
d27509f1 HM	63	};
d27509f1 HM	64
cdc36b22	65	timer@20200 {
d27509f1	66	compatible = "arm,cortex-a9-global-timer";
cdc36b22	67	reg = <0x20200 0x100>;
0e34079c	68	interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
cdc36b22	69	clocks = <&periph_clk>;
d27509f1 HM	70	};
d27509f1 HM	71
f22c635e	72	timer@20600 {
d27509f1	73	compatible = "arm,cortex-a9-twd-timer";
f22c635e JM	74	reg = <0x20600 0x20>;
	75	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \|
	76	IRQ_TYPE_EDGE_RISING)>;
	77	clocks = <&periph_clk>;
	78	};
	79
	80	watchdog@20620 {
	81	compatible = "arm,cortex-a9-twd-wdt";
	82	reg = <0x20620 0x20>;
	83	interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \|
	84	IRQ_TYPE_EDGE_RISING)>;
cdc36b22	85	clocks = <&periph_clk>;
d27509f1 HM	86	};
d27509f1 HM	87
cdc36b22	88	gic: interrupt-controller@21000 {
d27509f1 HM	89	compatible = "arm,cortex-a9-gic";
	90	#interrupt-cells = <3>;
	91	#address-cells = <0>;
	92	interrupt-controller;
cdc36b22 JM	93	reg = <0x21000 0x1000>,
cdc36b22 JM	94	<0x20100 0x100>;
d27509f1 HM	95	};
d27509f1 HM	96
cdc36b22	97	L2: cache-controller@22000 {
d27509f1	98	compatible = "arm,pl310-cache";
cdc36b22	99	reg = <0x22000 0x1000>;
d27509f1	100	cache-unified;
db44f134 HM	101	arm,shared-override;
	102	prefetch-data = <1>;
	103	prefetch-instr = <1>;
d27509f1 HM	104	cache-level = <2>;
	105	};
	106	};
	107
1ff80363 FF	108	pmu {
	109	compatible = "arm,cortex-a9-pmu";
	110	interrupts =
	111	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	112	<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	113	};
	114
d27509f1 HM	115	clocks {
d27509f1 HM	116	#address-cells = <1>;
cdc36b22 JM	117	#size-cells = <1>;
cdc36b22 JM	118	ranges;
d27509f1	119
cdc36b22 JM	120	osc: oscillator {
cdc36b22 JM	121	#clock-cells = <0>;
d27509f1	122	compatible = "fixed-clock";
cdc36b22 JM	123	clock-frequency = <25000000>;
	124	};
	125
	126	iprocmed: iprocmed {
	127	#clock-cells = <0>;
	128	compatible = "fixed-factor-clock";
	129	clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
	130	clock-div = <2>;
	131	clock-mult = <1>;
	132	};
	133
	134	iprocslow: iprocslow {
	135	#clock-cells = <0>;
	136	compatible = "fixed-factor-clock";
	137	clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
	138	clock-div = <4>;
	139	clock-mult = <1>;
	140	};
	141
	142	periph_clk: periph_clk {
d27509f1	143	#clock-cells = <0>;
cdc36b22 JM	144	compatible = "fixed-factor-clock";
	145	clocks = <&a9pll>;
	146	clock-div = <2>;
	147	clock-mult = <1>;
d27509f1 HM	148	};
d27509f1 HM	149	};
fb026d3d	150
2709d393 RM	151	usb2_phy: usb2-phy {
	152	compatible = "brcm,ns-usb2-phy";
	153	reg = <0x1800c000 0x1000>;
	154	reg-names = "dmu";
	155	#phy-cells = <0>;
	156	clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
	157	clock-names = "phy-ref-clk";
	158	};
	159
fb026d3d RM	160	axi@18000000 {
	161	compatible = "brcm,bus-axi";
	162	reg = <0x18000000 0x1000>;
	163	ranges = <0x00000000 0x18000000 0x00100000>;
	164	#address-cells = <1>;
	165	#size-cells = <1>;
	166
dec37882 HM	167	#interrupt-cells = <1>;
	168	interrupt-map-mask = <0x000fffff 0xffff>;
	169	interrupt-map =
	170	/* ChipCommon */
	171	<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	172
2cd0c020 FF	173	/* Switch Register Access Block */
	174	<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
	175	<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
	176	<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	177	<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	178	<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	179	<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	180	<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	181	<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	182	<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	183	<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	184	<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	185	<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	186	<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	187
1f80de68 HM	188	/* PCIe Controller 0 */
	189	<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	190	<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
	191	<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	192	<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	193	<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	194	<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	195
	196	/* PCIe Controller 1 */
	197	<0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	198	<0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	199	<0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	200	<0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	201	<0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	202	<0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	203
	204	/* PCIe Controller 2 */
	205	<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	206	<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	207	<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	208	<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	209	<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	210	<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
	211
dec37882 HM	212	/* USB 2.0 Controller */
	213	<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
	214
	215	/* USB 3.0 Controller */
	216	<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
	217
	218	/* Ethernet Controller 0 */
	219	<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
	220
	221	/* Ethernet Controller 1 */
	222	<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	223
	224	/* Ethernet Controller 2 */
	225	<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	226
	227	/* Ethernet Controller 3 */
	228	<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
	229
	230	/* NAND Controller */
	231	<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
	232	<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
	233	<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	234	<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	235	<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	236	<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	237	<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	238	<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	239
fb026d3d RM	240	chipcommon: chipcommon@0 {
	241	reg = <0x00000000 0x1000>;
	242
	243	gpio-controller;
	244	#gpio-cells = <2>;
	245	};
dd70ccfa	246
5d1f2d2c RM	247	pcie0: pcie@12000 {
	248	reg = <0x00012000 0x1000>;
	249	};
	250
	251	pcie1: pcie@13000 {
	252	reg = <0x00013000 0x1000>;
	253	};
	254
dd70ccfa RM	255	usb2: usb2@21000 {
	256	reg = <0x00021000 0x1000>;
	257
	258	#address-cells = <1>;
	259	#size-cells = <1>;
0725c842	260	ranges;
2709d393	261
0725c842 RM	262	interrupt-parent = <&gic>;
	263
	264	ehci: ehci@21000 {
	265	#usb-cells = <0>;
	266
	267	compatible = "generic-ehci";
	268	reg = <0x00021000 0x1000>;
	269	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	270	phys = <&usb2_phy>;
69d22c70 RM	271
	272	#address-cells = <1>;
	273	#size-cells = <0>;
	274
	275	ehci_port1: port@1 {
	276	reg = <1>;
	277	#trigger-source-cells = <0>;
	278	};
	279
	280	ehci_port2: port@2 {
	281	reg = <2>;
	282	#trigger-source-cells = <0>;
	283	};
0725c842 RM	284	};
	285
	286	ohci: ohci@22000 {
	287	#usb-cells = <0>;
	288
	289	compatible = "generic-ohci";
	290	reg = <0x00022000 0x1000>;
	291	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
69d22c70 RM	292
	293	#address-cells = <1>;
	294	#size-cells = <0>;
	295
	296	ohci_port1: port@1 {
	297	reg = <1>;
	298	#trigger-source-cells = <0>;
	299	};
	300
	301	ohci_port2: port@2 {
	302	reg = <2>;
	303	#trigger-source-cells = <0>;
	304	};
0725c842	305	};
dd70ccfa RM	306	};
	307
	308	usb3: usb3@23000 {
	309	reg = <0x00023000 0x1000>;
	310
	311	#address-cells = <1>;
	312	#size-cells = <1>;
0725c842 RM	313	ranges;
	314
	315	interrupt-parent = <&gic>;
	316
	317	xhci: xhci@23000 {
	318	#usb-cells = <0>;
	319
	320	compatible = "generic-xhci";
	321	reg = <0x00023000 0x1000>;
	322	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	323	phys = <&usb3_phy>;
	324	phy-names = "usb";
69d22c70 RM	325
	326	#address-cells = <1>;
	327	#size-cells = <0>;
	328
	329	xhci_port1: port@1 {
	330	reg = <1>;
	331	#trigger-source-cells = <0>;
	332	};
0725c842	333	};
dd70ccfa	334	};
1b47b98a	335
59f0ce1a FF	336	gmac0: ethernet@24000 {
	337	reg = <0x24000 0x800>;
	338	};
	339
	340	gmac1: ethernet@25000 {
	341	reg = <0x25000 0x800>;
	342	};
	343
	344	gmac2: ethernet@26000 {
	345	reg = <0x26000 0x800>;
	346	};
	347
	348	gmac3: ethernet@27000 {
	349	reg = <0x27000 0x800>;
	350	};
fb026d3d	351	};
9faa5960	352
23f1eca6 RM	353	mdio: mdio@18003000 {
	354	compatible = "brcm,iproc-mdio";
	355	reg = <0x18003000 0x8>;
	356	#size-cells = <1>;
	357	#address-cells = <0>;
37f6130e VU	358	};
	359
	360	mdio-bus-mux {
	361	compatible = "mdio-mux-mmioreg";
	362	mdio-parent-bus = <&mdio>;
	363	#address-cells = <1>;
	364	#size-cells = <0>;
	365	reg = <0x18003000 0x4>;
	366	mux-mask = <0x200>;
	367
	368	mdio@0 {
	369	reg = <0x0>;
	370	#address-cells = <1>;
	371	#size-cells = <0>;
	372
	373	usb3_phy: usb3-phy@10 {
	374	compatible = "brcm,ns-ax-usb3-phy";
	375	reg = <0x10>;
	376	usb3-dmp-syscon = <&usb3_dmp>;
	377	#phy-cells = <0>;
	378	status = "disabled";
	379	};
	380	};
	381	};
	382
	383	usb3_dmp: syscon@18105000 {
	384	reg = <0x18105000 0x1000>;
23f1eca6 RM	385	};
23f1eca6 RM	386
bb097e3e JM	387	i2c0: i2c@18009000 {
	388	compatible = "brcm,iproc-i2c";
	389	reg = <0x18009000 0x50>;
a0a8338e	390	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
bb097e3e JM	391	#address-cells = <1>;
	392	#size-cells = <0>;
	393	clock-frequency = <100000>;
	394	status = "disabled";
	395	};
	396
9994241a RM	397	dmu@1800c000 {
	398	compatible = "simple-bus";
	399	ranges = <0 0x1800c000 0x1000>;
	400	#address-cells = <1>;
	401	#size-cells = <1>;
	402
	403	cru@100 {
	404	compatible = "simple-bus";
	405	reg = <0x100 0x1a4>;
	406	ranges;
	407	#address-cells = <1>;
	408	#size-cells = <1>;
	409
	410	pin-controller@1c0 {
	411	compatible = "brcm,bcm4708-pinmux";
	412	reg = <0x1c0 0x24>;
	413	reg-names = "cru_gpio_control";
	414
	415	spi-pins {
	416	groups = "spi_grp";
	417	function = "spi";
	418	};
	419
	420	i2c {
	421	groups = "i2c_grp";
	422	function = "i2c";
	423	};
	424
	425	pwm {
	426	groups = "pwm0_grp", "pwm1_grp",
	427	"pwm2_grp", "pwm3_grp";
	428	function = "pwm";
	429	};
	430
	431	pinmux_uart1: uart1 {
	432	groups = "uart1_grp";
	433	function = "uart1";
	434	};
	435	};
	436	};
	437	};
	438
cdc36b22 JM	439	lcpll0: lcpll0@1800c100 {
	440	#clock-cells = <1>;
	441	compatible = "brcm,nsp-lcpll0";
	442	reg = <0x1800c100 0x14>;
	443	clocks = <&osc>;
	444	clock-output-names = "lcpll0", "pcie_phy", "sdio",
	445	"ddr_phy";
	446	};
	447
	448	genpll: genpll@1800c140 {
	449	#clock-cells = <1>;
	450	compatible = "brcm,nsp-genpll";
	451	reg = <0x1800c140 0x24>;
	452	clocks = <&osc>;
	453	clock-output-names = "genpll", "phy", "ethernetclk",
	454	"usbclk", "iprocfast", "sata1",
	455	"sata2";
	456	};
	457
36c2cb18 RM	458	thermal: thermal@1800c2c0 {
	459	compatible = "brcm,ns-thermal";
	460	reg = <0x1800c2c0 0x10>;
	461	#thermal-sensor-cells = <0>;
	462	};
	463
59f0ce1a FF	464	srab: srab@18007000 {
	465	compatible = "brcm,bcm5301x-srab";
	466	reg = <0x18007000 0x1000>;
	467	#address-cells = <1>;
	468	#size-cells = <0>;
	469
	470	status = "disabled";
	471
	472	/* ports are defined in board DTS */
	473	};
	474
36e55669 FF	475	rng: rng@18004000 {
	476	compatible = "brcm,bcm5301x-rng";
	477	reg = <0x18004000 0x14>;
	478	};
	479
9faa5960 HM	480	nand: nand@18028000 {
	481	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
	482	reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
	483	reg-names = "nand", "iproc-idm", "iproc-ext";
	484	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	485
	486	#address-cells = <1>;
	487	#size-cells = <0>;
	488
	489	brcm,nand-has-wp;
	490	};
1c8f4065 JM	491
	492	spi@18029200 {
	493	compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
	494	reg = <0x18029200 0x184>,
	495	<0x18029000 0x124>,
	496	<0x1811b408 0x004>,
	497	<0x180293a0 0x01c>;
	498	reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
	499	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	500	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
	501	<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
	502	<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
	503	<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	504	<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
	505	<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	506	interrupt-names = "spi_lr_fullness_reached",
	507	"spi_lr_session_aborted",
	508	"spi_lr_impatient",
	509	"spi_lr_session_done",
	510	"spi_lr_overhead",
	511	"mspi_done",
	512	"mspi_halted";
	513	clocks = <&iprocmed>;
	514	clock-names = "iprocmed";
	515	num-cs = <2>;
	516	#address-cells = <1>;
	517	#size-cells = <0>;
	518
	519	spi_nor: spi-nor@0 {
	520	compatible = "jedec,spi-nor";
	521	reg = <0>;
	522	spi-max-frequency = <20000000>;
1c8f4065	523	status = "disabled";
b0465fdf RM	524
	525	partitions {
	526	compatible = "brcm,bcm947xx-cfe-partitions";
	527	};
1c8f4065 JM	528	};
1c8f4065 JM	529	};
36c2cb18 RM	530
	531	thermal-zones {
	532	cpu_thermal: cpu-thermal {
	533	polling-delay-passive = <0>;
	534	polling-delay = <1000>;
	535	coefficients = <(-556) 418000>;
	536	thermal-sensors = <&thermal>;
	537
	538	trips {
	539	cpu-crit {
	540	temperature = <125000>;
	541	hysteresis = <0>;
	542	type = "critical";
	543	};
	544	};
	545
	546	cooling-maps {
	547	};
	548	};
	549	};
d27509f1	550	};