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1 | /* |
2 | * Broadcom BCM63138 DSL SoCs Device Tree | |
3 | */ | |
4 | ||
5 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
6 | #include <dt-bindings/interrupt-controller/irq.h> | |
7 | ||
8 | #include "skeleton.dtsi" | |
9 | ||
10 | / { | |
11 | compatible = "brcm,bcm63138"; | |
12 | model = "Broadcom BCM63138 DSL SoC"; | |
13 | interrupt-parent = <&gic>; | |
14 | ||
15 | aliases { | |
16 | uart0 = &serial0; | |
17 | uart1 = &serial1; | |
18 | }; | |
19 | ||
20 | cpus { | |
21 | #address-cells = <1>; | |
22 | #size-cells = <0>; | |
23 | ||
24 | cpu@0 { | |
25 | device_type = "cpu"; | |
26 | compatible = "arm,cortex-a9"; | |
27 | next-level-cache = <&L2>; | |
28 | reg = <0>; | |
29 | }; | |
30 | ||
31 | cpu@1 { | |
32 | device_type = "cpu"; | |
33 | compatible = "arm,cortex-a9"; | |
34 | next-level-cache = <&L2>; | |
35 | reg = <1>; | |
36 | }; | |
37 | }; | |
38 | ||
39 | clocks { | |
40 | #address-cells = <1>; | |
41 | #size-cells = <0>; | |
42 | ||
43 | arm_timer_clk: arm_timer_clk { | |
44 | #clock-cells = <0>; | |
45 | compatible = "fixed-clock"; | |
46 | clock-frequency = <500000000>; | |
47 | }; | |
48 | ||
49 | periph_clk: periph_clk { | |
50 | #clock-cells = <0>; | |
51 | compatible = "fixed-clock"; | |
52 | clock-frequency = <50000000>; | |
53 | clock-output-names = "periph"; | |
54 | }; | |
55 | }; | |
56 | ||
57 | /* ARM bus */ | |
58 | axi@80000000 { | |
59 | compatible = "simple-bus"; | |
60 | ranges = <0 0x80000000 0x784000>; | |
61 | #address-cells = <1>; | |
62 | #size-cells = <1>; | |
63 | ||
64 | L2: cache-controller@1d000 { | |
65 | compatible = "arm,pl310-cache"; | |
66 | reg = <0x1d000 0x1000>; | |
67 | cache-unified; | |
68 | cache-level = <2>; | |
69 | cache-sets = <16>; | |
70 | cache-size = <0x80000>; | |
71 | interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; | |
72 | }; | |
73 | ||
74 | scu: scu@1e000 { | |
75 | compatible = "arm,cortex-a9-scu"; | |
76 | reg = <0x1e000 0x100>; | |
77 | }; | |
78 | ||
79 | gic: interrupt-controller@1e100 { | |
80 | compatible = "arm,cortex-a9-gic"; | |
81 | reg = <0x1f000 0x1000 | |
82 | 0x1e100 0x100>; | |
83 | #interrupt-cells = <3>; | |
84 | #address-cells = <0>; | |
85 | interrupt-controller; | |
86 | }; | |
87 | ||
88 | global_timer: timer@1e200 { | |
89 | compatible = "arm,cortex-a9-global-timer"; | |
90 | reg = <0x1e200 0x20>; | |
91 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
92 | clocks = <&arm_timer_clk>; | |
93 | }; | |
94 | ||
95 | local_timer: local-timer@1e600 { | |
96 | compatible = "arm,cortex-a9-twd-timer"; | |
97 | reg = <0x1e600 0x20>; | |
98 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
99 | clocks = <&arm_timer_clk>; | |
100 | }; | |
101 | ||
102 | twd_watchdog: watchdog@1e620 { | |
103 | compatible = "arm,cortex-a9-twd-wdt"; | |
104 | reg = <0x1e620 0x20>; | |
105 | interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
106 | }; | |
107 | }; | |
108 | ||
109 | /* Legacy UBUS base */ | |
110 | ubus@fffe8000 { | |
111 | compatible = "simple-bus"; | |
112 | #address-cells = <1>; | |
113 | #size-cells = <1>; | |
114 | ranges = <0 0xfffe8000 0x8100>; | |
115 | ||
116 | serial0: serial@600 { | |
117 | compatible = "brcm,bcm6345-uart"; | |
118 | reg = <0x600 0x1b>; | |
119 | interrupts = <GIC_SPI 32 0>; | |
120 | clocks = <&periph_clk>; | |
121 | clock-names = "periph"; | |
122 | status = "disabled"; | |
123 | }; | |
124 | ||
125 | serial1: serial@620 { | |
126 | compatible = "brcm,bcm6345-uart"; | |
127 | reg = <0x620 0x1b>; | |
128 | interrupts = <GIC_SPI 33 0>; | |
129 | clocks = <&periph_clk>; | |
130 | clock-names = "periph"; | |
131 | status = "disabled"; | |
132 | }; | |
133 | }; | |
134 | }; |