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79187a8e MC |
1 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
2 | ||
3 | #include "skeleton.dtsi" | |
4 | ||
5 | / { | |
6 | #address-cells = <2>; | |
7 | #size-cells = <2>; | |
8 | model = "Broadcom STB (bcm7445)"; | |
9 | compatible = "brcm,bcm7445", "brcm,brcmstb"; | |
10 | interrupt-parent = <&gic>; | |
11 | ||
12 | chosen { | |
13 | bootargs = "console=ttyS0,115200 earlyprintk"; | |
14 | }; | |
15 | ||
16 | cpus { | |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
20 | cpu@0 { | |
21 | compatible = "brcm,brahma-b15"; | |
22 | device_type = "cpu"; | |
23 | enable-method = "brcm,brahma-b15"; | |
24 | reg = <0>; | |
25 | }; | |
26 | ||
27 | cpu@1 { | |
28 | compatible = "brcm,brahma-b15"; | |
29 | device_type = "cpu"; | |
30 | enable-method = "brcm,brahma-b15"; | |
31 | reg = <1>; | |
32 | }; | |
33 | ||
34 | cpu@2 { | |
35 | compatible = "brcm,brahma-b15"; | |
36 | device_type = "cpu"; | |
37 | enable-method = "brcm,brahma-b15"; | |
38 | reg = <2>; | |
39 | }; | |
40 | ||
41 | cpu@3 { | |
42 | compatible = "brcm,brahma-b15"; | |
43 | device_type = "cpu"; | |
44 | enable-method = "brcm,brahma-b15"; | |
45 | reg = <3>; | |
46 | }; | |
47 | }; | |
48 | ||
49 | gic: interrupt-controller@ffd00000 { | |
50 | compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic"; | |
51 | reg = <0x00 0xffd01000 0x00 0x1000>, | |
52 | <0x00 0xffd02000 0x00 0x2000>, | |
53 | <0x00 0xffd04000 0x00 0x2000>, | |
54 | <0x00 0xffd06000 0x00 0x2000>; | |
55 | interrupt-controller; | |
56 | #interrupt-cells = <3>; | |
57 | }; | |
58 | ||
59 | timer { | |
60 | compatible = "arm,armv7-timer"; | |
61 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, | |
62 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, | |
63 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, | |
64 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; | |
65 | }; | |
66 | ||
67 | rdb { | |
68 | #address-cells = <1>; | |
69 | #size-cells = <1>; | |
70 | compatible = "simple-bus"; | |
71 | ranges = <0 0x00 0xf0000000 0x1000000>; | |
72 | ||
73 | serial@40ab00 { | |
74 | compatible = "ns16550a"; | |
75 | reg = <0x40ab00 0x20>; | |
76 | reg-shift = <2>; | |
77 | reg-io-width = <4>; | |
78 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
e36fcd13 | 79 | clock-frequency = <81000000>; |
79187a8e MC |
80 | }; |
81 | ||
82 | sun_top_ctrl: syscon@404000 { | |
83 | compatible = "brcm,bcm7445-sun-top-ctrl", | |
84 | "syscon"; | |
85 | reg = <0x404000 0x51c>; | |
86 | }; | |
87 | ||
88 | hif_cpubiuctrl: syscon@3e2400 { | |
89 | compatible = "brcm,bcm7445-hif-cpubiuctrl", | |
90 | "syscon"; | |
91 | reg = <0x3e2400 0x5b4>; | |
92 | }; | |
93 | ||
94 | hif_continuation: syscon@452000 { | |
95 | compatible = "brcm,bcm7445-hif-continuation", | |
96 | "syscon"; | |
97 | reg = <0x452000 0x100>; | |
98 | }; | |
0c02acec | 99 | |
6054ef25 | 100 | irq0_intc: interrupt-controller@40a780 { |
0c02acec BN |
101 | compatible = "brcm,bcm7120-l2-intc"; |
102 | interrupt-parent = <&gic>; | |
103 | #interrupt-cells = <1>; | |
104 | reg = <0x40a780 0x8>; | |
105 | interrupt-controller; | |
106 | interrupts = <GIC_SPI 0x45 0x0>, | |
107 | <GIC_SPI 0x43 0x0>; | |
108 | brcm,int-map-mask = <0x25c>, <0x7000000>; | |
109 | brcm,int-fwd-mask = <0x70000>; | |
110 | }; | |
3420ab38 | 111 | |
e73ff4d2 GF |
112 | irq0_aon_intc: interrupt-controller@417280 { |
113 | compatible = "brcm,bcm7120-l2-intc"; | |
114 | reg = <0x417280 0x8>; | |
115 | interrupt-parent = <&gic>; | |
116 | #interrupt-cells = <1>; | |
117 | interrupt-controller; | |
118 | interrupts = <GIC_SPI 0x46 0x0>, | |
119 | <GIC_SPI 0x44 0x0>, | |
120 | <GIC_SPI 0x49 0x0>; | |
121 | brcm,int-map-mask = <0x1e3 0x18000000 0x100000>; | |
122 | brcm,int-fwd-mask = <0x0>; | |
123 | brcm,irq-can-wake; | |
124 | }; | |
125 | ||
3420ab38 BN |
126 | hif_intr2_intc: interrupt-controller@3e1000 { |
127 | compatible = "brcm,l2-intc"; | |
128 | reg = <0x3e1000 0x30>; | |
129 | interrupt-controller; | |
130 | #interrupt-cells = <1>; | |
131 | interrupts = <GIC_SPI 0x20 0x0>; | |
132 | interrupt-parent = <&gic>; | |
133 | interrupt-names = "hif"; | |
134 | }; | |
135 | ||
e73ff4d2 GF |
136 | aon_pm_l2_intc: interrupt-controller@410640 { |
137 | compatible = "brcm,l2-intc"; | |
138 | reg = <0x410640 0x30>; | |
139 | interrupt-controller; | |
140 | #interrupt-cells = <1>; | |
141 | interrupts = <GIC_SPI 0x40 0x0>; | |
142 | interrupt-parent = <&gic>; | |
143 | brcm,irq-can-wake; | |
144 | }; | |
145 | ||
3420ab38 BN |
146 | nand: nand@3e2800 { |
147 | status = "disabled"; | |
148 | #address-cells = <1>; | |
149 | #size-cells = <0>; | |
150 | compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; | |
151 | reg-names = "nand", "flash-dma"; | |
152 | reg = <0x3e2800 0x600>, <0x3e3000 0x2c>; | |
153 | interrupt-parent = <&hif_intr2_intc>; | |
154 | interrupts = <24>, <4>; | |
155 | interrupt-names = "nand_ctlrdy", "flash_dma_done"; | |
156 | }; | |
592e2ddf BN |
157 | |
158 | sata@45a000 { | |
159 | compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; | |
160 | reg-names = "ahci", "top-ctrl"; | |
161 | reg = <0x45a000 0xa9c>, <0x458040 0x24>; | |
162 | interrupts = <GIC_SPI 30 0>; | |
163 | #address-cells = <1>; | |
164 | #size-cells = <0>; | |
165 | ||
166 | sata0: sata-port@0 { | |
167 | reg = <0>; | |
168 | phys = <&sata_phy0>; | |
169 | }; | |
170 | ||
171 | sata1: sata-port@1 { | |
172 | reg = <1>; | |
173 | phys = <&sata_phy1>; | |
174 | }; | |
175 | }; | |
176 | ||
177 | sata_phy: sata-phy@458100 { | |
178 | compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; | |
179 | reg = <0x458100 0x1f00>; | |
180 | reg-names = "phy"; | |
181 | #address-cells = <0x1>; | |
182 | #size-cells = <0x0>; | |
183 | ||
184 | sata_phy0: sata-phy@0 { | |
185 | reg = <0>; | |
186 | #phy-cells = <0>; | |
187 | }; | |
188 | ||
189 | sata_phy1: sata-phy@1 { | |
190 | reg = <1>; | |
191 | #phy-cells = <0>; | |
192 | }; | |
193 | }; | |
e73ff4d2 GF |
194 | |
195 | upg_gio: gpio@40a700 { | |
196 | compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; | |
197 | reg = <0x40a700 0x80>; | |
198 | #gpio-cells = <2>; | |
199 | #interrupt-cells = <2>; | |
200 | gpio-controller; | |
201 | interrupt-controller; | |
202 | interrupt-parent = <&irq0_intc>; | |
203 | interrupts = <6>; | |
204 | brcm,gpio-bank-widths = <32 32 32 24>; | |
205 | }; | |
206 | ||
207 | upg_gio_aon: gpio@4172c0 { | |
208 | compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; | |
209 | reg = <0x4172c0 0x40>; | |
210 | #gpio-cells = <2>; | |
211 | #interrupt-cells = <2>; | |
212 | gpio-controller; | |
213 | interrupt-controller; | |
214 | interrupts-extended = <&irq0_aon_intc 0x6>, | |
215 | <&aon_pm_l2_intc 0x5>; | |
216 | wakeup-source; | |
217 | brcm,gpio-bank-widths = <18 4>; | |
218 | }; | |
219 | ||
79187a8e MC |
220 | }; |
221 | ||
222 | smpboot { | |
223 | compatible = "brcm,brcmstb-smpboot"; | |
224 | syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; | |
225 | syscon-cont = <&hif_continuation>; | |
226 | }; | |
227 | ||
228 | reboot { | |
229 | compatible = "brcm,brcmstb-reboot"; | |
230 | syscon = <&sun_top_ctrl 0x304 0x308>; | |
231 | }; | |
232 | }; |