[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / berlin2.dtsi

/*
 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * based on GPL'ed 2.6 kernel sources
 *  (c) Marvell International Ltd.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include "skeleton.dtsi"
#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500 (BG2) SoC";
	compatible = "marvell,berlin2", "marvell,berlin";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,berlin-smp";

		cpu@0 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};

		cpu@1 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;

		ranges = <0 0xf7000000 0x1000000>;

		l2: l2-cache-controller@ac0000 {
			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip CLKID_TWD>;
		};

		eth1: ethernet@b90000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xb90000 0x10000>;
			clocks = <&chip CLKID_GETH1>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy1>;
			status = "disabled";

			ethphy1: ethernet-phy@0 {
				reg = <0>;
			};
		};

		cpu-ctrl@dd0000 {
			compatible = "marvell,berlin-cpu-ctrl";
			reg = <0xdd0000 0x10000>;
		};

		eth0: ethernet@e50000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xe50000 0x10000>;
			clocks = <&chip CLKID_GETH0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy0>;
			status = "disabled";

			ethphy0: ethernet-phy@0 {
				reg = <0>;
			};
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@0400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@0800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@0c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				interrupts = <8>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				interrupts = <9>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				interrupts = <10>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				interrupts = <11>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				interrupts = <12>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				interrupts = <13>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				interrupts = <14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				interrupts = <15>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3000 0xc00>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		chip: chip-control@ea0000 {
			compatible = "marvell,berlin2-chip-ctrl";
			#clock-cells = <1>;
			#reset-cells = <2>;
			reg = <0xea0000 0x400>;
			clocks = <&refclk>;
			clock-names = "refclk";
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			sm_gpio1: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
				};
			};

			sm_gpio0: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <11>;
				};
			};

			uart0: serial@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <8>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: serial@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <9>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart2: serial@b000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xb000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <10>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart2_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sysctrl: system-controller@d000 {
				compatible = "marvell,berlin2-system-ctrl";
				reg = <0xd000 0x100>;

				uart0_pmux: uart0-pmux {
					groups = "GSM4";
					function = "uart0";
				};

				uart1_pmux: uart1-pmux {
					groups = "GSM5";
					function = "uart1";
				};

				uart2_pmux: uart2-pmux {
					groups = "GSM3";
					function = "uart2";
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x400>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
2440946c SH	1	/*
	2	* Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
	3	*
	4	* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
	5	*
	6	* based on GPL'ed 2.6 kernel sources
	7	* (c) Marvell International Ltd.
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include "skeleton.dtsi"
36601dbf	15	#include <dt-bindings/clock/berlin2.h>
2440946c SH	16	#include <dt-bindings/interrupt-controller/arm-gic.h>
	17
	18	/ {
	19	model = "Marvell Armada 1500 (BG2) SoC";
	20	compatible = "marvell,berlin2", "marvell,berlin";
	21
	22	cpus {
	23	#address-cells = <1>;
	24	#size-cells = <0>;
460d02ac	25	enable-method = "marvell,berlin-smp";
2440946c SH	26
	27	cpu@0 {
	28	compatible = "marvell,pj4b";
	29	device_type = "cpu";
	30	next-level-cache = <&l2>;
	31	reg = <0>;
	32	};
	33
	34	cpu@1 {
	35	compatible = "marvell,pj4b";
	36	device_type = "cpu";
	37	next-level-cache = <&l2>;
	38	reg = <1>;
	39	};
	40	};
	41
36601dbf SH	42	refclk: oscillator {
	43	compatible = "fixed-clock";
	44	#clock-cells = <0>;
	45	clock-frequency = <25000000>;
2440946c SH	46	};
	47
	48	soc {
	49	compatible = "simple-bus";
	50	#address-cells = <1>;
	51	#size-cells = <1>;
	52	interrupt-parent = <&gic>;
	53
	54	ranges = <0 0xf7000000 0x1000000>;
	55
	56	l2: l2-cache-controller@ac0000 {
	57	compatible = "marvell,tauros3-cache", "arm,pl310-cache";
	58	reg = <0xac0000 0x1000>;
	59	cache-unified;
	60	cache-level = <2>;
	61	};
	62
0bd4b346 SH	63	scu: snoop-control-unit@ad0000 {
	64	compatible = "arm,cortex-a9-scu";
	65	reg = <0xad0000 0x58>;
	66	};
	67
2440946c SH	68	gic: interrupt-controller@ad1000 {
	69	compatible = "arm,cortex-a9-gic";
	70	reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
	71	interrupt-controller;
	72	#interrupt-cells = <3>;
	73	};
	74
	75	local-timer@ad0600 {
	76	compatible = "arm,cortex-a9-twd-timer";
	77	reg = <0xad0600 0x20>;
	78	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
36601dbf	79	clocks = <&chip CLKID_TWD>;
2440946c SH	80	};
2440946c SH	81
ae01f64b SH	82	eth1: ethernet@b90000 {
	83	compatible = "marvell,pxa168-eth";
	84	reg = <0xb90000 0x10000>;
	85	clocks = <&chip CLKID_GETH1>;
	86	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	87	/* set by bootloader */
	88	local-mac-address = [00 00 00 00 00 00];
	89	#address-cells = <1>;
	90	#size-cells = <0>;
	91	phy-connection-type = "mii";
	92	phy-handle = <&ethphy1>;
	93	status = "disabled";
	94
	95	ethphy1: ethernet-phy@0 {
	96	reg = <0>;
	97	};
	98	};
	99
460d02ac AT	100	cpu-ctrl@dd0000 {
	101	compatible = "marvell,berlin-cpu-ctrl";
	102	reg = <0xdd0000 0x10000>;
	103	};
	104
ae01f64b SH	105	eth0: ethernet@e50000 {
	106	compatible = "marvell,pxa168-eth";
	107	reg = <0xe50000 0x10000>;
	108	clocks = <&chip CLKID_GETH0>;
	109	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	110	/* set by bootloader */
	111	local-mac-address = [00 00 00 00 00 00];
	112	#address-cells = <1>;
	113	#size-cells = <0>;
	114	phy-connection-type = "mii";
	115	phy-handle = <&ethphy0>;
	116	status = "disabled";
	117
	118	ethphy0: ethernet-phy@0 {
	119	reg = <0>;
	120	};
	121	};
	122
2440946c SH	123	apb@e80000 {
	124	compatible = "simple-bus";
	125	#address-cells = <1>;
	126	#size-cells = <1>;
	127
	128	ranges = <0 0xe80000 0x10000>;
	129	interrupt-parent = <&aic>;
	130
6d3da018 AT	131	gpio0: gpio@0400 {
	132	compatible = "snps,dw-apb-gpio";
	133	reg = <0x0400 0x400>;
	134	#address-cells = <1>;
	135	#size-cells = <0>;
	136
	137	porta: gpio-port@0 {
	138	compatible = "snps,dw-apb-gpio-port";
	139	gpio-controller;
	140	#gpio-cells = <2>;
	141	snps,nr-gpios = <8>;
	142	reg = <0>;
	143	interrupt-controller;
	144	#interrupt-cells = <2>;
	145	interrupts = <0>;
	146	};
	147	};
	148
	149	gpio1: gpio@0800 {
	150	compatible = "snps,dw-apb-gpio";
	151	reg = <0x0800 0x400>;
	152	#address-cells = <1>;
	153	#size-cells = <0>;
	154
	155	portb: gpio-port@1 {
	156	compatible = "snps,dw-apb-gpio-port";
	157	gpio-controller;
	158	#gpio-cells = <2>;
	159	snps,nr-gpios = <8>;
	160	reg = <0>;
	161	interrupt-controller;
	162	#interrupt-cells = <2>;
	163	interrupts = <1>;
	164	};
	165	};
	166
	167	gpio2: gpio@0c00 {
	168	compatible = "snps,dw-apb-gpio";
	169	reg = <0x0c00 0x400>;
	170	#address-cells = <1>;
	171	#size-cells = <0>;
	172
	173	portc: gpio-port@2 {
	174	compatible = "snps,dw-apb-gpio-port";
	175	gpio-controller;
	176	#gpio-cells = <2>;
	177	snps,nr-gpios = <8>;
	178	reg = <0>;
	179	interrupt-controller;
	180	#interrupt-cells = <2>;
	181	interrupts = <2>;
	182	};
	183	};
	184
	185	gpio3: gpio@1000 {
	186	compatible = "snps,dw-apb-gpio";
	187	reg = <0x1000 0x400>;
	188	#address-cells = <1>;
	189	#size-cells = <0>;
	190
	191	portd: gpio-port@3 {
	192	compatible = "snps,dw-apb-gpio-port";
	193	gpio-controller;
	194	#gpio-cells = <2>;
195	snps,nr-gpios = <8>;
196	reg = <0>;
197	interrupt-controller;
198	#interrupt-cells = <2>;
199	interrupts = <3>;
200	};
201	};
202
2440946c SH	203	timer0: timer@2c00 {
	204	compatible = "snps,dw-apb-timer";
	205	reg = <0x2c00 0x14>;
	206	interrupts = <8>;
36601dbf	207	clocks = <&chip CLKID_CFG>;
2440946c SH	208	clock-names = "timer";
	209	status = "okay";
	210	};
	211
	212	timer1: timer@2c14 {
	213	compatible = "snps,dw-apb-timer";
	214	reg = <0x2c14 0x14>;
	215	interrupts = <9>;
36601dbf	216	clocks = <&chip CLKID_CFG>;
2440946c SH	217	clock-names = "timer";
	218	status = "okay";
	219	};
	220
	221	timer2: timer@2c28 {
	222	compatible = "snps,dw-apb-timer";
	223	reg = <0x2c28 0x14>;
	224	interrupts = <10>;
36601dbf	225	clocks = <&chip CLKID_CFG>;
2440946c SH	226	clock-names = "timer";
	227	status = "disabled";
	228	};
	229
	230	timer3: timer@2c3c {
	231	compatible = "snps,dw-apb-timer";
	232	reg = <0x2c3c 0x14>;
	233	interrupts = <11>;
36601dbf	234	clocks = <&chip CLKID_CFG>;
2440946c SH	235	clock-names = "timer";
	236	status = "disabled";
	237	};
	238
	239	timer4: timer@2c50 {
	240	compatible = "snps,dw-apb-timer";
	241	reg = <0x2c50 0x14>;
	242	interrupts = <12>;
36601dbf	243	clocks = <&chip CLKID_CFG>;
2440946c SH	244	clock-names = "timer";
	245	status = "disabled";
	246	};
	247
	248	timer5: timer@2c64 {
	249	compatible = "snps,dw-apb-timer";
	250	reg = <0x2c64 0x14>;
	251	interrupts = <13>;
36601dbf	252	clocks = <&chip CLKID_CFG>;
2440946c SH	253	clock-names = "timer";
	254	status = "disabled";
	255	};
	256
	257	timer6: timer@2c78 {
	258	compatible = "snps,dw-apb-timer";
	259	reg = <0x2c78 0x14>;
	260	interrupts = <14>;
36601dbf	261	clocks = <&chip CLKID_CFG>;
2440946c SH	262	clock-names = "timer";
	263	status = "disabled";
	264	};
	265
	266	timer7: timer@2c8c {
	267	compatible = "snps,dw-apb-timer";
	268	reg = <0x2c8c 0x14>;
	269	interrupts = <15>;
36601dbf	270	clocks = <&chip CLKID_CFG>;
2440946c SH	271	clock-names = "timer";
	272	status = "disabled";
	273	};
	274
	275	aic: interrupt-controller@3000 {
	276	compatible = "snps,dw-apb-ictl";
	277	reg = <0x3000 0xc00>;
	278	interrupt-controller;
	279	#interrupt-cells = <1>;
	280	interrupt-parent = <&gic>;
	281	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	282	};
	283	};
	284
36601dbf SH	285	chip: chip-control@ea0000 {
	286	compatible = "marvell,berlin2-chip-ctrl";
	287	#clock-cells = <1>;
1e27a261	288	#reset-cells = <2>;
36601dbf SH	289	reg = <0xea0000 0x400>;
	290	clocks = <&refclk>;
	291	clock-names = "refclk";
0bd4b346 SH	292	};
0bd4b346 SH	293
2440946c SH	294	apb@fc0000 {
	295	compatible = "simple-bus";
	296	#address-cells = <1>;
	297	#size-cells = <1>;
	298
	299	ranges = <0 0xfc0000 0x10000>;
	300	interrupt-parent = <&sic>;
	301
6d3da018 AT	302	sm_gpio1: gpio@5000 {
	303	compatible = "snps,dw-apb-gpio";
	304	reg = <0x5000 0x400>;
	305	#address-cells = <1>;
	306	#size-cells = <0>;
	307
	308	portf: gpio-port@5 {
	309	compatible = "snps,dw-apb-gpio-port";
	310	gpio-controller;
	311	#gpio-cells = <2>;
	312	snps,nr-gpios = <8>;
	313	reg = <0>;
	314	};
	315	};
	316
	317	sm_gpio0: gpio@c000 {
	318	compatible = "snps,dw-apb-gpio";
	319	reg = <0xc000 0x400>;
	320	#address-cells = <1>;
	321	#size-cells = <0>;
	322
	323	porte: gpio-port@4 {
	324	compatible = "snps,dw-apb-gpio-port";
	325	gpio-controller;
	326	#gpio-cells = <2>;
	327	snps,nr-gpios = <8>;
	328	reg = <0>;
	329	interrupt-controller;
	330	#interrupt-cells = <2>;
	331	interrupts = <11>;
	332	};
	333	};
	334
2440946c SH	335	uart0: serial@9000 {
	336	compatible = "snps,dw-apb-uart";
	337	reg = <0x9000 0x100>;
	338	reg-shift = <2>;
	339	reg-io-width = <1>;
	340	interrupts = <8>;
36601dbf	341	clocks = <&refclk>;
50cc24ff AT	342	pinctrl-0 = <&uart0_pmux>;
50cc24ff AT	343	pinctrl-names = "default";
2440946c SH	344	status = "disabled";
	345	};
	346
	347	uart1: serial@a000 {
	348	compatible = "snps,dw-apb-uart";
	349	reg = <0xa000 0x100>;
	350	reg-shift = <2>;
	351	reg-io-width = <1>;
	352	interrupts = <9>;
36601dbf	353	clocks = <&refclk>;
50cc24ff AT	354	pinctrl-0 = <&uart1_pmux>;
50cc24ff AT	355	pinctrl-names = "default";
2440946c SH	356	status = "disabled";
	357	};
	358
	359	uart2: serial@b000 {
	360	compatible = "snps,dw-apb-uart";
	361	reg = <0xb000 0x100>;
	362	reg-shift = <2>;
	363	reg-io-width = <1>;
	364	interrupts = <10>;
36601dbf	365	clocks = <&refclk>;
50cc24ff AT	366	pinctrl-0 = <&uart2_pmux>;
50cc24ff AT	367	pinctrl-names = "default";
2440946c SH	368	status = "disabled";
	369	};
	370
50cc24ff AT	371	sysctrl: system-controller@d000 {
	372	compatible = "marvell,berlin2-system-ctrl";
	373	reg = <0xd000 0x100>;
	374
	375	uart0_pmux: uart0-pmux {
	376	groups = "GSM4";
	377	function = "uart0";
	378	};
	379
	380	uart1_pmux: uart1-pmux {
	381	groups = "GSM5";
	382	function = "uart1";
	383	};
	384
	385	uart2_pmux: uart2-pmux {
	386	groups = "GSM3";
	387	function = "uart2";
	388	};
	389	};
	390
2440946c SH	391	sic: interrupt-controller@e000 {
	392	compatible = "snps,dw-apb-ictl";
	393	reg = <0xe000 0x400>;
	394	interrupt-controller;
	395	#interrupt-cells = <1>;
	396	interrupt-parent = <&gic>;
	397	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	398	};
	399	};
	400	};
	401	};