[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / berlin2.dtsi

/*
 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * based on GPL'ed 2.6 kernel sources
 *  (c) Marvell International Ltd.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500 (BG2) SoC";
	compatible = "marvell,berlin2", "marvell,berlin";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};

		cpu@1 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;
		};
	};

	clocks {
		smclk: sysmgr-clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		cfgclk: cfg-clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <100000000>;
		};

		sysclk: system-clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <400000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;

		ranges = <0 0xf7000000 0x1000000>;

		l2: l2-cache-controller@ac0000 {
			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysclk>;
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				interrupts = <8>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "okay";
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				interrupts = <9>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "okay";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				interrupts = <10>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				interrupts = <11>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				interrupts = <12>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				interrupts = <13>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				interrupts = <14>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				interrupts = <15>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3000 0xc00>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		generic-regs@ea0184 {
			compatible = "marvell,berlin-generic-regs", "syscon";
			reg = <0xea0184 0x10>;
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			uart0: serial@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <8>;
				clocks = <&smclk>;
				status = "disabled";
			};

			uart1: serial@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <9>;
				clocks = <&smclk>;
				status = "disabled";
			};

			uart2: serial@b000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xb000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <10>;
				clocks = <&smclk>;
				status = "disabled";
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x400>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
2440946c SH	1	/*
	2	* Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
	3	*
	4	* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
	5	*
	6	* based on GPL'ed 2.6 kernel sources
	7	* (c) Marvell International Ltd.
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include "skeleton.dtsi"
	15	#include <dt-bindings/interrupt-controller/arm-gic.h>
	16
	17	/ {
	18	model = "Marvell Armada 1500 (BG2) SoC";
	19	compatible = "marvell,berlin2", "marvell,berlin";
	20
	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	cpu@0 {
	26	compatible = "marvell,pj4b";
	27	device_type = "cpu";
	28	next-level-cache = <&l2>;
	29	reg = <0>;
	30	};
	31
	32	cpu@1 {
	33	compatible = "marvell,pj4b";
	34	device_type = "cpu";
	35	next-level-cache = <&l2>;
	36	reg = <1>;
	37	};
	38	};
	39
	40	clocks {
	41	smclk: sysmgr-clock {
	42	compatible = "fixed-clock";
	43	#clock-cells = <0>;
	44	clock-frequency = <25000000>;
	45	};
	46
	47	cfgclk: cfg-clock {
	48	compatible = "fixed-clock";
	49	#clock-cells = <0>;
	50	clock-frequency = <100000000>;
	51	};
	52
	53	sysclk: system-clock {
	54	compatible = "fixed-clock";
	55	#clock-cells = <0>;
	56	clock-frequency = <400000000>;
	57	};
	58	};
	59
	60	soc {
	61	compatible = "simple-bus";
	62	#address-cells = <1>;
	63	#size-cells = <1>;
	64	interrupt-parent = <&gic>;
65
66	ranges = <0 0xf7000000 0x1000000>;
67
68	l2: l2-cache-controller@ac0000 {
69	compatible = "marvell,tauros3-cache", "arm,pl310-cache";
70	reg = <0xac0000 0x1000>;
71	cache-unified;
72	cache-level = <2>;
73	};
74
0bd4b346 SH	75	scu: snoop-control-unit@ad0000 {
	76	compatible = "arm,cortex-a9-scu";
	77	reg = <0xad0000 0x58>;
	78	};
	79
2440946c SH	80	gic: interrupt-controller@ad1000 {
	81	compatible = "arm,cortex-a9-gic";
	82	reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
	83	interrupt-controller;
	84	#interrupt-cells = <3>;
	85	};
	86
	87	local-timer@ad0600 {
	88	compatible = "arm,cortex-a9-twd-timer";
	89	reg = <0xad0600 0x20>;
	90	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
	91	clocks = <&sysclk>;
	92	};
	93
	94	apb@e80000 {
	95	compatible = "simple-bus";
	96	#address-cells = <1>;
	97	#size-cells = <1>;
	98
	99	ranges = <0 0xe80000 0x10000>;
	100	interrupt-parent = <&aic>;
	101
	102	timer0: timer@2c00 {
	103	compatible = "snps,dw-apb-timer";
	104	reg = <0x2c00 0x14>;
	105	interrupts = <8>;
	106	clocks = <&cfgclk>;
	107	clock-names = "timer";
	108	status = "okay";
	109	};
	110
	111	timer1: timer@2c14 {
	112	compatible = "snps,dw-apb-timer";
	113	reg = <0x2c14 0x14>;
	114	interrupts = <9>;
	115	clocks = <&cfgclk>;
	116	clock-names = "timer";
	117	status = "okay";
	118	};
	119
	120	timer2: timer@2c28 {
	121	compatible = "snps,dw-apb-timer";
	122	reg = <0x2c28 0x14>;
	123	interrupts = <10>;
	124	clocks = <&cfgclk>;
	125	clock-names = "timer";
	126	status = "disabled";
	127	};
	128
	129	timer3: timer@2c3c {
	130	compatible = "snps,dw-apb-timer";
	131	reg = <0x2c3c 0x14>;
	132	interrupts = <11>;
	133	clocks = <&cfgclk>;
	134	clock-names = "timer";
	135	status = "disabled";
	136	};
	137
	138	timer4: timer@2c50 {
	139	compatible = "snps,dw-apb-timer";
	140	reg = <0x2c50 0x14>;
	141	interrupts = <12>;
	142	clocks = <&cfgclk>;
	143	clock-names = "timer";
144	status = "disabled";
145	};
146
147	timer5: timer@2c64 {
148	compatible = "snps,dw-apb-timer";
149	reg = <0x2c64 0x14>;
150	interrupts = <13>;
151	clocks = <&cfgclk>;
152	clock-names = "timer";
153	status = "disabled";
154	};
155
156	timer6: timer@2c78 {
157	compatible = "snps,dw-apb-timer";
158	reg = <0x2c78 0x14>;
159	interrupts = <14>;
160	clocks = <&cfgclk>;
161	clock-names = "timer";
162	status = "disabled";
163	};
164
165	timer7: timer@2c8c {
166	compatible = "snps,dw-apb-timer";
167	reg = <0x2c8c 0x14>;
168	interrupts = <15>;
169	clocks = <&cfgclk>;
170	clock-names = "timer";
171	status = "disabled";
172	};
173
174	aic: interrupt-controller@3000 {
175	compatible = "snps,dw-apb-ictl";
176	reg = <0x3000 0xc00>;
177	interrupt-controller;
178	#interrupt-cells = <1>;
179	interrupt-parent = <&gic>;
180	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
181	};
182	};
183
0bd4b346 SH	184	generic-regs@ea0184 {
	185	compatible = "marvell,berlin-generic-regs", "syscon";
	186	reg = <0xea0184 0x10>;
	187	};
	188
2440946c SH	189	apb@fc0000 {
	190	compatible = "simple-bus";
	191	#address-cells = <1>;
	192	#size-cells = <1>;
	193
	194	ranges = <0 0xfc0000 0x10000>;
	195	interrupt-parent = <&sic>;
	196
	197	uart0: serial@9000 {
	198	compatible = "snps,dw-apb-uart";
	199	reg = <0x9000 0x100>;
	200	reg-shift = <2>;
	201	reg-io-width = <1>;
	202	interrupts = <8>;
	203	clocks = <&smclk>;
	204	status = "disabled";
	205	};
	206
	207	uart1: serial@a000 {
	208	compatible = "snps,dw-apb-uart";
	209	reg = <0xa000 0x100>;
	210	reg-shift = <2>;
	211	reg-io-width = <1>;
	212	interrupts = <9>;
	213	clocks = <&smclk>;
	214	status = "disabled";
	215	};
	216
	217	uart2: serial@b000 {
	218	compatible = "snps,dw-apb-uart";
	219	reg = <0xb000 0x100>;
	220	reg-shift = <2>;
	221	reg-io-width = <1>;
	222	interrupts = <10>;
	223	clocks = <&smclk>;
	224	status = "disabled";
	225	};
	226
	227	sic: interrupt-controller@e000 {
	228	compatible = "snps,dw-apb-ictl";
	229	reg = <0xe000 0x400>;
	230	interrupt-controller;
	231	#interrupt-cells = <1>;
	232	interrupt-parent = <&gic>;
	233	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	234	};
	235	};
	236	};
	237	};