[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / berlin2cd.dtsi

/*
 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * based on GPL'ed 2.6 kernel sources
 *  (c) Marvell International Ltd.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include "skeleton.dtsi"
#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500-mini (BG2CD) SoC";
	compatible = "marvell,berlin2cd", "marvell,berlin";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;

		ranges = <0 0xf7000000 0x1000000>;

		pmu {
			compatible = "arm,cortex-a9-pmu";
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		};

		sdhci0: sdhci@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		l2: l2-cache-controller@ac0000 {
			compatible = "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&chip CLKID_TWD>;
		};

		usb_phy0: usb-phy@b74000 {
			compatible = "marvell,berlin2cd-usb-phy";
			reg = <0xb74000 0x128>;
			#phy-cells = <0>;
			resets = <&chip 0x178 23>;
			status = "disabled";
		};

		usb_phy1: usb-phy@b78000 {
			compatible = "marvell,berlin2cd-usb-phy";
			reg = <0xb78000 0x128>;
			#phy-cells = <0>;
			resets = <&chip 0x178 24>;
			status = "disabled";
		};

		eth1: ethernet@b90000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xb90000 0x10000>;
			clocks = <&chip CLKID_GETH1>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy1>;
			status = "disabled";

			ethphy1: ethernet-phy@0 {
				reg = <0>;
			};
		};

		eth0: ethernet@e50000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xe50000 0x10000>;
			clocks = <&chip CLKID_GETH0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy0>;
			status = "disabled";

			ethphy0: ethernet-phy@0 {
				reg = <0>;
			};
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@0400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@0800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@0c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				interrupts = <8>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				interrupts = <9>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				interrupts = <10>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				interrupts = <11>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				interrupts = <12>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				interrupts = <13>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				interrupts = <14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				interrupts = <15>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3000 0xc00>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		chip: chip-control@ea0000 {
			compatible = "marvell,berlin2cd-chip-ctrl";
			#clock-cells = <1>;
			#reset-cells = <2>;
			reg = <0xea0000 0x400>;
			clocks = <&refclk>;
			clock-names = "refclk";

			uart0_pmux: uart0-pmux {
				groups = "G6";
				function = "uart0";
			};
		};

		usb0: usb@ed0000 {
			compatible = "chipidea,usb2";
			reg = <0xed0000 0x200>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip CLKID_USB0>;
			phys = <&usb_phy0>;
			phy-names = "usb-phy";
			status = "disabled";
		};

		usb1: usb@ee0000 {
			compatible = "chipidea,usb2";
			reg = <0xee0000 0x200>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip CLKID_USB1>;
			phys = <&usb_phy1>;
			phy-names = "usb-phy";
			status = "disabled";
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			sm_gpio1: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
				};
			};

			sm_gpio0: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
				};
			};

			uart0: serial@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <8>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: serial@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <9>;
				clocks = <&refclk>;
				status = "disabled";
			};

			sysctrl: system-controller@d000 {
				compatible = "marvell,berlin2cd-system-ctrl";
				reg = <0xd000 0x100>;
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x400>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
a9092118 SH	1	/*
	2	* Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
	3	*
	4	* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
	5	*
	6	* based on GPL'ed 2.6 kernel sources
	7	* (c) Marvell International Ltd.
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include "skeleton.dtsi"
556f4a33	15	#include <dt-bindings/clock/berlin2.h>
a9092118 SH	16	#include <dt-bindings/interrupt-controller/arm-gic.h>
	17
	18	/ {
	19	model = "Marvell Armada 1500-mini (BG2CD) SoC";
	20	compatible = "marvell,berlin2cd", "marvell,berlin";
	21
	22	cpus {
	23	#address-cells = <1>;
	24	#size-cells = <0>;
	25
	26	cpu@0 {
	27	compatible = "arm,cortex-a9";
	28	device_type = "cpu";
	29	next-level-cache = <&l2>;
	30	reg = <0>;
	31	};
	32	};
	33
556f4a33 SH	34	refclk: oscillator {
	35	compatible = "fixed-clock";
	36	#clock-cells = <0>;
	37	clock-frequency = <25000000>;
a9092118 SH	38	};
	39
	40	soc {
	41	compatible = "simple-bus";
	42	#address-cells = <1>;
	43	#size-cells = <1>;
	44	interrupt-parent = <&gic>;
	45
	46	ranges = <0 0xf7000000 0x1000000>;
	47
d4ce8042 JZ	48	pmu {
	49	compatible = "arm,cortex-a9-pmu";
	50	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	51	};
	52
652538c4 SH	53	sdhci0: sdhci@ab0000 {
	54	compatible = "mrvl,pxav3-mmc";
	55	reg = <0xab0000 0x200>;
	56	clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
	57	clock-names = "io", "core";
	58	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	59	status = "disabled";
	60	};
	61
a9092118 SH	62	l2: l2-cache-controller@ac0000 {
	63	compatible = "arm,pl310-cache";
	64	reg = <0xac0000 0x1000>;
	65	cache-unified;
	66	cache-level = <2>;
	67	};
	68
	69	gic: interrupt-controller@ad1000 {
	70	compatible = "arm,cortex-a9-gic";
	71	reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
	72	interrupt-controller;
	73	#interrupt-cells = <3>;
	74	};
	75
	76	local-timer@ad0600 {
	77	compatible = "arm,cortex-a9-twd-timer";
	78	reg = <0xad0600 0x20>;
2356d2f3	79	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>;
556f4a33	80	clocks = <&chip CLKID_TWD>;
a9092118 SH	81	};
a9092118 SH	82
e802b3a2 SH	83	usb_phy0: usb-phy@b74000 {
	84	compatible = "marvell,berlin2cd-usb-phy";
	85	reg = <0xb74000 0x128>;
	86	#phy-cells = <0>;
	87	resets = <&chip 0x178 23>;
	88	status = "disabled";
	89	};
	90
	91	usb_phy1: usb-phy@b78000 {
	92	compatible = "marvell,berlin2cd-usb-phy";
	93	reg = <0xb78000 0x128>;
	94	#phy-cells = <0>;
	95	resets = <&chip 0x178 24>;
	96	status = "disabled";
	97	};
	98
631338af SH	99	eth1: ethernet@b90000 {
	100	compatible = "marvell,pxa168-eth";
	101	reg = <0xb90000 0x10000>;
	102	clocks = <&chip CLKID_GETH1>;
	103	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	104	/* set by bootloader */
	105	local-mac-address = [00 00 00 00 00 00];
	106	#address-cells = <1>;
	107	#size-cells = <0>;
	108	phy-connection-type = "mii";
	109	phy-handle = <&ethphy1>;
	110	status = "disabled";
	111
	112	ethphy1: ethernet-phy@0 {
	113	reg = <0>;
	114	};
	115	};
	116
	117	eth0: ethernet@e50000 {
	118	compatible = "marvell,pxa168-eth";
	119	reg = <0xe50000 0x10000>;
	120	clocks = <&chip CLKID_GETH0>;
	121	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	122	/* set by bootloader */
	123	local-mac-address = [00 00 00 00 00 00];
	124	#address-cells = <1>;
	125	#size-cells = <0>;
	126	phy-connection-type = "mii";
	127	phy-handle = <&ethphy0>;
	128	status = "disabled";
	129
	130	ethphy0: ethernet-phy@0 {
	131	reg = <0>;
	132	};
	133	};
	134
a9092118 SH	135	apb@e80000 {
	136	compatible = "simple-bus";
	137	#address-cells = <1>;
	138	#size-cells = <1>;
	139
	140	ranges = <0 0xe80000 0x10000>;
	141	interrupt-parent = <&aic>;
	142
c920a669 AT	143	gpio0: gpio@0400 {
	144	compatible = "snps,dw-apb-gpio";
	145	reg = <0x0400 0x400>;
	146	#address-cells = <1>;
	147	#size-cells = <0>;
	148
	149	porta: gpio-port@0 {
	150	compatible = "snps,dw-apb-gpio-port";
	151	gpio-controller;
	152	#gpio-cells = <2>;
	153	snps,nr-gpios = <8>;
	154	reg = <0>;
	155	interrupt-controller;
	156	#interrupt-cells = <2>;
	157	interrupts = <0>;
	158	};
	159	};
	160
	161	gpio1: gpio@0800 {
	162	compatible = "snps,dw-apb-gpio";
	163	reg = <0x0800 0x400>;
	164	#address-cells = <1>;
	165	#size-cells = <0>;
	166
	167	portb: gpio-port@1 {
	168	compatible = "snps,dw-apb-gpio-port";
	169	gpio-controller;
	170	#gpio-cells = <2>;
	171	snps,nr-gpios = <8>;
	172	reg = <0>;
	173	interrupt-controller;
	174	#interrupt-cells = <2>;
	175	interrupts = <1>;
	176	};
	177	};
	178
	179	gpio2: gpio@0c00 {
	180	compatible = "snps,dw-apb-gpio";
	181	reg = <0x0c00 0x400>;
	182	#address-cells = <1>;
	183	#size-cells = <0>;
	184
	185	portc: gpio-port@2 {
	186	compatible = "snps,dw-apb-gpio-port";
	187	gpio-controller;
	188	#gpio-cells = <2>;
	189	snps,nr-gpios = <8>;
	190	reg = <0>;
	191	interrupt-controller;
	192	#interrupt-cells = <2>;
	193	interrupts = <2>;
	194	};
	195	};
	196
	197	gpio3: gpio@1000 {
	198	compatible = "snps,dw-apb-gpio";
	199	reg = <0x1000 0x400>;
	200	#address-cells = <1>;
	201	#size-cells = <0>;
	202
	203	portd: gpio-port@3 {
	204	compatible = "snps,dw-apb-gpio-port";
	205	gpio-controller;
	206	#gpio-cells = <2>;
207	snps,nr-gpios = <8>;
208	reg = <0>;
209	interrupt-controller;
210	#interrupt-cells = <2>;
211	interrupts = <3>;
212	};
213	};
214
a9092118 SH	215	timer0: timer@2c00 {
	216	compatible = "snps,dw-apb-timer";
	217	reg = <0x2c00 0x14>;
	218	interrupts = <8>;
556f4a33	219	clocks = <&chip CLKID_CFG>;
a9092118 SH	220	clock-names = "timer";
	221	status = "okay";
	222	};
	223
	224	timer1: timer@2c14 {
	225	compatible = "snps,dw-apb-timer";
	226	reg = <0x2c14 0x14>;
	227	interrupts = <9>;
556f4a33	228	clocks = <&chip CLKID_CFG>;
a9092118 SH	229	clock-names = "timer";
	230	status = "okay";
	231	};
	232
	233	timer2: timer@2c28 {
	234	compatible = "snps,dw-apb-timer";
	235	reg = <0x2c28 0x14>;
	236	interrupts = <10>;
556f4a33	237	clocks = <&chip CLKID_CFG>;
a9092118 SH	238	clock-names = "timer";
	239	status = "disabled";
	240	};
	241
	242	timer3: timer@2c3c {
	243	compatible = "snps,dw-apb-timer";
	244	reg = <0x2c3c 0x14>;
	245	interrupts = <11>;
556f4a33	246	clocks = <&chip CLKID_CFG>;
a9092118 SH	247	clock-names = "timer";
	248	status = "disabled";
	249	};
	250
	251	timer4: timer@2c50 {
	252	compatible = "snps,dw-apb-timer";
	253	reg = <0x2c50 0x14>;
	254	interrupts = <12>;
556f4a33	255	clocks = <&chip CLKID_CFG>;
a9092118 SH	256	clock-names = "timer";
	257	status = "disabled";
	258	};
	259
	260	timer5: timer@2c64 {
	261	compatible = "snps,dw-apb-timer";
	262	reg = <0x2c64 0x14>;
	263	interrupts = <13>;
556f4a33	264	clocks = <&chip CLKID_CFG>;
a9092118 SH	265	clock-names = "timer";
	266	status = "disabled";
	267	};
	268
	269	timer6: timer@2c78 {
	270	compatible = "snps,dw-apb-timer";
	271	reg = <0x2c78 0x14>;
	272	interrupts = <14>;
556f4a33	273	clocks = <&chip CLKID_CFG>;
a9092118 SH	274	clock-names = "timer";
	275	status = "disabled";
	276	};
	277
	278	timer7: timer@2c8c {
	279	compatible = "snps,dw-apb-timer";
	280	reg = <0x2c8c 0x14>;
	281	interrupts = <15>;
556f4a33	282	clocks = <&chip CLKID_CFG>;
a9092118 SH	283	clock-names = "timer";
	284	status = "disabled";
	285	};
	286
	287	aic: interrupt-controller@3000 {
	288	compatible = "snps,dw-apb-ictl";
	289	reg = <0x3000 0xc00>;
	290	interrupt-controller;
	291	#interrupt-cells = <1>;
	292	interrupt-parent = <&gic>;
	293	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	294	};
	295	};
	296
556f4a33 SH	297	chip: chip-control@ea0000 {
	298	compatible = "marvell,berlin2cd-chip-ctrl";
	299	#clock-cells = <1>;
1e27a261	300	#reset-cells = <2>;
556f4a33 SH	301	reg = <0xea0000 0x400>;
	302	clocks = <&refclk>;
	303	clock-names = "refclk";
50cc24ff AT	304
	305	uart0_pmux: uart0-pmux {
	306	groups = "G6";
	307	function = "uart0";
	308	};
556f4a33 SH	309	};
556f4a33 SH	310
e802b3a2 SH	311	usb0: usb@ed0000 {
	312	compatible = "chipidea,usb2";
	313	reg = <0xed0000 0x200>;
	314	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	315	clocks = <&chip CLKID_USB0>;
	316	phys = <&usb_phy0>;
	317	phy-names = "usb-phy";
	318	status = "disabled";
	319	};
	320
	321	usb1: usb@ee0000 {
	322	compatible = "chipidea,usb2";
	323	reg = <0xee0000 0x200>;
	324	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	325	clocks = <&chip CLKID_USB1>;
	326	phys = <&usb_phy1>;
	327	phy-names = "usb-phy";
	328	status = "disabled";
	329	};
	330
a9092118 SH	331	apb@fc0000 {
	332	compatible = "simple-bus";
	333	#address-cells = <1>;
	334	#size-cells = <1>;
	335
	336	ranges = <0 0xfc0000 0x10000>;
	337	interrupt-parent = <&sic>;
	338
c920a669 AT	339	sm_gpio1: gpio@5000 {
	340	compatible = "snps,dw-apb-gpio";
	341	reg = <0x5000 0x400>;
	342	#address-cells = <1>;
	343	#size-cells = <0>;
	344
	345	portf: gpio-port@5 {
	346	compatible = "snps,dw-apb-gpio-port";
	347	gpio-controller;
	348	#gpio-cells = <2>;
	349	snps,nr-gpios = <8>;
	350	reg = <0>;
	351	};
	352	};
	353
	354	sm_gpio0: gpio@c000 {
	355	compatible = "snps,dw-apb-gpio";
	356	reg = <0xc000 0x400>;
	357	#address-cells = <1>;
	358	#size-cells = <0>;
	359
	360	porte: gpio-port@4 {
	361	compatible = "snps,dw-apb-gpio-port";
	362	gpio-controller;
	363	#gpio-cells = <2>;
	364	snps,nr-gpios = <8>;
	365	reg = <0>;
	366	};
	367	};
	368
a9092118 SH	369	uart0: serial@9000 {
	370	compatible = "snps,dw-apb-uart";
	371	reg = <0x9000 0x100>;
	372	reg-shift = <2>;
	373	reg-io-width = <1>;
	374	interrupts = <8>;
556f4a33	375	clocks = <&refclk>;
50cc24ff AT	376	pinctrl-0 = <&uart0_pmux>;
50cc24ff AT	377	pinctrl-names = "default";
a9092118 SH	378	status = "disabled";
	379	};
	380
	381	uart1: serial@a000 {
	382	compatible = "snps,dw-apb-uart";
	383	reg = <0xa000 0x100>;
	384	reg-shift = <2>;
	385	reg-io-width = <1>;
	386	interrupts = <9>;
556f4a33	387	clocks = <&refclk>;
a9092118 SH	388	status = "disabled";
	389	};
	390
50cc24ff AT	391	sysctrl: system-controller@d000 {
	392	compatible = "marvell,berlin2cd-system-ctrl";
	393	reg = <0xd000 0x100>;
	394	};
	395
a9092118 SH	396	sic: interrupt-controller@e000 {
	397	compatible = "snps,dw-apb-ictl";
	398	reg = <0xe000 0x400>;
	399	interrupt-controller;
	400	#interrupt-cells = <1>;
	401	interrupt-parent = <&gic>;
	402	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	403	};
	404	};
	405	};
	406	};