[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / berlin2cd.dtsi

/*
 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * based on GPL'ed 2.6 kernel sources
 *  (c) Marvell International Ltd.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500-mini (BG2CD) SoC";
	compatible = "marvell,berlin2cd", "marvell,berlin";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};
	};

	clocks {
		smclk: sysmgr-clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		cfgclk: cfg-clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <75000000>;
		};

		sysclk: system-clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <300000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;

		ranges = <0 0xf7000000 0x1000000>;

		l2: l2-cache-controller@ac0000 {
			compatible = "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysclk>;
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				interrupts = <8>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "okay";
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				interrupts = <9>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "okay";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				interrupts = <10>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				interrupts = <11>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				interrupts = <12>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				interrupts = <13>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				interrupts = <14>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				interrupts = <15>;
				clocks = <&cfgclk>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3000 0xc00>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			uart0: serial@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <8>;
				clocks = <&smclk>;
				status = "disabled";
			};

			uart1: serial@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <9>;
				clocks = <&smclk>;
				status = "disabled";
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x400>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
a9092118 SH	1	/*
	2	* Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
	3	*
	4	* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
	5	*
	6	* based on GPL'ed 2.6 kernel sources
	7	* (c) Marvell International Ltd.
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include "skeleton.dtsi"
	15	#include <dt-bindings/interrupt-controller/arm-gic.h>
	16
	17	/ {
	18	model = "Marvell Armada 1500-mini (BG2CD) SoC";
	19	compatible = "marvell,berlin2cd", "marvell,berlin";
	20
	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	cpu@0 {
	26	compatible = "arm,cortex-a9";
	27	device_type = "cpu";
	28	next-level-cache = <&l2>;
	29	reg = <0>;
	30	};
	31	};
	32
	33	clocks {
	34	smclk: sysmgr-clock {
	35	compatible = "fixed-clock";
	36	#clock-cells = <0>;
	37	clock-frequency = <25000000>;
	38	};
	39
	40	cfgclk: cfg-clock {
	41	compatible = "fixed-clock";
	42	#clock-cells = <0>;
	43	clock-frequency = <75000000>;
	44	};
	45
	46	sysclk: system-clock {
	47	compatible = "fixed-clock";
	48	#clock-cells = <0>;
	49	clock-frequency = <300000000>;
	50	};
	51	};
	52
	53	soc {
	54	compatible = "simple-bus";
	55	#address-cells = <1>;
	56	#size-cells = <1>;
	57	interrupt-parent = <&gic>;
	58
	59	ranges = <0 0xf7000000 0x1000000>;
	60
	61	l2: l2-cache-controller@ac0000 {
	62	compatible = "arm,pl310-cache";
	63	reg = <0xac0000 0x1000>;
	64	cache-unified;
65	cache-level = <2>;
66	};
67
68	gic: interrupt-controller@ad1000 {
69	compatible = "arm,cortex-a9-gic";
70	reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
71	interrupt-controller;
72	#interrupt-cells = <3>;
73	};
74
75	local-timer@ad0600 {
76	compatible = "arm,cortex-a9-twd-timer";
77	reg = <0xad0600 0x20>;
78	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
79	clocks = <&sysclk>;
80	};
81
82	apb@e80000 {
83	compatible = "simple-bus";
84	#address-cells = <1>;
85	#size-cells = <1>;
86
87	ranges = <0 0xe80000 0x10000>;
88	interrupt-parent = <&aic>;
89
90	timer0: timer@2c00 {
91	compatible = "snps,dw-apb-timer";
92	reg = <0x2c00 0x14>;
93	interrupts = <8>;
94	clocks = <&cfgclk>;
95	clock-names = "timer";
96	status = "okay";
97	};
98
99	timer1: timer@2c14 {
100	compatible = "snps,dw-apb-timer";
101	reg = <0x2c14 0x14>;
102	interrupts = <9>;
103	clocks = <&cfgclk>;
104	clock-names = "timer";
105	status = "okay";
106	};
107
108	timer2: timer@2c28 {
109	compatible = "snps,dw-apb-timer";
110	reg = <0x2c28 0x14>;
111	interrupts = <10>;
112	clocks = <&cfgclk>;
113	clock-names = "timer";
114	status = "disabled";
115	};
116
117	timer3: timer@2c3c {
118	compatible = "snps,dw-apb-timer";
119	reg = <0x2c3c 0x14>;
120	interrupts = <11>;
121	clocks = <&cfgclk>;
122	clock-names = "timer";
123	status = "disabled";
124	};
125
126	timer4: timer@2c50 {
127	compatible = "snps,dw-apb-timer";
128	reg = <0x2c50 0x14>;
129	interrupts = <12>;
130	clocks = <&cfgclk>;
131	clock-names = "timer";
132	status = "disabled";
133	};
134
135	timer5: timer@2c64 {
136	compatible = "snps,dw-apb-timer";
137	reg = <0x2c64 0x14>;
138	interrupts = <13>;
139	clocks = <&cfgclk>;
140	clock-names = "timer";
141	status = "disabled";
142	};
143
144	timer6: timer@2c78 {
145	compatible = "snps,dw-apb-timer";
146	reg = <0x2c78 0x14>;
147	interrupts = <14>;
148	clocks = <&cfgclk>;
149	clock-names = "timer";
150	status = "disabled";
151	};
152
153	timer7: timer@2c8c {
154	compatible = "snps,dw-apb-timer";
155	reg = <0x2c8c 0x14>;
156	interrupts = <15>;
157	clocks = <&cfgclk>;
158	clock-names = "timer";
159	status = "disabled";
160	};
161
162	aic: interrupt-controller@3000 {
163	compatible = "snps,dw-apb-ictl";
164	reg = <0x3000 0xc00>;
165	interrupt-controller;
166	#interrupt-cells = <1>;
167	interrupt-parent = <&gic>;
168	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
169	};
170	};
171
172	apb@fc0000 {
173	compatible = "simple-bus";
174	#address-cells = <1>;
175	#size-cells = <1>;
176
177	ranges = <0 0xfc0000 0x10000>;
178	interrupt-parent = <&sic>;
179
180	uart0: serial@9000 {
181	compatible = "snps,dw-apb-uart";
182	reg = <0x9000 0x100>;
183	reg-shift = <2>;
184	reg-io-width = <1>;
185	interrupts = <8>;
186	clocks = <&smclk>;
187	status = "disabled";
188	};
189
190	uart1: serial@a000 {
191	compatible = "snps,dw-apb-uart";
192	reg = <0xa000 0x100>;
193	reg-shift = <2>;
194	reg-io-width = <1>;
195	interrupts = <9>;
196	clocks = <&smclk>;
197	status = "disabled";
198	};
199
200	sic: interrupt-controller@e000 {
201	compatible = "snps,dw-apb-ictl";
202	reg = <0xe000 0x400>;
203	interrupt-controller;
204	#interrupt-cells = <1>;
205	interrupt-parent = <&gic>;
206	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
207	};
208	};
209	};
210	};