[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / berlin2q.dtsi

/*
 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <dt-bindings/clock/berlin2q.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	model = "Marvell Armada 1500 pro (BG2-Q) SoC";
	compatible = "marvell,berlin2q", "marvell,berlin";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <3>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0 0xf7000000 0x1000000>;
		interrupt-parent = <&gic>;

		sdhci0: sdhci@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip CLKID_SDIO1XIN>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci1: sdhci@ab0800 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0800 0x200>;
			clocks = <&chip CLKID_SDIO1XIN>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci2: sdhci@ab1000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab1000 0x200>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip CLKID_SDIO1XIN>;
			status = "disabled";
		};

		l2: l2-cache-controller@ac0000 {
			compatible = "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-level = <2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			clocks = <&chip CLKID_TWD>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@0400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@0800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@0c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				interrupts = <8>;
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3800 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3800 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio4: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
				};
			};

			gpio5: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
				};
			};
		};

		chip: chip-control@ea0000 {
			compatible = "marvell,berlin2q-chip-ctrl";
			#clock-cells = <1>;
			reg = <0xea0000 0x400>, <0xdd0170 0x10>;
			clocks = <&refclk>;
			clock-names = "refclk";
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			uart0: uart@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <8>;
				clocks = <&refclk>;
				reg-shift = <2>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: uart@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <9>;
				clocks = <&refclk>;
				reg-shift = <2>;
				pinctrl-0 = <&uart1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sysctrl: pin-controller@d000 {
				compatible = "marvell,berlin2q-system-ctrl";
				reg = <0xd000 0x100>;

				uart0_pmux: uart0-pmux {
					groups = "GSM12";
					function = "uart0";
				};

				uart1_pmux: uart1-pmux {
					groups = "GSM14";
					function = "uart1";
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
374ddcbf AT	1	/*
	2	* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
	3	*
	4	* This file is licensed under the terms of the GNU General Public
	5	* License version 2. This program is licensed "as is" without any
	6	* warranty of any kind, whether express or implied.
	7	*/
	8
414dcf8f	9	#include <dt-bindings/clock/berlin2q.h>
374ddcbf AT	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
	11
	12	#include "skeleton.dtsi"
	13
	14	/ {
	15	model = "Marvell Armada 1500 pro (BG2-Q) SoC";
	16	compatible = "marvell,berlin2q", "marvell,berlin";
	17
	18	cpus {
	19	#address-cells = <1>;
	20	#size-cells = <0>;
	21
	22	cpu@0 {
	23	compatible = "arm,cortex-a9";
	24	device_type = "cpu";
	25	next-level-cache = <&l2>;
	26	reg = <0>;
	27	};
	28
	29	cpu@1 {
	30	compatible = "arm,cortex-a9";
	31	device_type = "cpu";
	32	next-level-cache = <&l2>;
	33	reg = <1>;
	34	};
	35
	36	cpu@2 {
	37	compatible = "arm,cortex-a9";
	38	device_type = "cpu";
	39	next-level-cache = <&l2>;
	40	reg = <2>;
	41	};
	42
	43	cpu@3 {
	44	compatible = "arm,cortex-a9";
	45	device_type = "cpu";
	46	next-level-cache = <&l2>;
	47	reg = <3>;
	48	};
	49	};
	50
414dcf8f	51	refclk: oscillator {
374ddcbf AT	52	compatible = "fixed-clock";
	53	#clock-cells = <0>;
	54	clock-frequency = <25000000>;
	55	};
	56
374ddcbf AT	57	soc {
	58	compatible = "simple-bus";
	59	#address-cells = <1>;
	60	#size-cells = <1>;
	61
	62	ranges = <0 0xf7000000 0x1000000>;
	63	interrupt-parent = <&gic>;
	64
0d859a6a AT	65	sdhci0: sdhci@ab0000 {
	66	compatible = "mrvl,pxav3-mmc";
	67	reg = <0xab0000 0x200>;
	68	clocks = <&chip CLKID_SDIO1XIN>;
	69	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	70	status = "disabled";
	71	};
	72
	73	sdhci1: sdhci@ab0800 {
	74	compatible = "mrvl,pxav3-mmc";
	75	reg = <0xab0800 0x200>;
	76	clocks = <&chip CLKID_SDIO1XIN>;
	77	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	78	status = "disabled";
	79	};
	80
	81	sdhci2: sdhci@ab1000 {
	82	compatible = "mrvl,pxav3-mmc";
	83	reg = <0xab1000 0x200>;
	84	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	85	clocks = <&chip CLKID_SDIO1XIN>;
	86	status = "disabled";
	87	};
	88
374ddcbf AT	89	l2: l2-cache-controller@ac0000 {
	90	compatible = "arm,pl310-cache";
	91	reg = <0xac0000 0x1000>;
	92	cache-level = <2>;
	93	};
	94
0bd4b346 SH	95	scu: snoop-control-unit@ad0000 {
	96	compatible = "arm,cortex-a9-scu";
	97	reg = <0xad0000 0x58>;
	98	};
	99
374ddcbf AT	100	local-timer@ad0600 {
	101	compatible = "arm,cortex-a9-twd-timer";
	102	reg = <0xad0600 0x20>;
414dcf8f	103	clocks = <&chip CLKID_TWD>;
374ddcbf AT	104	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
	105	};
	106
	107	gic: interrupt-controller@ad1000 {
	108	compatible = "arm,cortex-a9-gic";
	109	reg = <0xad1000 0x1000>, <0xad0100 0x100>;
	110	interrupt-controller;
	111	#interrupt-cells = <3>;
	112	};
	113
	114	apb@e80000 {
	115	compatible = "simple-bus";
	116	#address-cells = <1>;
	117	#size-cells = <1>;
	118
	119	ranges = <0 0xe80000 0x10000>;
	120	interrupt-parent = <&aic>;
	121
cedf57fc AT	122	gpio0: gpio@0400 {
	123	compatible = "snps,dw-apb-gpio";
	124	reg = <0x0400 0x400>;
	125	#address-cells = <1>;
	126	#size-cells = <0>;
	127
	128	porta: gpio-port@0 {
	129	compatible = "snps,dw-apb-gpio-port";
	130	gpio-controller;
	131	#gpio-cells = <2>;
	132	snps,nr-gpios = <32>;
	133	reg = <0>;
	134	interrupt-controller;
	135	#interrupt-cells = <2>;
	136	interrupts = <0>;
	137	};
	138	};
	139
	140	gpio1: gpio@0800 {
	141	compatible = "snps,dw-apb-gpio";
	142	reg = <0x0800 0x400>;
	143	#address-cells = <1>;
	144	#size-cells = <0>;
	145
	146	portb: gpio-port@1 {
	147	compatible = "snps,dw-apb-gpio-port";
	148	gpio-controller;
	149	#gpio-cells = <2>;
	150	snps,nr-gpios = <32>;
	151	reg = <0>;
	152	interrupt-controller;
	153	#interrupt-cells = <2>;
	154	interrupts = <1>;
	155	};
	156	};
	157
	158	gpio2: gpio@0c00 {
	159	compatible = "snps,dw-apb-gpio";
	160	reg = <0x0c00 0x400>;
	161	#address-cells = <1>;
	162	#size-cells = <0>;
	163
	164	portc: gpio-port@2 {
	165	compatible = "snps,dw-apb-gpio-port";
	166	gpio-controller;
	167	#gpio-cells = <2>;
	168	snps,nr-gpios = <32>;
	169	reg = <0>;
	170	interrupt-controller;
	171	#interrupt-cells = <2>;
	172	interrupts = <2>;
	173	};
	174	};
	175
	176	gpio3: gpio@1000 {
	177	compatible = "snps,dw-apb-gpio";
	178	reg = <0x1000 0x400>;
	179	#address-cells = <1>;
	180	#size-cells = <0>;
	181
	182	portd: gpio-port@3 {
	183	compatible = "snps,dw-apb-gpio-port";
	184	gpio-controller;
	185	#gpio-cells = <2>;
186	snps,nr-gpios = <32>;
187	reg = <0>;
188	interrupt-controller;
189	#interrupt-cells = <2>;
190	interrupts = <3>;
191	};
192	};
193
374ddcbf AT	194	timer0: timer@2c00 {
	195	compatible = "snps,dw-apb-timer";
	196	reg = <0x2c00 0x14>;
414dcf8f	197	clocks = <&chip CLKID_CFG>;
374ddcbf AT	198	clock-names = "timer";
	199	interrupts = <8>;
	200	};
	201
	202	timer1: timer@2c14 {
	203	compatible = "snps,dw-apb-timer";
	204	reg = <0x2c14 0x14>;
414dcf8f	205	clocks = <&chip CLKID_CFG>;
374ddcbf AT	206	clock-names = "timer";
	207	status = "disabled";
	208	};
	209
	210	timer2: timer@2c28 {
	211	compatible = "snps,dw-apb-timer";
	212	reg = <0x2c28 0x14>;
414dcf8f	213	clocks = <&chip CLKID_CFG>;
374ddcbf AT	214	clock-names = "timer";
	215	status = "disabled";
	216	};
	217
	218	timer3: timer@2c3c {
	219	compatible = "snps,dw-apb-timer";
	220	reg = <0x2c3c 0x14>;
414dcf8f	221	clocks = <&chip CLKID_CFG>;
374ddcbf AT	222	clock-names = "timer";
	223	status = "disabled";
	224	};
	225
	226	timer4: timer@2c50 {
	227	compatible = "snps,dw-apb-timer";
	228	reg = <0x2c50 0x14>;
414dcf8f	229	clocks = <&chip CLKID_CFG>;
374ddcbf AT	230	clock-names = "timer";
	231	status = "disabled";
	232	};
	233
	234	timer5: timer@2c64 {
	235	compatible = "snps,dw-apb-timer";
	236	reg = <0x2c64 0x14>;
414dcf8f	237	clocks = <&chip CLKID_CFG>;
374ddcbf AT	238	clock-names = "timer";
	239	status = "disabled";
	240	};
	241
	242	timer6: timer@2c78 {
	243	compatible = "snps,dw-apb-timer";
	244	reg = <0x2c78 0x14>;
414dcf8f	245	clocks = <&chip CLKID_CFG>;
374ddcbf AT	246	clock-names = "timer";
	247	status = "disabled";
	248	};
	249
	250	timer7: timer@2c8c {
	251	compatible = "snps,dw-apb-timer";
	252	reg = <0x2c8c 0x14>;
414dcf8f	253	clocks = <&chip CLKID_CFG>;
374ddcbf AT	254	clock-names = "timer";
	255	status = "disabled";
	256	};
	257
	258	aic: interrupt-controller@3800 {
	259	compatible = "snps,dw-apb-ictl";
	260	reg = <0x3800 0x30>;
	261	interrupt-controller;
	262	#interrupt-cells = <1>;
	263	interrupt-parent = <&gic>;
	264	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	265	};
cedf57fc AT	266
	267	gpio4: gpio@5000 {
	268	compatible = "snps,dw-apb-gpio";
	269	reg = <0x5000 0x400>;
	270	#address-cells = <1>;
	271	#size-cells = <0>;
	272
	273	porte: gpio-port@4 {
	274	compatible = "snps,dw-apb-gpio-port";
	275	gpio-controller;
	276	#gpio-cells = <2>;
	277	snps,nr-gpios = <32>;
	278	reg = <0>;
	279	};
	280	};
	281
	282	gpio5: gpio@c000 {
	283	compatible = "snps,dw-apb-gpio";
	284	reg = <0xc000 0x400>;
	285	#address-cells = <1>;
	286	#size-cells = <0>;
	287
	288	portf: gpio-port@5 {
	289	compatible = "snps,dw-apb-gpio-port";
	290	gpio-controller;
	291	#gpio-cells = <2>;
	292	snps,nr-gpios = <32>;
	293	reg = <0>;
	294	};
	295	};
374ddcbf AT	296	};
374ddcbf AT	297
414dcf8f AB	298	chip: chip-control@ea0000 {
	299	compatible = "marvell,berlin2q-chip-ctrl";
	300	#clock-cells = <1>;
	301	reg = <0xea0000 0x400>, <0xdd0170 0x10>;
	302	clocks = <&refclk>;
	303	clock-names = "refclk";
0bd4b346 SH	304	};
0bd4b346 SH	305
374ddcbf AT	306	apb@fc0000 {
	307	compatible = "simple-bus";
	308	#address-cells = <1>;
	309	#size-cells = <1>;
	310
	311	ranges = <0 0xfc0000 0x10000>;
	312	interrupt-parent = <&sic>;
	313
	314	uart0: uart@9000 {
	315	compatible = "snps,dw-apb-uart";
	316	reg = <0x9000 0x100>;
	317	interrupt-parent = <&sic>;
	318	interrupts = <8>;
414dcf8f	319	clocks = <&refclk>;
374ddcbf	320	reg-shift = <2>;
50cc24ff AT	321	pinctrl-0 = <&uart0_pmux>;
50cc24ff AT	322	pinctrl-names = "default";
374ddcbf AT	323	status = "disabled";
	324	};
	325
	326	uart1: uart@a000 {
	327	compatible = "snps,dw-apb-uart";
	328	reg = <0xa000 0x100>;
	329	interrupt-parent = <&sic>;
	330	interrupts = <9>;
414dcf8f	331	clocks = <&refclk>;
374ddcbf	332	reg-shift = <2>;
50cc24ff AT	333	pinctrl-0 = <&uart1_pmux>;
50cc24ff AT	334	pinctrl-names = "default";
374ddcbf AT	335	status = "disabled";
	336	};
	337
50cc24ff AT	338	sysctrl: pin-controller@d000 {
	339	compatible = "marvell,berlin2q-system-ctrl";
	340	reg = <0xd000 0x100>;
	341
	342	uart0_pmux: uart0-pmux {
	343	groups = "GSM12";
	344	function = "uart0";
	345	};
	346
	347	uart1_pmux: uart1-pmux {
	348	groups = "GSM14";
	349	function = "uart1";
	350	};
	351	};
	352
374ddcbf AT	353	sic: interrupt-controller@e000 {
	354	compatible = "snps,dw-apb-ictl";
	355	reg = <0xe000 0x30>;
	356	interrupt-controller;
	357	#interrupt-cells = <1>;
	358	interrupt-parent = <&gic>;
	359	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	360	};
	361	};
	362	};
	363	};