[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / berlin2q.dtsi

/*
 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <dt-bindings/clock/berlin2q.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	model = "Marvell Armada 1500 pro (BG2-Q) SoC";
	compatible = "marvell,berlin2q", "marvell,berlin";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <3>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0 0xf7000000 0x1000000>;
		interrupt-parent = <&gic>;

		sdhci0: sdhci@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip CLKID_SDIO1XIN>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci1: sdhci@ab0800 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0800 0x200>;
			clocks = <&chip CLKID_SDIO1XIN>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci2: sdhci@ab1000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab1000 0x200>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip CLKID_SDIO1XIN>;
			status = "disabled";
		};

		l2: l2-cache-controller@ac0000 {
			compatible = "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-level = <2>;
			arm,data-latency = <2 2 2>;
			arm,tag-latency = <2 2 2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			clocks = <&chip CLKID_TWD>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@0400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@0800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@0c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				interrupts = <8>;
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3800 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3800 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio4: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
				};
			};

			gpio5: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
				};
			};
		};

		chip: chip-control@ea0000 {
			compatible = "marvell,berlin2q-chip-ctrl";
			#clock-cells = <1>;
			reg = <0xea0000 0x400>, <0xdd0170 0x10>;
			clocks = <&refclk>;
			clock-names = "refclk";
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			uart0: uart@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <8>;
				clocks = <&refclk>;
				reg-shift = <2>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: uart@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <9>;
				clocks = <&refclk>;
				reg-shift = <2>;
				pinctrl-0 = <&uart1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sysctrl: pin-controller@d000 {
				compatible = "marvell,berlin2q-system-ctrl";
				reg = <0xd000 0x100>;

				uart0_pmux: uart0-pmux {
					groups = "GSM12";
					function = "uart0";
				};

				uart1_pmux: uart1-pmux {
					groups = "GSM14";
					function = "uart1";
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
374ddcbf AT	1	/*
	2	* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
	3	*
	4	* This file is licensed under the terms of the GNU General Public
	5	* License version 2. This program is licensed "as is" without any
	6	* warranty of any kind, whether express or implied.
	7	*/
	8
414dcf8f	9	#include <dt-bindings/clock/berlin2q.h>
374ddcbf AT	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
	11
	12	#include "skeleton.dtsi"
	13
	14	/ {
	15	model = "Marvell Armada 1500 pro (BG2-Q) SoC";
	16	compatible = "marvell,berlin2q", "marvell,berlin";
	17
	18	cpus {
	19	#address-cells = <1>;
	20	#size-cells = <0>;
	21
	22	cpu@0 {
	23	compatible = "arm,cortex-a9";
	24	device_type = "cpu";
	25	next-level-cache = <&l2>;
	26	reg = <0>;
	27	};
	28
	29	cpu@1 {
	30	compatible = "arm,cortex-a9";
	31	device_type = "cpu";
	32	next-level-cache = <&l2>;
	33	reg = <1>;
	34	};
	35
	36	cpu@2 {
	37	compatible = "arm,cortex-a9";
	38	device_type = "cpu";
	39	next-level-cache = <&l2>;
	40	reg = <2>;
	41	};
	42
	43	cpu@3 {
	44	compatible = "arm,cortex-a9";
	45	device_type = "cpu";
	46	next-level-cache = <&l2>;
	47	reg = <3>;
	48	};
	49	};
	50
414dcf8f	51	refclk: oscillator {
374ddcbf AT	52	compatible = "fixed-clock";
	53	#clock-cells = <0>;
	54	clock-frequency = <25000000>;
	55	};
	56
374ddcbf AT	57	soc {
	58	compatible = "simple-bus";
	59	#address-cells = <1>;
	60	#size-cells = <1>;
	61
	62	ranges = <0 0xf7000000 0x1000000>;
	63	interrupt-parent = <&gic>;
	64
0d859a6a AT	65	sdhci0: sdhci@ab0000 {
	66	compatible = "mrvl,pxav3-mmc";
	67	reg = <0xab0000 0x200>;
	68	clocks = <&chip CLKID_SDIO1XIN>;
	69	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	70	status = "disabled";
	71	};
	72
	73	sdhci1: sdhci@ab0800 {
	74	compatible = "mrvl,pxav3-mmc";
	75	reg = <0xab0800 0x200>;
	76	clocks = <&chip CLKID_SDIO1XIN>;
	77	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	78	status = "disabled";
	79	};
	80
	81	sdhci2: sdhci@ab1000 {
	82	compatible = "mrvl,pxav3-mmc";
	83	reg = <0xab1000 0x200>;
	84	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	85	clocks = <&chip CLKID_SDIO1XIN>;
	86	status = "disabled";
	87	};
	88
374ddcbf AT	89	l2: l2-cache-controller@ac0000 {
	90	compatible = "arm,pl310-cache";
	91	reg = <0xac0000 0x1000>;
	92	cache-level = <2>;
44991eb4 JZ	93	arm,data-latency = <2 2 2>;
44991eb4 JZ	94	arm,tag-latency = <2 2 2>;
374ddcbf AT	95	};
374ddcbf AT	96
0bd4b346 SH	97	scu: snoop-control-unit@ad0000 {
	98	compatible = "arm,cortex-a9-scu";
	99	reg = <0xad0000 0x58>;
	100	};
	101
374ddcbf AT	102	local-timer@ad0600 {
	103	compatible = "arm,cortex-a9-twd-timer";
	104	reg = <0xad0600 0x20>;
414dcf8f	105	clocks = <&chip CLKID_TWD>;
374ddcbf AT	106	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
	107	};
	108
	109	gic: interrupt-controller@ad1000 {
	110	compatible = "arm,cortex-a9-gic";
	111	reg = <0xad1000 0x1000>, <0xad0100 0x100>;
	112	interrupt-controller;
	113	#interrupt-cells = <3>;
	114	};
	115
	116	apb@e80000 {
	117	compatible = "simple-bus";
	118	#address-cells = <1>;
	119	#size-cells = <1>;
	120
	121	ranges = <0 0xe80000 0x10000>;
	122	interrupt-parent = <&aic>;
	123
cedf57fc AT	124	gpio0: gpio@0400 {
	125	compatible = "snps,dw-apb-gpio";
	126	reg = <0x0400 0x400>;
	127	#address-cells = <1>;
	128	#size-cells = <0>;
	129
	130	porta: gpio-port@0 {
	131	compatible = "snps,dw-apb-gpio-port";
	132	gpio-controller;
	133	#gpio-cells = <2>;
	134	snps,nr-gpios = <32>;
	135	reg = <0>;
	136	interrupt-controller;
	137	#interrupt-cells = <2>;
	138	interrupts = <0>;
	139	};
	140	};
	141
	142	gpio1: gpio@0800 {
	143	compatible = "snps,dw-apb-gpio";
	144	reg = <0x0800 0x400>;
	145	#address-cells = <1>;
	146	#size-cells = <0>;
	147
	148	portb: gpio-port@1 {
	149	compatible = "snps,dw-apb-gpio-port";
	150	gpio-controller;
	151	#gpio-cells = <2>;
	152	snps,nr-gpios = <32>;
	153	reg = <0>;
	154	interrupt-controller;
	155	#interrupt-cells = <2>;
	156	interrupts = <1>;
	157	};
	158	};
	159
	160	gpio2: gpio@0c00 {
	161	compatible = "snps,dw-apb-gpio";
	162	reg = <0x0c00 0x400>;
	163	#address-cells = <1>;
	164	#size-cells = <0>;
	165
	166	portc: gpio-port@2 {
	167	compatible = "snps,dw-apb-gpio-port";
	168	gpio-controller;
	169	#gpio-cells = <2>;
	170	snps,nr-gpios = <32>;
	171	reg = <0>;
	172	interrupt-controller;
	173	#interrupt-cells = <2>;
	174	interrupts = <2>;
	175	};
	176	};
	177
	178	gpio3: gpio@1000 {
	179	compatible = "snps,dw-apb-gpio";
	180	reg = <0x1000 0x400>;
	181	#address-cells = <1>;
	182	#size-cells = <0>;
	183
	184	portd: gpio-port@3 {
	185	compatible = "snps,dw-apb-gpio-port";
	186	gpio-controller;
	187	#gpio-cells = <2>;
188	snps,nr-gpios = <32>;
189	reg = <0>;
190	interrupt-controller;
191	#interrupt-cells = <2>;
192	interrupts = <3>;
193	};
194	};
195
374ddcbf AT	196	timer0: timer@2c00 {
	197	compatible = "snps,dw-apb-timer";
	198	reg = <0x2c00 0x14>;
414dcf8f	199	clocks = <&chip CLKID_CFG>;
374ddcbf AT	200	clock-names = "timer";
	201	interrupts = <8>;
	202	};
	203
	204	timer1: timer@2c14 {
	205	compatible = "snps,dw-apb-timer";
	206	reg = <0x2c14 0x14>;
414dcf8f	207	clocks = <&chip CLKID_CFG>;
374ddcbf AT	208	clock-names = "timer";
	209	status = "disabled";
	210	};
	211
	212	timer2: timer@2c28 {
	213	compatible = "snps,dw-apb-timer";
	214	reg = <0x2c28 0x14>;
414dcf8f	215	clocks = <&chip CLKID_CFG>;
374ddcbf AT	216	clock-names = "timer";
	217	status = "disabled";
	218	};
	219
	220	timer3: timer@2c3c {
	221	compatible = "snps,dw-apb-timer";
	222	reg = <0x2c3c 0x14>;
414dcf8f	223	clocks = <&chip CLKID_CFG>;
374ddcbf AT	224	clock-names = "timer";
	225	status = "disabled";
	226	};
	227
	228	timer4: timer@2c50 {
	229	compatible = "snps,dw-apb-timer";
	230	reg = <0x2c50 0x14>;
414dcf8f	231	clocks = <&chip CLKID_CFG>;
374ddcbf AT	232	clock-names = "timer";
	233	status = "disabled";
	234	};
	235
	236	timer5: timer@2c64 {
	237	compatible = "snps,dw-apb-timer";
	238	reg = <0x2c64 0x14>;
414dcf8f	239	clocks = <&chip CLKID_CFG>;
374ddcbf AT	240	clock-names = "timer";
	241	status = "disabled";
	242	};
	243
	244	timer6: timer@2c78 {
	245	compatible = "snps,dw-apb-timer";
	246	reg = <0x2c78 0x14>;
414dcf8f	247	clocks = <&chip CLKID_CFG>;
374ddcbf AT	248	clock-names = "timer";
	249	status = "disabled";
	250	};
	251
	252	timer7: timer@2c8c {
	253	compatible = "snps,dw-apb-timer";
	254	reg = <0x2c8c 0x14>;
414dcf8f	255	clocks = <&chip CLKID_CFG>;
374ddcbf AT	256	clock-names = "timer";
	257	status = "disabled";
	258	};
	259
	260	aic: interrupt-controller@3800 {
	261	compatible = "snps,dw-apb-ictl";
	262	reg = <0x3800 0x30>;
	263	interrupt-controller;
	264	#interrupt-cells = <1>;
	265	interrupt-parent = <&gic>;
	266	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	267	};
cedf57fc AT	268
	269	gpio4: gpio@5000 {
	270	compatible = "snps,dw-apb-gpio";
	271	reg = <0x5000 0x400>;
	272	#address-cells = <1>;
	273	#size-cells = <0>;
	274
	275	porte: gpio-port@4 {
	276	compatible = "snps,dw-apb-gpio-port";
	277	gpio-controller;
	278	#gpio-cells = <2>;
	279	snps,nr-gpios = <32>;
	280	reg = <0>;
	281	};
	282	};
	283
	284	gpio5: gpio@c000 {
	285	compatible = "snps,dw-apb-gpio";
	286	reg = <0xc000 0x400>;
	287	#address-cells = <1>;
	288	#size-cells = <0>;
	289
	290	portf: gpio-port@5 {
	291	compatible = "snps,dw-apb-gpio-port";
	292	gpio-controller;
	293	#gpio-cells = <2>;
	294	snps,nr-gpios = <32>;
	295	reg = <0>;
	296	};
	297	};
374ddcbf AT	298	};
374ddcbf AT	299
414dcf8f AB	300	chip: chip-control@ea0000 {
	301	compatible = "marvell,berlin2q-chip-ctrl";
	302	#clock-cells = <1>;
	303	reg = <0xea0000 0x400>, <0xdd0170 0x10>;
	304	clocks = <&refclk>;
	305	clock-names = "refclk";
0bd4b346 SH	306	};
0bd4b346 SH	307
374ddcbf AT	308	apb@fc0000 {
	309	compatible = "simple-bus";
	310	#address-cells = <1>;
	311	#size-cells = <1>;
	312
	313	ranges = <0 0xfc0000 0x10000>;
	314	interrupt-parent = <&sic>;
	315
	316	uart0: uart@9000 {
	317	compatible = "snps,dw-apb-uart";
	318	reg = <0x9000 0x100>;
	319	interrupt-parent = <&sic>;
	320	interrupts = <8>;
414dcf8f	321	clocks = <&refclk>;
374ddcbf	322	reg-shift = <2>;
50cc24ff AT	323	pinctrl-0 = <&uart0_pmux>;
50cc24ff AT	324	pinctrl-names = "default";
374ddcbf AT	325	status = "disabled";
	326	};
	327
	328	uart1: uart@a000 {
	329	compatible = "snps,dw-apb-uart";
	330	reg = <0xa000 0x100>;
	331	interrupt-parent = <&sic>;
	332	interrupts = <9>;
414dcf8f	333	clocks = <&refclk>;
374ddcbf	334	reg-shift = <2>;
50cc24ff AT	335	pinctrl-0 = <&uart1_pmux>;
50cc24ff AT	336	pinctrl-names = "default";
374ddcbf AT	337	status = "disabled";
	338	};
	339
50cc24ff AT	340	sysctrl: pin-controller@d000 {
	341	compatible = "marvell,berlin2q-system-ctrl";
	342	reg = <0xd000 0x100>;
	343
	344	uart0_pmux: uart0-pmux {
	345	groups = "GSM12";
	346	function = "uart0";
	347	};
	348
	349	uart1_pmux: uart1-pmux {
	350	groups = "GSM14";
	351	function = "uart1";
	352	};
	353	};
	354
374ddcbf AT	355	sic: interrupt-controller@e000 {
	356	compatible = "snps,dw-apb-ictl";
	357	reg = <0xe000 0x30>;
	358	interrupt-controller;
	359	#interrupt-cells = <1>;
	360	interrupt-parent = <&gic>;
	361	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	362	};
	363	};
	364	};
	365	};