[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / berlin2q.dtsi

/*
 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <dt-bindings/clock/berlin2q.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	model = "Marvell Armada 1500 pro (BG2-Q) SoC";
	compatible = "marvell,berlin2q", "marvell,berlin";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,berlin-smp";

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <3>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0 0xf7000000 0x1000000>;
		interrupt-parent = <&gic>;

		pmu {
			compatible = "arm,cortex-a9-pmu";
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		};

		sdhci0: sdhci@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip_clk CLKID_SDIO1XIN>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci1: sdhci@ab0800 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0800 0x200>;
			clocks = <&chip_clk CLKID_SDIO1XIN>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci2: sdhci@ab1000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab1000 0x200>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
			clock-names = "io", "core";
			status = "disabled";
		};

		l2: l2-cache-controller@ac0000 {
			compatible = "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-level = <2>;
			arm,data-latency = <2 2 2>;
			arm,tag-latency = <2 2 2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			clocks = <&chip_clk CLKID_TWD>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		usb_phy2: phy@a2f400 {
			compatible = "marvell,berlin2-usb-phy";
			reg = <0xa2f400 0x128>;
			#phy-cells = <0>;
			resets = <&chip_rst 0x104 14>;
			status = "disabled";
		};

		usb2: usb@a30000 {
			compatible = "chipidea,usb2";
			reg = <0xa30000 0x10000>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_USB2>;
			phys = <&usb_phy2>;
			phy-names = "usb-phy";
			status = "disabled";
		};

		usb_phy0: phy@b74000 {
			compatible = "marvell,berlin2-usb-phy";
			reg = <0xb74000 0x128>;
			#phy-cells = <0>;
			resets = <&chip_rst 0x104 12>;
			status = "disabled";
		};

		usb_phy1: phy@b78000 {
			compatible = "marvell,berlin2-usb-phy";
			reg = <0xb78000 0x128>;
			#phy-cells = <0>;
			resets = <&chip_rst 0x104 13>;
			status = "disabled";
		};

		eth0: ethernet@b90000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xb90000 0x10000>;
			clocks = <&chip_clk CLKID_GETH0>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy0>;
			status = "disabled";

			ethphy0: ethernet-phy@0 {
				reg = <0>;
			};
		};

		cpu-ctrl@dd0000 {
			compatible = "marvell,berlin-cpu-ctrl";
			reg = <0xdd0000 0x10000>;
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@0400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@0800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@0c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			i2c0: i2c@1400 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x1400 0x100>;
				interrupt-parent = <&aic>;
				interrupts = <4>;
				clocks = <&chip_clk CLKID_CFG>;
				pinctrl-0 = <&twsi0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			i2c1: i2c@1800 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x1800 0x100>;
				interrupt-parent = <&aic>;
				interrupts = <5>;
				clocks = <&chip_clk CLKID_CFG>;
				pinctrl-0 = <&twsi1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				interrupts = <8>;
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3800 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3800 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		chip: chip-control@ea0000 {
			compatible = "simple-mfd", "syscon";
			reg = <0xea0000 0x400>, <0xdd0170 0x10>;

			chip_clk: clock {
				compatible = "marvell,berlin2q-clk";
				#clock-cells = <1>;
				clocks = <&refclk>;
				clock-names = "refclk";
			};

			soc_pinctrl: pin-controller {
				compatible = "marvell,berlin2q-soc-pinctrl";

				twsi0_pmux: twsi0-pmux {
					groups = "G6";
					function = "twsi0";
				};

				twsi1_pmux: twsi1-pmux {
					groups = "G7";
					function = "twsi1";
				};
			};

			chip_rst: reset {
				compatible = "marvell,berlin2-reset";
				#reset-cells = <2>;
			};
		};

		ahci: sata@e90000 {
			compatible = "marvell,berlin2q-ahci", "generic-ahci";
			reg = <0xe90000 0x1000>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_SATA>;
			#address-cells = <1>;
			#size-cells = <0>;

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy 0>;
				status = "disabled";
			};

			sata1: sata-port@1 {
				reg = <1>;
				phys = <&sata_phy 1>;
				status = "disabled";
			};
		};

		sata_phy: phy@e900a0 {
			compatible = "marvell,berlin2q-sata-phy";
			reg = <0xe900a0 0x200>;
			clocks = <&chip_clk CLKID_SATA>;
			#address-cells = <1>;
			#size-cells = <0>;
			#phy-cells = <1>;
			status = "disabled";

			sata-phy@0 {
				reg = <0>;
			};

			sata-phy@1 {
				reg = <1>;
			};
		};

		usb0: usb@ed0000 {
			compatible = "chipidea,usb2";
			reg = <0xed0000 0x10000>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_USB0>;
			phys = <&usb_phy0>;
			phy-names = "usb-phy";
			status = "disabled";
		};

		usb1: usb@ee0000 {
			compatible = "chipidea,usb2";
			reg = <0xee0000 0x10000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_USB1>;
			phys = <&usb_phy1>;
			phy-names = "usb-phy";
			status = "disabled";
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			sm_gpio1: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
				};
			};

			i2c2: i2c@7000 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x7000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <6>;
				clocks = <&refclk>;
				pinctrl-0 = <&twsi2_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			i2c3: i2c@8000 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x8000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <7>;
				clocks = <&refclk>;
				pinctrl-0 = <&twsi3_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart0: uart@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <8>;
				clocks = <&refclk>;
				reg-shift = <2>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: uart@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <9>;
				clocks = <&refclk>;
				reg-shift = <2>;
				pinctrl-0 = <&uart1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sm_gpio0: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
				};
			};

			sysctrl: pin-controller@d000 {
				compatible = "simple-mfd", "syscon";
				reg = <0xd000 0x100>;

				sys_pinctrl: pin-controller {
					compatible = "marvell,berlin2q-system-pinctrl";

					uart0_pmux: uart0-pmux {
						groups = "GSM12";
						function = "uart0";
					};

					uart1_pmux: uart1-pmux {
						groups = "GSM14";
						function = "uart1";
					};

					twsi2_pmux: twsi2-pmux {
						groups = "GSM13";
						function = "twsi2";
					};

					twsi3_pmux: twsi3-pmux {
						groups = "GSM14";
						function = "twsi3";
					};
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
374ddcbf AT	1	/*
	2	* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
	3	*
	4	* This file is licensed under the terms of the GNU General Public
	5	* License version 2. This program is licensed "as is" without any
	6	* warranty of any kind, whether express or implied.
	7	*/
	8
414dcf8f	9	#include <dt-bindings/clock/berlin2q.h>
374ddcbf AT	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
	11
	12	#include "skeleton.dtsi"
	13
	14	/ {
	15	model = "Marvell Armada 1500 pro (BG2-Q) SoC";
	16	compatible = "marvell,berlin2q", "marvell,berlin";
	17
	18	cpus {
	19	#address-cells = <1>;
	20	#size-cells = <0>;
d19c9367	21	enable-method = "marvell,berlin-smp";
374ddcbf AT	22
	23	cpu@0 {
	24	compatible = "arm,cortex-a9";
	25	device_type = "cpu";
	26	next-level-cache = <&l2>;
	27	reg = <0>;
	28	};
	29
	30	cpu@1 {
	31	compatible = "arm,cortex-a9";
	32	device_type = "cpu";
	33	next-level-cache = <&l2>;
	34	reg = <1>;
	35	};
	36
	37	cpu@2 {
	38	compatible = "arm,cortex-a9";
	39	device_type = "cpu";
	40	next-level-cache = <&l2>;
	41	reg = <2>;
	42	};
	43
	44	cpu@3 {
	45	compatible = "arm,cortex-a9";
	46	device_type = "cpu";
	47	next-level-cache = <&l2>;
	48	reg = <3>;
	49	};
	50	};
	51
414dcf8f	52	refclk: oscillator {
374ddcbf AT	53	compatible = "fixed-clock";
	54	#clock-cells = <0>;
	55	clock-frequency = <25000000>;
	56	};
	57
374ddcbf AT	58	soc {
	59	compatible = "simple-bus";
	60	#address-cells = <1>;
	61	#size-cells = <1>;
	62
	63	ranges = <0 0xf7000000 0x1000000>;
	64	interrupt-parent = <&gic>;
	65
d4ce8042 JZ	66	pmu {
	67	compatible = "arm,cortex-a9-pmu";
	68	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	69	<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	70	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	71	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	72	};
	73
0d859a6a AT	74	sdhci0: sdhci@ab0000 {
	75	compatible = "mrvl,pxav3-mmc";
	76	reg = <0xab0000 0x200>;
a457b86c	77	clocks = <&chip_clk CLKID_SDIO1XIN>;
0d859a6a AT	78	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	79	status = "disabled";
	80	};
	81
	82	sdhci1: sdhci@ab0800 {
	83	compatible = "mrvl,pxav3-mmc";
	84	reg = <0xab0800 0x200>;
a457b86c	85	clocks = <&chip_clk CLKID_SDIO1XIN>;
0d859a6a AT	86	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	87	status = "disabled";
	88	};
	89
	90	sdhci2: sdhci@ab1000 {
	91	compatible = "mrvl,pxav3-mmc";
	92	reg = <0xab1000 0x200>;
	93	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
a457b86c	94	clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
96ed6046	95	clock-names = "io", "core";
0d859a6a AT	96	status = "disabled";
	97	};
	98
374ddcbf AT	99	l2: l2-cache-controller@ac0000 {
	100	compatible = "arm,pl310-cache";
	101	reg = <0xac0000 0x1000>;
	102	cache-level = <2>;
44991eb4 JZ	103	arm,data-latency = <2 2 2>;
44991eb4 JZ	104	arm,tag-latency = <2 2 2>;
374ddcbf AT	105	};
374ddcbf AT	106
0bd4b346 SH	107	scu: snoop-control-unit@ad0000 {
	108	compatible = "arm,cortex-a9-scu";
	109	reg = <0xad0000 0x58>;
	110	};
	111
374ddcbf AT	112	local-timer@ad0600 {
	113	compatible = "arm,cortex-a9-twd-timer";
	114	reg = <0xad0600 0x20>;
a457b86c	115	clocks = <&chip_clk CLKID_TWD>;
2356d2f3	116	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
374ddcbf AT	117	};
	118
	119	gic: interrupt-controller@ad1000 {
	120	compatible = "arm,cortex-a9-gic";
	121	reg = <0xad1000 0x1000>, <0xad0100 0x100>;
	122	interrupt-controller;
	123	#interrupt-cells = <3>;
	124	};
	125
c539711e AT	126	usb_phy2: phy@a2f400 {
	127	compatible = "marvell,berlin2-usb-phy";
	128	reg = <0xa2f400 0x128>;
	129	#phy-cells = <0>;
43225728	130	resets = <&chip_rst 0x104 14>;
c539711e AT	131	status = "disabled";
	132	};
	133
	134	usb2: usb@a30000 {
	135	compatible = "chipidea,usb2";
	136	reg = <0xa30000 0x10000>;
	137	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
a457b86c	138	clocks = <&chip_clk CLKID_USB2>;
c539711e AT	139	phys = <&usb_phy2>;
	140	phy-names = "usb-phy";
	141	status = "disabled";
	142	};
	143
	144	usb_phy0: phy@b74000 {
	145	compatible = "marvell,berlin2-usb-phy";
	146	reg = <0xb74000 0x128>;
	147	#phy-cells = <0>;
43225728	148	resets = <&chip_rst 0x104 12>;
c539711e AT	149	status = "disabled";
	150	};
	151
	152	usb_phy1: phy@b78000 {
	153	compatible = "marvell,berlin2-usb-phy";
	154	reg = <0xb78000 0x128>;
	155	#phy-cells = <0>;
43225728	156	resets = <&chip_rst 0x104 13>;
c539711e AT	157	status = "disabled";
	158	};
	159
bdc06cd7 AT	160	eth0: ethernet@b90000 {
	161	compatible = "marvell,pxa168-eth";
	162	reg = <0xb90000 0x10000>;
a457b86c	163	clocks = <&chip_clk CLKID_GETH0>;
bdc06cd7 AT	164	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	165	/* set by bootloader */
	166	local-mac-address = [00 00 00 00 00 00];
	167	#address-cells = <1>;
	168	#size-cells = <0>;
f5799dcf	169	phy-connection-type = "mii";
bdc06cd7 AT	170	phy-handle = <&ethphy0>;
	171	status = "disabled";
	172
	173	ethphy0: ethernet-phy@0 {
	174	reg = <0>;
	175	};
	176	};
	177
d19c9367 AT	178	cpu-ctrl@dd0000 {
	179	compatible = "marvell,berlin-cpu-ctrl";
	180	reg = <0xdd0000 0x10000>;
	181	};
	182
374ddcbf AT	183	apb@e80000 {
	184	compatible = "simple-bus";
	185	#address-cells = <1>;
	186	#size-cells = <1>;
	187
	188	ranges = <0 0xe80000 0x10000>;
	189	interrupt-parent = <&aic>;
	190
cedf57fc AT	191	gpio0: gpio@0400 {
	192	compatible = "snps,dw-apb-gpio";
	193	reg = <0x0400 0x400>;
	194	#address-cells = <1>;
	195	#size-cells = <0>;
	196
	197	porta: gpio-port@0 {
	198	compatible = "snps,dw-apb-gpio-port";
	199	gpio-controller;
	200	#gpio-cells = <2>;
	201	snps,nr-gpios = <32>;
	202	reg = <0>;
	203	interrupt-controller;
	204	#interrupt-cells = <2>;
	205	interrupts = <0>;
	206	};
	207	};
	208
	209	gpio1: gpio@0800 {
	210	compatible = "snps,dw-apb-gpio";
	211	reg = <0x0800 0x400>;
	212	#address-cells = <1>;
	213	#size-cells = <0>;
	214
	215	portb: gpio-port@1 {
	216	compatible = "snps,dw-apb-gpio-port";
	217	gpio-controller;
	218	#gpio-cells = <2>;
	219	snps,nr-gpios = <32>;
	220	reg = <0>;
	221	interrupt-controller;
	222	#interrupt-cells = <2>;
	223	interrupts = <1>;
	224	};
	225	};
	226
	227	gpio2: gpio@0c00 {
	228	compatible = "snps,dw-apb-gpio";
	229	reg = <0x0c00 0x400>;
	230	#address-cells = <1>;
	231	#size-cells = <0>;
	232
	233	portc: gpio-port@2 {
	234	compatible = "snps,dw-apb-gpio-port";
	235	gpio-controller;
	236	#gpio-cells = <2>;
	237	snps,nr-gpios = <32>;
	238	reg = <0>;
	239	interrupt-controller;
	240	#interrupt-cells = <2>;
	241	interrupts = <2>;
	242	};
	243	};
	244
	245	gpio3: gpio@1000 {
	246	compatible = "snps,dw-apb-gpio";
	247	reg = <0x1000 0x400>;
	248	#address-cells = <1>;
	249	#size-cells = <0>;
	250
	251	portd: gpio-port@3 {
	252	compatible = "snps,dw-apb-gpio-port";
	253	gpio-controller;
	254	#gpio-cells = <2>;
255	snps,nr-gpios = <32>;
256	reg = <0>;
257	interrupt-controller;
258	#interrupt-cells = <2>;
259	interrupts = <3>;
260	};
261	};
262
99f3deb8 AT	263	i2c0: i2c@1400 {
	264	compatible = "snps,designware-i2c";
	265	#address-cells = <1>;
	266	#size-cells = <0>;
	267	reg = <0x1400 0x100>;
	268	interrupt-parent = <&aic>;
	269	interrupts = <4>;
a457b86c	270	clocks = <&chip_clk CLKID_CFG>;
99f3deb8 AT	271	pinctrl-0 = <&twsi0_pmux>;
	272	pinctrl-names = "default";
	273	status = "disabled";
	274	};
	275
	276	i2c1: i2c@1800 {
	277	compatible = "snps,designware-i2c";
	278	#address-cells = <1>;
	279	#size-cells = <0>;
	280	reg = <0x1800 0x100>;
	281	interrupt-parent = <&aic>;
	282	interrupts = <5>;
a457b86c	283	clocks = <&chip_clk CLKID_CFG>;
99f3deb8 AT	284	pinctrl-0 = <&twsi1_pmux>;
	285	pinctrl-names = "default";
	286	status = "disabled";
	287	};
	288
374ddcbf AT	289	timer0: timer@2c00 {
	290	compatible = "snps,dw-apb-timer";
	291	reg = <0x2c00 0x14>;
a457b86c	292	clocks = <&chip_clk CLKID_CFG>;
374ddcbf AT	293	clock-names = "timer";
	294	interrupts = <8>;
	295	};
	296
	297	timer1: timer@2c14 {
	298	compatible = "snps,dw-apb-timer";
	299	reg = <0x2c14 0x14>;
a457b86c	300	clocks = <&chip_clk CLKID_CFG>;
374ddcbf	301	clock-names = "timer";
374ddcbf AT	302	};
	303
	304	timer2: timer@2c28 {
	305	compatible = "snps,dw-apb-timer";
	306	reg = <0x2c28 0x14>;
a457b86c	307	clocks = <&chip_clk CLKID_CFG>;
374ddcbf AT	308	clock-names = "timer";
	309	status = "disabled";
	310	};
	311
	312	timer3: timer@2c3c {
	313	compatible = "snps,dw-apb-timer";
	314	reg = <0x2c3c 0x14>;
a457b86c	315	clocks = <&chip_clk CLKID_CFG>;
374ddcbf AT	316	clock-names = "timer";
	317	status = "disabled";
	318	};
	319
	320	timer4: timer@2c50 {
	321	compatible = "snps,dw-apb-timer";
	322	reg = <0x2c50 0x14>;
a457b86c	323	clocks = <&chip_clk CLKID_CFG>;
374ddcbf AT	324	clock-names = "timer";
	325	status = "disabled";
	326	};
	327
	328	timer5: timer@2c64 {
	329	compatible = "snps,dw-apb-timer";
	330	reg = <0x2c64 0x14>;
a457b86c	331	clocks = <&chip_clk CLKID_CFG>;
374ddcbf AT	332	clock-names = "timer";
	333	status = "disabled";
	334	};
	335
	336	timer6: timer@2c78 {
	337	compatible = "snps,dw-apb-timer";
	338	reg = <0x2c78 0x14>;
a457b86c	339	clocks = <&chip_clk CLKID_CFG>;
374ddcbf AT	340	clock-names = "timer";
	341	status = "disabled";
	342	};
	343
	344	timer7: timer@2c8c {
	345	compatible = "snps,dw-apb-timer";
	346	reg = <0x2c8c 0x14>;
a457b86c	347	clocks = <&chip_clk CLKID_CFG>;
374ddcbf AT	348	clock-names = "timer";
	349	status = "disabled";
	350	};
	351
	352	aic: interrupt-controller@3800 {
	353	compatible = "snps,dw-apb-ictl";
	354	reg = <0x3800 0x30>;
	355	interrupt-controller;
	356	#interrupt-cells = <1>;
	357	interrupt-parent = <&gic>;
	358	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	359	};
	360	};
	361
414dcf8f	362	chip: chip-control@ea0000 {
f3f94f71	363	compatible = "simple-mfd", "syscon";
414dcf8f	364	reg = <0xea0000 0x400>, <0xdd0170 0x10>;
a457b86c AT	365
	366	chip_clk: clock {
	367	compatible = "marvell,berlin2q-clk";
	368	#clock-cells = <1>;
	369	clocks = <&refclk>;
	370	clock-names = "refclk";
	371	};
99f3deb8	372
630c986b AT	373	soc_pinctrl: pin-controller {
	374	compatible = "marvell,berlin2q-soc-pinctrl";
	375
	376	twsi0_pmux: twsi0-pmux {
	377	groups = "G6";
	378	function = "twsi0";
	379	};
99f3deb8	380
630c986b AT	381	twsi1_pmux: twsi1-pmux {
	382	groups = "G7";
	383	function = "twsi1";
	384	};
99f3deb8	385	};
43225728 AT	386
	387	chip_rst: reset {
	388	compatible = "marvell,berlin2-reset";
	389	#reset-cells = <2>;
	390	};
0bd4b346 SH	391	};
0bd4b346 SH	392
70a2b717 AT	393	ahci: sata@e90000 {
	394	compatible = "marvell,berlin2q-ahci", "generic-ahci";
	395	reg = <0xe90000 0x1000>;
	396	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
a457b86c	397	clocks = <&chip_clk CLKID_SATA>;
70a2b717 AT	398	#address-cells = <1>;
	399	#size-cells = <0>;
	400
	401	sata0: sata-port@0 {
	402	reg = <0>;
	403	phys = <&sata_phy 0>;
	404	status = "disabled";
	405	};
	406
	407	sata1: sata-port@1 {
	408	reg = <1>;
	409	phys = <&sata_phy 1>;
	410	status = "disabled";
	411	};
	412	};
	413
	414	sata_phy: phy@e900a0 {
	415	compatible = "marvell,berlin2q-sata-phy";
	416	reg = <0xe900a0 0x200>;
a457b86c	417	clocks = <&chip_clk CLKID_SATA>;
70a2b717 AT	418	#address-cells = <1>;
	419	#size-cells = <0>;
	420	#phy-cells = <1>;
	421	status = "disabled";
	422
	423	sata-phy@0 {
	424	reg = <0>;
	425	};
	426
	427	sata-phy@1 {
	428	reg = <1>;
	429	};
	430	};
	431
c539711e AT	432	usb0: usb@ed0000 {
	433	compatible = "chipidea,usb2";
	434	reg = <0xed0000 0x10000>;
	435	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
a457b86c	436	clocks = <&chip_clk CLKID_USB0>;
c539711e AT	437	phys = <&usb_phy0>;
	438	phy-names = "usb-phy";
	439	status = "disabled";
	440	};
	441
	442	usb1: usb@ee0000 {
	443	compatible = "chipidea,usb2";
	444	reg = <0xee0000 0x10000>;
	445	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
a457b86c	446	clocks = <&chip_clk CLKID_USB1>;
c539711e AT	447	phys = <&usb_phy1>;
	448	phy-names = "usb-phy";
	449	status = "disabled";
	450	};
	451
374ddcbf AT	452	apb@fc0000 {
	453	compatible = "simple-bus";
	454	#address-cells = <1>;
	455	#size-cells = <1>;
	456
	457	ranges = <0 0xfc0000 0x10000>;
	458	interrupt-parent = <&sic>;
	459
5138d5c5 JZ	460	sm_gpio1: gpio@5000 {
	461	compatible = "snps,dw-apb-gpio";
	462	reg = <0x5000 0x400>;
	463	#address-cells = <1>;
	464	#size-cells = <0>;
	465
	466	portf: gpio-port@5 {
	467	compatible = "snps,dw-apb-gpio-port";
	468	gpio-controller;
	469	#gpio-cells = <2>;
	470	snps,nr-gpios = <32>;
	471	reg = <0>;
	472	};
	473	};
	474
99f3deb8 AT	475	i2c2: i2c@7000 {
	476	compatible = "snps,designware-i2c";
	477	#address-cells = <1>;
	478	#size-cells = <0>;
	479	reg = <0x7000 0x100>;
	480	interrupt-parent = <&sic>;
	481	interrupts = <6>;
	482	clocks = <&refclk>;
	483	pinctrl-0 = <&twsi2_pmux>;
	484	pinctrl-names = "default";
	485	status = "disabled";
	486	};
	487
	488	i2c3: i2c@8000 {
	489	compatible = "snps,designware-i2c";
	490	#address-cells = <1>;
	491	#size-cells = <0>;
	492	reg = <0x8000 0x100>;
	493	interrupt-parent = <&sic>;
	494	interrupts = <7>;
	495	clocks = <&refclk>;
	496	pinctrl-0 = <&twsi3_pmux>;
	497	pinctrl-names = "default";
	498	status = "disabled";
	499	};
	500
374ddcbf AT	501	uart0: uart@9000 {
	502	compatible = "snps,dw-apb-uart";
	503	reg = <0x9000 0x100>;
	504	interrupt-parent = <&sic>;
	505	interrupts = <8>;
414dcf8f	506	clocks = <&refclk>;
374ddcbf	507	reg-shift = <2>;
50cc24ff AT	508	pinctrl-0 = <&uart0_pmux>;
50cc24ff AT	509	pinctrl-names = "default";
374ddcbf AT	510	status = "disabled";
	511	};
	512
	513	uart1: uart@a000 {
	514	compatible = "snps,dw-apb-uart";
	515	reg = <0xa000 0x100>;
	516	interrupt-parent = <&sic>;
	517	interrupts = <9>;
414dcf8f	518	clocks = <&refclk>;
374ddcbf	519	reg-shift = <2>;
50cc24ff AT	520	pinctrl-0 = <&uart1_pmux>;
50cc24ff AT	521	pinctrl-names = "default";
374ddcbf AT	522	status = "disabled";
	523	};
	524
5138d5c5 JZ	525	sm_gpio0: gpio@c000 {
	526	compatible = "snps,dw-apb-gpio";
	527	reg = <0xc000 0x400>;
	528	#address-cells = <1>;
	529	#size-cells = <0>;
	530
	531	porte: gpio-port@4 {
	532	compatible = "snps,dw-apb-gpio-port";
	533	gpio-controller;
	534	#gpio-cells = <2>;
	535	snps,nr-gpios = <32>;
	536	reg = <0>;
	537	};
	538	};
	539
50cc24ff	540	sysctrl: pin-controller@d000 {
f3f94f71	541	compatible = "simple-mfd", "syscon";
50cc24ff AT	542	reg = <0xd000 0x100>;
50cc24ff AT	543
630c986b AT	544	sys_pinctrl: pin-controller {
630c986b AT	545	compatible = "marvell,berlin2q-system-pinctrl";
50cc24ff	546
630c986b AT	547	uart0_pmux: uart0-pmux {
	548	groups = "GSM12";
	549	function = "uart0";
	550	};
99f3deb8	551
630c986b AT	552	uart1_pmux: uart1-pmux {
	553	groups = "GSM14";
	554	function = "uart1";
	555	};
	556
	557	twsi2_pmux: twsi2-pmux {
	558	groups = "GSM13";
	559	function = "twsi2";
	560	};
99f3deb8	561
630c986b AT	562	twsi3_pmux: twsi3-pmux {
	563	groups = "GSM14";
	564	function = "twsi3";
	565	};
99f3deb8	566	};
50cc24ff AT	567	};
50cc24ff AT	568
374ddcbf AT	569	sic: interrupt-controller@e000 {
	570	compatible = "snps,dw-apb-ictl";
	571	reg = <0xe000 0x30>;
	572	interrupt-controller;
	573	#interrupt-cells = <1>;
	574	interrupt-parent = <&gic>;
	575	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	576	};
	577	};
	578	};
	579	};