]>
Commit | Line | Data |
---|---|---|
f50a7f3d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
44524a01 KB |
2 | /* |
3 | * Copyright (c) 2016 BayLibre, Inc. | |
44524a01 KB |
4 | */ |
5 | /dts-v1/; | |
6 | #include "da850.dtsi" | |
7 | #include <dt-bindings/gpio/gpio.h> | |
e3d9e1eb | 8 | #include <dt-bindings/input/input.h> |
44524a01 KB |
9 | |
10 | / { | |
11 | model = "DA850/AM1808/OMAP-L138 LCDK"; | |
12 | compatible = "ti,da850-lcdk", "ti,da850"; | |
13 | ||
14 | aliases { | |
15 | serial2 = &serial2; | |
e177e730 | 16 | ethernet0 = ð0; |
44524a01 KB |
17 | }; |
18 | ||
19 | chosen { | |
20 | stdout-path = "serial2:115200n8"; | |
21 | }; | |
22 | ||
01de0be5 SN |
23 | memory@c0000000 { |
24 | /* 128 MB DDR2 SDRAM @ 0xc0000000 */ | |
44524a01 KB |
25 | reg = <0xc0000000 0x08000000>; |
26 | }; | |
9d05b389 | 27 | |
d9fe22b8 SA |
28 | reserved-memory { |
29 | #address-cells = <1>; | |
30 | #size-cells = <1>; | |
31 | ranges; | |
32 | ||
33 | dsp_memory_region: dsp-memory@c3000000 { | |
34 | compatible = "shared-dma-pool"; | |
35 | reg = <0xc3000000 0x1000000>; | |
36 | reusable; | |
37 | status = "okay"; | |
38 | }; | |
39 | }; | |
40 | ||
bd540ebe PU |
41 | vcc_5vd: fixedregulator-vcc_5vd { |
42 | compatible = "regulator-fixed"; | |
43 | regulator-name = "vcc_5vd"; | |
44 | regulator-min-microvolt = <5000000>; | |
45 | regulator-max-microvolt = <5000000>; | |
46 | regulator-boot-on; | |
47 | }; | |
48 | ||
49 | vcc_3v3d: fixedregulator-vcc_3v3d { | |
50 | /* TPS650250 - VDCDC1 */ | |
51 | compatible = "regulator-fixed"; | |
52 | regulator-name = "vcc_3v3d"; | |
53 | regulator-min-microvolt = <3300000>; | |
54 | regulator-max-microvolt = <3300000>; | |
55 | vin-supply = <&vcc_5vd>; | |
56 | regulator-always-on; | |
57 | regulator-boot-on; | |
58 | }; | |
59 | ||
60 | vcc_1v8d: fixedregulator-vcc_1v8d { | |
61 | /* TPS650250 - VDCDC2 */ | |
62 | compatible = "regulator-fixed"; | |
63 | regulator-name = "vcc_1v8d"; | |
64 | regulator-min-microvolt = <1800000>; | |
65 | regulator-max-microvolt = <1800000>; | |
66 | vin-supply = <&vcc_5vd>; | |
67 | regulator-always-on; | |
68 | regulator-boot-on; | |
69 | }; | |
70 | ||
9d05b389 KB |
71 | sound { |
72 | compatible = "simple-audio-card"; | |
c25748ac | 73 | simple-audio-card,name = "DA850-OMAPL138 LCDK"; |
9d05b389 KB |
74 | simple-audio-card,widgets = |
75 | "Line", "Line In", | |
7dd2e8f8 PU |
76 | "Line", "Line Out", |
77 | "Microphone", "Mic Jack"; | |
9d05b389 KB |
78 | simple-audio-card,routing = |
79 | "LINE1L", "Line In", | |
80 | "LINE1R", "Line In", | |
81 | "Line Out", "LLOUT", | |
7dd2e8f8 PU |
82 | "Line Out", "RLOUT", |
83 | "MIC3L", "Mic Jack", | |
84 | "MIC3R", "Mic Jack", | |
85 | "Mic Jack", "Mic Bias"; | |
9d05b389 KB |
86 | simple-audio-card,format = "dsp_b"; |
87 | simple-audio-card,bitclock-master = <&link0_codec>; | |
88 | simple-audio-card,frame-master = <&link0_codec>; | |
89 | simple-audio-card,bitclock-inversion; | |
90 | ||
91 | simple-audio-card,cpu { | |
92 | sound-dai = <&mcasp0>; | |
93 | system-clock-frequency = <24576000>; | |
94 | }; | |
95 | ||
96 | link0_codec: simple-audio-card,codec { | |
97 | sound-dai = <&tlv320aic3106>; | |
98 | system-clock-frequency = <24576000>; | |
99 | }; | |
100 | }; | |
e3d9e1eb BG |
101 | |
102 | gpio-keys { | |
103 | compatible = "gpio-keys"; | |
104 | autorepeat; | |
105 | ||
106 | user1 { | |
107 | label = "GPIO Key USER1"; | |
108 | linux,code = <BTN_0>; | |
109 | gpios = <&gpio 36 GPIO_ACTIVE_LOW>; | |
110 | }; | |
111 | ||
112 | user2 { | |
113 | label = "GPIO Key USER2"; | |
114 | linux,code = <BTN_1>; | |
115 | gpios = <&gpio 37 GPIO_ACTIVE_LOW>; | |
116 | }; | |
117 | }; | |
c9825344 BG |
118 | |
119 | vga-bridge { | |
120 | compatible = "ti,ths8135"; | |
121 | #address-cells = <1>; | |
122 | #size-cells = <0>; | |
123 | ||
124 | ports { | |
125 | #address-cells = <1>; | |
126 | #size-cells = <0>; | |
127 | ||
128 | port@0 { | |
129 | reg = <0>; | |
130 | ||
131 | vga_bridge_in: endpoint { | |
132 | remote-endpoint = <&lcdc_out_vga>; | |
133 | }; | |
134 | }; | |
135 | ||
136 | port@1 { | |
137 | reg = <1>; | |
138 | ||
139 | vga_bridge_out: endpoint { | |
140 | remote-endpoint = <&vga_con_in>; | |
141 | }; | |
142 | }; | |
143 | }; | |
144 | }; | |
145 | ||
146 | vga { | |
147 | compatible = "vga-connector"; | |
148 | ||
149 | ddc-i2c-bus = <&i2c0>; | |
150 | ||
151 | port { | |
152 | vga_con_in: endpoint { | |
153 | remote-endpoint = <&vga_bridge_out>; | |
154 | }; | |
155 | }; | |
156 | }; | |
44524a01 KB |
157 | }; |
158 | ||
3652e274 DL |
159 | &ref_clk { |
160 | clock-frequency = <24000000>; | |
161 | }; | |
162 | ||
44524a01 KB |
163 | &pmx_core { |
164 | status = "okay"; | |
9d05b389 KB |
165 | |
166 | mcasp0_pins: pinmux_mcasp0_pins { | |
167 | pinctrl-single,bits = < | |
168 | /* AHCLKX AFSX ACLKX */ | |
169 | 0x00 0x00101010 0x00f0f0f0 | |
170 | /* ARX13 ARX14 */ | |
171 | 0x04 0x00000110 0x00000ff0 | |
172 | >; | |
173 | }; | |
9304af1b KB |
174 | |
175 | nand_pins: nand_pins { | |
176 | pinctrl-single,bits = < | |
177 | /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ | |
178 | 0x1c 0x10110010 0xf0ff00f0 | |
179 | /* | |
180 | * EMA_D[0], EMA_D[1], EMA_D[2], | |
181 | * EMA_D[3], EMA_D[4], EMA_D[5], | |
182 | * EMA_D[6], EMA_D[7] | |
183 | */ | |
184 | 0x24 0x11111111 0xffffffff | |
185 | /* | |
186 | * EMA_D[8], EMA_D[9], EMA_D[10], | |
187 | * EMA_D[11], EMA_D[12], EMA_D[13], | |
188 | * EMA_D[14], EMA_D[15] | |
189 | */ | |
190 | 0x20 0x11111111 0xffffffff | |
191 | /* EMA_A[1], EMA_A[2] */ | |
192 | 0x30 0x01100000 0x0ff00000 | |
193 | >; | |
194 | }; | |
44524a01 KB |
195 | }; |
196 | ||
197 | &serial2 { | |
198 | pinctrl-names = "default"; | |
199 | pinctrl-0 = <&serial2_rxtx_pins>; | |
200 | status = "okay"; | |
201 | }; | |
202 | ||
203 | &wdt { | |
204 | status = "okay"; | |
205 | }; | |
206 | ||
207 | &rtc0 { | |
208 | status = "okay"; | |
209 | }; | |
210 | ||
211 | &gpio { | |
212 | status = "okay"; | |
213 | }; | |
214 | ||
3652e274 DL |
215 | &sata_refclk { |
216 | status = "okay"; | |
217 | clock-frequency = <100000000>; | |
218 | }; | |
219 | ||
91aba937 BG |
220 | &sata { |
221 | status = "okay"; | |
222 | }; | |
223 | ||
44524a01 KB |
224 | &mdio { |
225 | pinctrl-names = "default"; | |
226 | pinctrl-0 = <&mdio_pins>; | |
227 | bus_freq = <2200000>; | |
228 | status = "okay"; | |
229 | }; | |
230 | ||
231 | ð0 { | |
232 | pinctrl-names = "default"; | |
233 | pinctrl-0 = <&mii_pins>; | |
234 | status = "okay"; | |
235 | }; | |
236 | ||
237 | &mmc0 { | |
238 | max-frequency = <50000000>; | |
239 | bus-width = <4>; | |
240 | pinctrl-names = "default"; | |
241 | pinctrl-0 = <&mmc0_pins>; | |
a9aa4233 | 242 | cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; |
44524a01 KB |
243 | status = "okay"; |
244 | }; | |
9d05b389 KB |
245 | |
246 | &i2c0 { | |
247 | pinctrl-names = "default"; | |
248 | pinctrl-0 = <&i2c0_pins>; | |
249 | clock-frequency = <100000>; | |
250 | status = "okay"; | |
251 | ||
252 | tlv320aic3106: tlv320aic3106@18 { | |
253 | #sound-dai-cells = <0>; | |
254 | compatible = "ti,tlv320aic3106"; | |
255 | reg = <0x18>; | |
7dd2e8f8 PU |
256 | adc-settle-ms = <40>; |
257 | ai3x-micbias-vg = <1>; /* 2.0V */ | |
9d05b389 | 258 | status = "okay"; |
bd540ebe PU |
259 | |
260 | /* Regulators */ | |
261 | IOVDD-supply = <&vcc_3v3d>; | |
262 | AVDD-supply = <&vcc_3v3d>; | |
263 | DRVDD-supply = <&vcc_3v3d>; | |
264 | DVDD-supply = <&vcc_1v8d>; | |
9d05b389 KB |
265 | }; |
266 | }; | |
267 | ||
268 | &mcasp0 { | |
269 | #sound-dai-cells = <0>; | |
270 | pinctrl-names = "default"; | |
271 | pinctrl-0 = <&mcasp0_pins>; | |
272 | status = "okay"; | |
273 | ||
274 | op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ | |
275 | tdm-slots = <2>; | |
276 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | |
277 | 0 0 0 0 | |
278 | 0 0 0 0 | |
279 | 0 0 0 0 | |
280 | 0 1 2 0 | |
281 | >; | |
282 | tx-num-evt = <32>; | |
283 | rx-num-evt = <32>; | |
284 | }; | |
9304af1b | 285 | |
83de086c AB |
286 | &usb_phy { |
287 | status = "okay"; | |
288 | }; | |
289 | ||
290 | &usb0 { | |
291 | status = "okay"; | |
292 | }; | |
293 | ||
9e6612eb AH |
294 | &usb1 { |
295 | status = "okay"; | |
296 | }; | |
297 | ||
9304af1b KB |
298 | &aemif { |
299 | pinctrl-names = "default"; | |
300 | pinctrl-0 = <&nand_pins>; | |
301 | status = "okay"; | |
302 | cs3 { | |
303 | #address-cells = <2>; | |
304 | #size-cells = <1>; | |
305 | clock-ranges; | |
306 | ranges; | |
307 | ||
308 | ti,cs-chipselect = <3>; | |
309 | ||
310 | nand@2000000,0 { | |
311 | compatible = "ti,davinci-nand"; | |
312 | #address-cells = <1>; | |
313 | #size-cells = <1>; | |
314 | reg = <0 0x02000000 0x02000000 | |
315 | 1 0x00000000 0x00008000>; | |
316 | ||
317 | ti,davinci-chipselect = <1>; | |
318 | ti,davinci-mask-ale = <0>; | |
319 | ti,davinci-mask-cle = <0>; | |
320 | ti,davinci-mask-chipsel = <0>; | |
321 | ||
322 | ti,davinci-nand-buswidth = <16>; | |
323 | ti,davinci-ecc-mode = "hw"; | |
324 | ti,davinci-ecc-bits = <4>; | |
325 | ti,davinci-nand-use-bbt; | |
326 | ||
327 | /* | |
328 | * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: | |
329 | * "To boot from NAND Flash, the AIS should be written | |
330 | * to NAND block 1 (NAND block 0 is not used by default)". | |
331 | * The same doc mentions that for ROM "Silicon Revision 2.1", | |
332 | * "Updated NAND boot mode to offer boot from block 0 or block 1". | |
333 | * However the limitaion is left here by default for compatibility | |
334 | * with older silicon and because it needs new boot pin settings | |
335 | * not possible in stock LCDK. | |
336 | */ | |
337 | partitions { | |
338 | compatible = "fixed-partitions"; | |
339 | #address-cells = <1>; | |
340 | #size-cells = <1>; | |
341 | ||
342 | partition@0 { | |
343 | label = "u-boot env"; | |
344 | reg = <0 0x020000>; | |
345 | }; | |
7669b122 | 346 | partition@20000 { |
9304af1b KB |
347 | /* The LCDK defaults to booting from this partition */ |
348 | label = "u-boot"; | |
349 | reg = <0x020000 0x080000>; | |
350 | }; | |
7669b122 | 351 | partition@a0000 { |
9304af1b KB |
352 | label = "free space"; |
353 | reg = <0x0a0000 0>; | |
354 | }; | |
355 | }; | |
356 | }; | |
357 | }; | |
358 | }; | |
878e908a BG |
359 | |
360 | &prictrl { | |
361 | status = "okay"; | |
362 | }; | |
363 | ||
364 | &memctrl { | |
365 | status = "okay"; | |
366 | }; | |
c9825344 BG |
367 | |
368 | &lcdc { | |
369 | status = "okay"; | |
370 | pinctrl-names = "default"; | |
371 | pinctrl-0 = <&lcd_pins>; | |
372 | ||
373 | port { | |
374 | lcdc_out_vga: endpoint { | |
375 | remote-endpoint = <&vga_bridge_in>; | |
376 | }; | |
377 | }; | |
378 | }; | |
5280bc3e KH |
379 | |
380 | &vpif { | |
381 | pinctrl-names = "default"; | |
382 | pinctrl-0 = <&vpif_capture_pins>; | |
383 | status = "okay"; | |
5280bc3e | 384 | }; |
d9fe22b8 SA |
385 | |
386 | &dsp { | |
387 | memory-region = <&dsp_memory_region>; | |
388 | status = "okay"; | |
389 | }; |