[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / da850.dtsi

/*
 * Copyright 2012 DENX Software Engineering GmbH
 * Heiko Schocher <hs@denx.de>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	arm {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		intc: interrupt-controller@fffee000 {
			compatible = "ti,cp-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,intc-size = <101>;
			reg = <0xfffee000 0x2000>;
		};
	};
	soc@1c00000 {
		compatible = "simple-bus";
		model = "da850";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x01c00000 0x400000>;
		interrupt-parent = <&intc>;

		pmx_core: pinmux@14120 {
			compatible = "pinctrl-single";
			reg = <0x14120 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			#pinctrl-cells = <2>;
			pinctrl-single,bit-per-mux;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0xf>;
			status = "disabled";

			serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
				pinctrl-single,bits = <
					/* UART0_RTS UART0_CTS */
					0x0c 0x22000000 0xff000000
				>;
			};
			serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
				pinctrl-single,bits = <
					/* UART0_TXD UART0_RXD */
					0x0c 0x00220000 0x00ff0000
				>;
			};
			serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
				pinctrl-single,bits = <
					/* UART1_CTS UART1_RTS */
					0x00 0x00440000 0x00ff0000
				>;
			};
			serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
				pinctrl-single,bits = <
					/* UART1_TXD UART1_RXD */
					0x10 0x22000000 0xff000000
				>;
			};
			serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
				pinctrl-single,bits = <
					/* UART2_CTS UART2_RTS */
					0x00 0x44000000 0xff000000
				>;
			};
			serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
				pinctrl-single,bits = <
					/* UART2_TXD UART2_RXD */
					0x10 0x00220000 0x00ff0000
				>;
			};
			i2c0_pins: pinmux_i2c0_pins {
				pinctrl-single,bits = <
					/* I2C0_SDA,I2C0_SCL */
					0x10 0x00002200 0x0000ff00
				>;
			};
			i2c1_pins: pinmux_i2c1_pins {
				pinctrl-single,bits = <
					/* I2C1_SDA, I2C1_SCL */
					0x10 0x00440000 0x00ff0000
				>;
			};
			mmc0_pins: pinmux_mmc_pins {
				pinctrl-single,bits = <
					/* MMCSD0_DAT[3] MMCSD0_DAT[2]
					 * MMCSD0_DAT[1] MMCSD0_DAT[0]
					 * MMCSD0_CMD    MMCSD0_CLK
					 */
					0x28 0x00222222  0x00ffffff
				>;
			};
			ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
				pinctrl-single,bits = <
					/* EPWM0A */
					0xc 0x00000002 0x0000000f
				>;
			};
			ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
				pinctrl-single,bits = <
					/* EPWM0B */
					0xc 0x00000020 0x000000f0
				>;
			};
			ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
				pinctrl-single,bits = <
					/* EPWM1A */
					0x14 0x00000002 0x0000000f
				>;
			};
			ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
				pinctrl-single,bits = <
					/* EPWM1B */
					0x14 0x00000020 0x000000f0
				>;
			};
			ecap0_pins: pinmux_ecap0_pins {
				pinctrl-single,bits = <
					/* ECAP0_APWM0 */
					0x8 0x20000000 0xf0000000
				>;
			};
			ecap1_pins: pinmux_ecap1_pins {
				pinctrl-single,bits = <
					/* ECAP1_APWM1 */
					0x4 0x40000000 0xf0000000
				>;
			};
			ecap2_pins: pinmux_ecap2_pins {
				pinctrl-single,bits = <
					/* ECAP2_APWM2 */
					0x4 0x00000004 0x0000000f
				>;
			};
			spi0_pins: pinmux_spi0_pins {
				pinctrl-single,bits = <
					/* SIMO, SOMI, CLK */
					0xc 0x00001101 0x0000ff0f
				>;
			};
			spi0_cs0_pin: pinmux_spi0_cs0 {
				pinctrl-single,bits = <
					/* CS0 */
					0x10 0x00000010 0x000000f0
				>;
			};
			spi1_pins: pinmux_spi1_pins {
				pinctrl-single,bits = <
					/* SIMO, SOMI, CLK */
					0x14 0x00110100 0x00ff0f00
				>;
			};
			spi1_cs0_pin: pinmux_spi1_cs0 {
				pinctrl-single,bits = <
					/* CS0 */
					0x14 0x00000010 0x000000f0
				>;
			};
			mdio_pins: pinmux_mdio_pins {
				pinctrl-single,bits = <
					/* MDIO_CLK, MDIO_D */
					0x10 0x00000088 0x000000ff
				>;
			};
			mii_pins: pinmux_mii_pins {
				pinctrl-single,bits = <
					/*
					 * MII_TXEN, MII_TXCLK, MII_COL
					 * MII_TXD_3, MII_TXD_2, MII_TXD_1
					 * MII_TXD_0
					 */
					0x8 0x88888880 0xfffffff0
					/*
					 * MII_RXER, MII_CRS, MII_RXCLK
					 * MII_RXDV, MII_RXD_3, MII_RXD_2
					 * MII_RXD_1, MII_RXD_0
					 */
					0xc 0x88888888 0xffffffff
				>;
			};
			lcd_pins: pinmux_lcd_pins {
				pinctrl-single,bits = <
					/*
					 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
					 * LCD_D[6], LCD_D[7]
					 */
					0x40 0x22222200 0xffffff00
					/*
					 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
					 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
					 */
					0x44 0x22222222 0xffffffff
					/* LCD_D[8], LCD_D[9] */
					0x48 0x00000022 0x000000ff

					/* LCD_PCLK */
					0x48 0x02000000 0x0f000000
					/* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
					0x4c 0x02000022 0x0f0000ff
				>;
			};

		};
		prictrl: priority-controller@14110 {
			compatible = "ti,da850-mstpri";
			reg = <0x14110 0x0c>;
			status = "disabled";
		};
		cfgchip: chip-controller@1417c {
			compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
			reg = <0x1417c 0x14>;

			usb_phy: usb-phy {
				compatible = "ti,da830-usb-phy";
				#phy-cells = <1>;
				status = "disabled";
			};
		};
		edma0: edma@0 {
			compatible = "ti,edma3-tpcc";
			/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
			reg =	<0x0 0x8000>;
			reg-names = "edma3_cc";
			interrupts = <11 12>;
			interrupt-names = "edma3_ccint", "edma3_ccerrint";
			#dma-cells = <2>;

			ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
		};
		edma0_tptc0: tptc@8000 {
			compatible = "ti,edma3-tptc";
			reg =	<0x8000 0x400>;
			interrupts = <13>;
			interrupt-names = "edm3_tcerrint";
		};
		edma0_tptc1: tptc@8400 {
			compatible = "ti,edma3-tptc";
			reg =	<0x8400 0x400>;
			interrupts = <32>;
			interrupt-names = "edm3_tcerrint";
		};
		edma1: edma@230000 {
			compatible = "ti,edma3-tpcc";
			/* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
			reg =	<0x230000 0x8000>;
			reg-names = "edma3_cc";
			interrupts = <93 94>;
			interrupt-names = "edma3_ccint", "edma3_ccerrint";
			#dma-cells = <2>;

			ti,tptcs = <&edma1_tptc0 7>;
		};
		edma1_tptc0: tptc@238000 {
			compatible = "ti,edma3-tptc";
			reg =	<0x238000 0x400>;
			interrupts = <95>;
			interrupt-names = "edm3_tcerrint";
		};
		serial0: serial@42000 {
			compatible = "ns16550a";
			reg = <0x42000 0x100>;
			reg-shift = <2>;
			interrupts = <25>;
			status = "disabled";
		};
		serial1: serial@10c000 {
			compatible = "ns16550a";
			reg = <0x10c000 0x100>;
			reg-shift = <2>;
			interrupts = <53>;
			status = "disabled";
		};
		serial2: serial@10d000 {
			compatible = "ns16550a";
			reg = <0x10d000 0x100>;
			reg-shift = <2>;
			interrupts = <61>;
			status = "disabled";
		};
		rtc0: rtc@23000 {
			compatible = "ti,da830-rtc";
			reg = <0x23000 0x1000>;
			interrupts = <19
				      19>;
			status = "disabled";
		};
		i2c0: i2c@22000 {
			compatible = "ti,davinci-i2c";
			reg = <0x22000 0x1000>;
			interrupts = <15>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		i2c1: i2c@228000 {
			compatible = "ti,davinci-i2c";
			reg = <0x228000 0x1000>;
			interrupts = <51>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		wdt: wdt@21000 {
			compatible = "ti,davinci-wdt";
			reg = <0x21000 0x1000>;
			status = "disabled";
		};
		mmc0: mmc@40000 {
			compatible = "ti,da830-mmc";
			reg = <0x40000 0x1000>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			interrupts = <16>;
			dmas = <&edma0 16 0>, <&edma0 17 0>;
			dma-names = "rx", "tx";
			status = "disabled";
		};
		mmc1: mmc@21b000 {
			compatible = "ti,da830-mmc";
			reg = <0x21b000 0x1000>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			interrupts = <72>;
			dmas = <&edma1 28 0>, <&edma1 29 0>;
			dma-names = "rx", "tx";
			status = "disabled";
		};
		ehrpwm0: pwm@300000 {
			compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
				     "ti,am33xx-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x300000 0x2000>;
			status = "disabled";
		};
		ehrpwm1: pwm@302000 {
			compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
				     "ti,am33xx-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x302000 0x2000>;
			status = "disabled";
		};
		ecap0: ecap@306000 {
			compatible = "ti,da850-ecap", "ti,am3352-ecap",
				     "ti,am33xx-ecap";
			#pwm-cells = <3>;
			reg = <0x306000 0x80>;
			status = "disabled";
		};
		ecap1: ecap@307000 {
			compatible = "ti,da850-ecap", "ti,am3352-ecap",
				     "ti,am33xx-ecap";
			#pwm-cells = <3>;
			reg = <0x307000 0x80>;
			status = "disabled";
		};
		ecap2: ecap@308000 {
			compatible = "ti,da850-ecap", "ti,am3352-ecap",
				     "ti,am33xx-ecap";
			#pwm-cells = <3>;
			reg = <0x308000 0x80>;
			status = "disabled";
		};
		spi0: spi@41000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "ti,da830-spi";
			reg = <0x41000 0x1000>;
			num-cs = <6>;
			ti,davinci-spi-intr-line = <1>;
			interrupts = <20>;
			dmas = <&edma0 14 0>, <&edma0 15 0>;
			dma-names = "rx", "tx";
			status = "disabled";
		};
		spi1: spi@30e000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "ti,da830-spi";
			reg = <0x30e000 0x1000>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <1>;
			interrupts = <56>;
			dmas = <&edma0 18 0>, <&edma0 19 0>;
			dma-names = "rx", "tx";
			status = "disabled";
		};
		usb0: usb@200000 {
			compatible = "ti,da830-musb";
			reg = <0x200000 0x10000>;
			interrupts = <58>;
			interrupt-names = "mc";
			dr_mode = "otg";
			phys = <&usb_phy 0>;
			phy-names = "usb-phy";
			status = "disabled";
		};
		mdio: mdio@224000 {
			compatible = "ti,davinci_mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x224000 0x1000>;
			status = "disabled";
		};
		eth0: ethernet@220000 {
			compatible = "ti,davinci-dm6467-emac";
			reg = <0x220000 0x4000>;
			ti,davinci-ctrl-reg-offset = <0x3000>;
			ti,davinci-ctrl-mod-reg-offset = <0x2000>;
			ti,davinci-ctrl-ram-offset = <0>;
			ti,davinci-ctrl-ram-size = <0x2000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <33
					34
					35
					36
					>;
			status = "disabled";
		};
		gpio: gpio@226000 {
			compatible = "ti,dm6441-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x226000 0x1000>;
			interrupts = <42 IRQ_TYPE_EDGE_BOTH
				43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
				45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
				47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
				49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
			ti,ngpio = <144>;
			ti,davinci-gpio-unbanked = <0>;
			status = "disabled";
		};
		pinconf: pin-controller@22c00c {
			compatible = "ti,da850-pupd";
			reg = <0x22c00c 0x8>;
			status = "disabled";
		};

		mcasp0: mcasp@100000 {
			compatible = "ti,da830-mcasp-audio";
			reg = <0x100000 0x2000>,
			      <0x102000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <54>;
			interrupt-names = "common";
			status = "disabled";
			dmas = <&edma0 1 1>,
				<&edma0 0 1>;
			dma-names = "tx", "rx";
		};

		display: display@213000 {
			compatible = "ti,da850-tilcdc";
			reg = <0x213000 0x1000>;
			interrupts = <52>;
			status = "disabled";
		};
	};
	aemif: aemif@68000000 {
		compatible = "ti,da850-aemif";
		#address-cells = <2>;
		#size-cells = <1>;

		reg = <0x68000000 0x00008000>;
		ranges = <0 0 0x60000000 0x08000000
			  1 0 0x68000000 0x00008000>;
		status = "disabled";
	};
	memctrl: memory-controller@b0000000 {
		compatible = "ti,da850-ddr-controller";
		reg = <0xb0000000 0xe8>;
		status = "disabled";
	};
};
Commit	Line	Data
33085b3e HS	1	/*
	2	* Copyright 2012 DENX Software Engineering GmbH
	3	* Heiko Schocher <hs@denx.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
a2bcd776	10	#include "skeleton.dtsi"
2e38b946	11	#include <dt-bindings/interrupt-controller/irq.h>
33085b3e HS	12
	13	/ {
	14	arm {
	15	#address-cells = <1>;
	16	#size-cells = <1>;
	17	ranges;
c2a3b4bc	18	intc: interrupt-controller@fffee000 {
33085b3e HS	19	compatible = "ti,cp-intc";
	20	interrupt-controller;
	21	#interrupt-cells = <1>;
c6d3b5dd	22	ti,intc-size = <101>;
33085b3e HS	23	reg = <0xfffee000 0x2000>;
	24	};
	25	};
c2a3b4bc	26	soc@1c00000 {
33085b3e HS	27	compatible = "simple-bus";
	28	model = "da850";
	29	#address-cells = <1>;
	30	#size-cells = <1>;
	31	ranges = <0x0 0x01c00000 0x400000>;
c57ff58d	32	interrupt-parent = <&intc>;
33085b3e	33
c2a3b4bc	34	pmx_core: pinmux@14120 {
1faaba3d KA	35	compatible = "pinctrl-single";
	36	reg = <0x14120 0x50>;
	37	#address-cells = <1>;
	38	#size-cells = <0>;
be76fd31	39	#pinctrl-cells = <2>;
1faaba3d KA	40	pinctrl-single,bit-per-mux;
1faaba3d KA	41	pinctrl-single,register-width = <32>;
055cb2a9	42	pinctrl-single,function-mask = <0xf>;
1faaba3d	43	status = "disabled";
99b8800c	44
10ead752 KB	45	serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
	46	pinctrl-single,bits = <
	47	/* UART0_RTS UART0_CTS */
	48	0x0c 0x22000000 0xff000000
	49	>;
	50	};
	51	serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
	52	pinctrl-single,bits = <
	53	/* UART0_TXD UART0_RXD */
	54	0x0c 0x00220000 0x00ff0000
	55	>;
	56	};
	57	serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
	58	pinctrl-single,bits = <
	59	/* UART1_CTS UART1_RTS */
	60	0x00 0x00440000 0x00ff0000
	61	>;
	62	};
	63	serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
	64	pinctrl-single,bits = <
	65	/* UART1_TXD UART1_RXD */
	66	0x10 0x22000000 0xff000000
	67	>;
	68	};
	69	serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
	70	pinctrl-single,bits = <
	71	/* UART2_CTS UART2_RTS */
	72	0x00 0x44000000 0xff000000
	73	>;
	74	};
	75	serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
	76	pinctrl-single,bits = <
	77	/* UART2_TXD UART2_RXD */
	78	0x10 0x00220000 0x00ff0000
	79	>;
	80	};
01729ccf VBM	81	i2c0_pins: pinmux_i2c0_pins {
	82	pinctrl-single,bits = <
	83	/* I2C0_SDA,I2C0_SCL */
	84	0x10 0x00002200 0x0000ff00
	85	>;
	86	};
92d64642 PK	87	i2c1_pins: pinmux_i2c1_pins {
	88	pinctrl-single,bits = <
	89	/* I2C1_SDA, I2C1_SCL */
	90	0x10 0x00440000 0x00ff0000
	91	>;
	92	};
88df4122 MP	93	mmc0_pins: pinmux_mmc_pins {
	94	pinctrl-single,bits = <
	95	/* MMCSD0_DAT[3] MMCSD0_DAT[2]
	96	* MMCSD0_DAT[1] MMCSD0_DAT[0]
	97	* MMCSD0_CMD MMCSD0_CLK
	98	*/
	99	0x28 0x00222222 0x00ffffff
	100	>;
	101	};
64fa59c4 PA	102	ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
	103	pinctrl-single,bits = <
	104	/* EPWM0A */
	105	0xc 0x00000002 0x0000000f
	106	>;
	107	};
	108	ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
	109	pinctrl-single,bits = <
	110	/* EPWM0B */
	111	0xc 0x00000020 0x000000f0
	112	>;
	113	};
	114	ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
	115	pinctrl-single,bits = <
	116	/* EPWM1A */
	117	0x14 0x00000002 0x0000000f
	118	>;
	119	};
	120	ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
	121	pinctrl-single,bits = <
	122	/* EPWM1B */
	123	0x14 0x00000020 0x000000f0
	124	>;
	125	};
	126	ecap0_pins: pinmux_ecap0_pins {
	127	pinctrl-single,bits = <
	128	/* ECAP0_APWM0 */
	129	0x8 0x20000000 0xf0000000
	130	>;
	131	};
	132	ecap1_pins: pinmux_ecap1_pins {
	133	pinctrl-single,bits = <
	134	/* ECAP1_APWM1 */
	135	0x4 0x40000000 0xf0000000
	136	>;
	137	};
	138	ecap2_pins: pinmux_ecap2_pins {
	139	pinctrl-single,bits = <
	140	/* ECAP2_APWM2 */
	141	0x4 0x00000004 0x0000000f
	142	>;
	143	};
4be4b28a DL	144	spi0_pins: pinmux_spi0_pins {
	145	pinctrl-single,bits = <
	146	/* SIMO, SOMI, CLK */
	147	0xc 0x00001101 0x0000ff0f
	148	>;
	149	};
	150	spi0_cs0_pin: pinmux_spi0_cs0 {
	151	pinctrl-single,bits = <
	152	/* CS0 */
	153	0x10 0x00000010 0x000000f0
	154	>;
	155	};
	156	spi1_pins: pinmux_spi1_pins {
c6347e48 MP	157	pinctrl-single,bits = <
	158	/* SIMO, SOMI, CLK */
	159	0x14 0x00110100 0x00ff0f00
	160	>;
	161	};
	162	spi1_cs0_pin: pinmux_spi1_cs0 {
	163	pinctrl-single,bits = <
	164	/* CS0 */
	165	0x14 0x00000010 0x000000f0
	166	>;
	167	};
609f4bcf LP	168	mdio_pins: pinmux_mdio_pins {
	169	pinctrl-single,bits = <
	170	/* MDIO_CLK, MDIO_D */
	171	0x10 0x00000088 0x000000ff
	172	>;
	173	};
dd7deaf2 LP	174	mii_pins: pinmux_mii_pins {
	175	pinctrl-single,bits = <
	176	/*
	177	* MII_TXEN, MII_TXCLK, MII_COL
	178	* MII_TXD_3, MII_TXD_2, MII_TXD_1
	179	* MII_TXD_0
	180	*/
	181	0x8 0x88888880 0xfffffff0
	182	/*
	183	* MII_RXER, MII_CRS, MII_RXCLK
	184	* MII_RXDV, MII_RXD_3, MII_RXD_2
	185	* MII_RXD_1, MII_RXD_0
	186	*/
	187	0xc 0x88888888 0xffffffff
	188	>;
	189	};
f28b7824 KB	190	lcd_pins: pinmux_lcd_pins {
	191	pinctrl-single,bits = <
	192	/*
	193	* LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
	194	* LCD_D[6], LCD_D[7]
	195	*/
	196	0x40 0x22222200 0xffffff00
	197	/*
	198	* LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
	199	* LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
	200	*/
	201	0x44 0x22222222 0xffffffff
	202	/* LCD_D[8], LCD_D[9] */
	203	0x48 0x00000022 0x000000ff
	204
	205	/* LCD_PCLK */
	206	0x48 0x02000000 0x0f000000
	207	/* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
	208	0x4c 0x02000022 0x0f0000ff
	209	>;
	210	};
609f4bcf	211
1faaba3d	212	};
f3d47fc9 BG	213	prictrl: priority-controller@14110 {
	214	compatible = "ti,da850-mstpri";
	215	reg = <0x14110 0x0c>;
878e908a	216	status = "disabled";
f3d47fc9	217	};
1b499f25 DL	218	cfgchip: chip-controller@1417c {
	219	compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
	220	reg = <0x1417c 0x14>;
	221
	222	usb_phy: usb-phy {
	223	compatible = "ti,da830-usb-phy";
	224	#phy-cells = <1>;
	225	status = "disabled";
	226	};
	227	};
c2a3b4bc	228	edma0: edma@0 {
7a7faedd	229	compatible = "ti,edma3-tpcc";
dfaebb50 PU	230	/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
dfaebb50 PU	231	reg = <0x0 0x8000>;
7a7faedd PU	232	reg-names = "edma3_cc";
	233	interrupts = <11 12>;
	234	interrupt-names = "edma3_ccint", "edma3_ccerrint";
	235	#dma-cells = <2>;
	236
	237	ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
	238	};
c2a3b4bc	239	edma0_tptc0: tptc@8000 {
7a7faedd PU	240	compatible = "ti,edma3-tptc";
	241	reg = <0x8000 0x400>;
	242	interrupts = <13>;
	243	interrupt-names = "edm3_tcerrint";
	244	};
c2a3b4bc	245	edma0_tptc1: tptc@8400 {
7a7faedd PU	246	compatible = "ti,edma3-tptc";
	247	reg = <0x8400 0x400>;
	248	interrupts = <32>;
	249	interrupt-names = "edm3_tcerrint";
ee766e4d	250	};
c2a3b4bc	251	edma1: edma@230000 {
b47a8560 PU	252	compatible = "ti,edma3-tpcc";
	253	/* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
	254	reg = <0x230000 0x8000>;
	255	reg-names = "edma3_cc";
	256	interrupts = <93 94>;
	257	interrupt-names = "edma3_ccint", "edma3_ccerrint";
	258	#dma-cells = <2>;
	259
	260	ti,tptcs = <&edma1_tptc0 7>;
	261	};
c2a3b4bc	262	edma1_tptc0: tptc@238000 {
b47a8560 PU	263	compatible = "ti,edma3-tptc";
	264	reg = <0x238000 0x400>;
	265	interrupts = <95>;
	266	interrupt-names = "edm3_tcerrint";
	267	};
c2a3b4bc	268	serial0: serial@42000 {
33085b3e HS	269	compatible = "ns16550a";
33085b3e HS	270	reg = <0x42000 0x100>;
33085b3e HS	271	reg-shift = <2>;
33085b3e HS	272	interrupts = <25>;
33085b3e HS	273	status = "disabled";
33085b3e HS	274	};
c2a3b4bc	275	serial1: serial@10c000 {
33085b3e HS	276	compatible = "ns16550a";
33085b3e HS	277	reg = <0x10c000 0x100>;
33085b3e HS	278	reg-shift = <2>;
33085b3e HS	279	interrupts = <53>;
33085b3e HS	280	status = "disabled";
33085b3e HS	281	};
c2a3b4bc	282	serial2: serial@10d000 {
33085b3e HS	283	compatible = "ns16550a";
33085b3e HS	284	reg = <0x10d000 0x100>;
33085b3e HS	285	reg-shift = <2>;
33085b3e HS	286	interrupts = <61>;
33085b3e HS	287	status = "disabled";
33085b3e HS	288	};
c2a3b4bc	289	rtc0: rtc@23000 {
1661636d MK	290	compatible = "ti,da830-rtc";
	291	reg = <0x23000 0x1000>;
	292	interrupts = <19
	293	19>;
	294	status = "disabled";
	295	};
c2a3b4bc	296	i2c0: i2c@22000 {
01729ccf VBM	297	compatible = "ti,davinci-i2c";
	298	reg = <0x22000 0x1000>;
	299	interrupts = <15>;
	300	#address-cells = <1>;
	301	#size-cells = <0>;
	302	status = "disabled";
	303	};
92d64642 PK	304	i2c1: i2c@228000 {
	305	compatible = "ti,davinci-i2c";
	306	reg = <0x228000 0x1000>;
	307	interrupts = <51>;
	308	#address-cells = <1>;
	309	#size-cells = <0>;
	310	status = "disabled";
	311	};
c2a3b4bc	312	wdt: wdt@21000 {
518f97db KA	313	compatible = "ti,davinci-wdt";
	314	reg = <0x21000 0x1000>;
	315	status = "disabled";
	316	};
c2a3b4bc	317	mmc0: mmc@40000 {
88df4122 MP	318	compatible = "ti,da830-mmc";
88df4122 MP	319	reg = <0x40000 0x1000>;
e4ce904d AH	320	cap-sd-highspeed;
e4ce904d AH	321	cap-mmc-highspeed;
88df4122	322	interrupts = <16>;
684892a2 PU	323	dmas = <&edma0 16 0>, <&edma0 17 0>;
684892a2 PU	324	dma-names = "rx", "tx";
88df4122 MP	325	status = "disabled";
88df4122 MP	326	};
c2a3b4bc	327	mmc1: mmc@21b000 {
3c497582 PU	328	compatible = "ti,da830-mmc";
3c497582 PU	329	reg = <0x21b000 0x1000>;
e4ce904d AH	330	cap-sd-highspeed;
e4ce904d AH	331	cap-mmc-highspeed;
3c497582 PU	332	interrupts = <72>;
	333	dmas = <&edma1 28 0>, <&edma1 29 0>;
	334	dma-names = "rx", "tx";
	335	status = "disabled";
	336	};
1ea7c8b6	337	ehrpwm0: pwm@300000 {
38b8da79 CJF	338	compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
38b8da79 CJF	339	"ti,am33xx-ehrpwm";
64fa59c4 PA	340	#pwm-cells = <3>;
	341	reg = <0x300000 0x2000>;
	342	status = "disabled";
	343	};
1ea7c8b6	344	ehrpwm1: pwm@302000 {
38b8da79 CJF	345	compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
38b8da79 CJF	346	"ti,am33xx-ehrpwm";
64fa59c4 PA	347	#pwm-cells = <3>;
	348	reg = <0x302000 0x2000>;
	349	status = "disabled";
	350	};
c2a3b4bc	351	ecap0: ecap@306000 {
38b8da79 CJF	352	compatible = "ti,da850-ecap", "ti,am3352-ecap",
38b8da79 CJF	353	"ti,am33xx-ecap";
64fa59c4 PA	354	#pwm-cells = <3>;
	355	reg = <0x306000 0x80>;
	356	status = "disabled";
	357	};
c2a3b4bc	358	ecap1: ecap@307000 {
38b8da79 CJF	359	compatible = "ti,da850-ecap", "ti,am3352-ecap",
38b8da79 CJF	360	"ti,am33xx-ecap";
64fa59c4 PA	361	#pwm-cells = <3>;
	362	reg = <0x307000 0x80>;
	363	status = "disabled";
	364	};
c2a3b4bc	365	ecap2: ecap@308000 {
38b8da79 CJF	366	compatible = "ti,da850-ecap", "ti,am3352-ecap",
38b8da79 CJF	367	"ti,am33xx-ecap";
64fa59c4 PA	368	#pwm-cells = <3>;
	369	reg = <0x308000 0x80>;
	370	status = "disabled";
	371	};
4be4b28a DL	372	spi0: spi@41000 {
	373	#address-cells = <1>;
	374	#size-cells = <0>;
	375	compatible = "ti,da830-spi";
	376	reg = <0x41000 0x1000>;
	377	num-cs = <6>;
	378	ti,davinci-spi-intr-line = <1>;
	379	interrupts = <20>;
b5028b28 DL	380	dmas = <&edma0 14 0>, <&edma0 15 0>;
b5028b28 DL	381	dma-names = "rx", "tx";
4be4b28a DL	382	status = "disabled";
4be4b28a DL	383	};
c2a3b4bc	384	spi1: spi@30e000 {
c6347e48 MP	385	#address-cells = <1>;
	386	#size-cells = <0>;
	387	compatible = "ti,da830-spi";
	388	reg = <0x30e000 0x1000>;
	389	num-cs = <4>;
	390	ti,davinci-spi-intr-line = <1>;
	391	interrupts = <56>;
f0ad4353 PU	392	dmas = <&edma0 18 0>, <&edma0 19 0>;
f0ad4353 PU	393	dma-names = "rx", "tx";
c6347e48 MP	394	status = "disabled";
c6347e48 MP	395	};
2957e36e AB	396	usb0: usb@200000 {
	397	compatible = "ti,da830-musb";
	398	reg = <0x200000 0x10000>;
	399	interrupts = <58>;
	400	interrupt-names = "mc";
	401	dr_mode = "otg";
	402	phys = <&usb_phy 0>;
	403	phy-names = "usb-phy";
	404	status = "disabled";
	405	};
c2a3b4bc	406	mdio: mdio@224000 {
609f4bcf LP	407	compatible = "ti,davinci_mdio";
	408	#address-cells = <1>;
	409	#size-cells = <0>;
	410	reg = <0x224000 0x1000>;
5209a8f1	411	status = "disabled";
609f4bcf	412	};
c2a3b4bc	413	eth0: ethernet@220000 {
dd7deaf2 LP	414	compatible = "ti,davinci-dm6467-emac";
	415	reg = <0x220000 0x4000>;
	416	ti,davinci-ctrl-reg-offset = <0x3000>;
	417	ti,davinci-ctrl-mod-reg-offset = <0x2000>;
	418	ti,davinci-ctrl-ram-offset = <0>;
	419	ti,davinci-ctrl-ram-size = <0x2000>;
	420	local-mac-address = [ 00 00 00 00 00 00 ];
	421	interrupts = <33
	422	34
	423	35
	424	36
	425	>;
5209a8f1	426	status = "disabled";
dd7deaf2	427	};
c2a3b4bc	428	gpio: gpio@226000 {
2e38b946 KS	429	compatible = "ti,dm6441-gpio";
2e38b946 KS	430	gpio-controller;
497762b8	431	#gpio-cells = <2>;
2e38b946 KS	432	reg = <0x226000 0x1000>;
	433	interrupts = <42 IRQ_TYPE_EDGE_BOTH
	434	43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
	435	45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
	436	47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
	437	49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
	438	ti,ngpio = <144>;
	439	ti,davinci-gpio-unbanked = <0>;
	440	status = "disabled";
	441	};
7937038a DL	442	pinconf: pin-controller@22c00c {
	443	compatible = "ti,da850-pupd";
	444	reg = <0x22c00c 0x8>;
	445	status = "disabled";
	446	};
db74904e	447
c2a3b4bc	448	mcasp0: mcasp@100000 {
db74904e PU	449	compatible = "ti,da830-mcasp-audio";
	450	reg = <0x100000 0x2000>,
	451	<0x102000 0x400000>;
	452	reg-names = "mpu", "dat";
	453	interrupts = <54>;
	454	interrupt-names = "common";
	455	status = "disabled";
7a7faedd PU	456	dmas = <&edma0 1 1>,
7a7faedd PU	457	<&edma0 0 1>;
db74904e PU	458	dma-names = "tx", "rx";
db74904e PU	459	};
f28b7824 KB	460
	461	display: display@213000 {
	462	compatible = "ti,da850-tilcdc";
	463	reg = <0x213000 0x1000>;
	464	interrupts = <52>;
	465	status = "disabled";
	466	};
33085b3e	467	};
31e3a881 KB	468	aemif: aemif@68000000 {
	469	compatible = "ti,da850-aemif";
	470	#address-cells = <2>;
	471	#size-cells = <1>;
	472
	473	reg = <0x68000000 0x00008000>;
	474	ranges = <0 0 0x60000000 0x08000000
	475	1 0 0x68000000 0x00008000>;
99b8800c KA	476	status = "disabled";
99b8800c KA	477	};
f3d47fc9 BG	478	memctrl: memory-controller@b0000000 {
	479	compatible = "ti,da850-ddr-controller";
	480	reg = <0xb0000000 0xe8>;
878e908a	481	status = "disabled";
f3d47fc9	482	};
33085b3e	483	};